1 files changed, 110 insertions, 0 deletions
diff --git a/doc/supplements/powerpc/memmodel.t b/doc/supplements/powerpc/memmodel.t
new file mode 100644
index 0000000000..13341696cf
--- /dev/null
+++ b/doc/supplements/powerpc/memmodel.t
@@ -0,0 +1,110 @@
+@c
+@c  COPYRIGHT (c) 1988-2002.
+@c  On-Line Applications Research Corporation (OAR).
+@c  All rights reserved.
+@c
+@c  $Id$
+@c
+
+@chapter Memory Model
+
+@section Introduction
+
+A processor may support any combination of memory
+models ranging from pure physical addressing to complex demand
+paged virtual memory systems.  RTEMS supports a flat memory
+model which ranges contiguously over the processor's allowable
+address space.  RTEMS does not support segmentation or virtual
+memory of any kind.  The appropriate memory model for RTEMS
+provided by the targeted processor and related characteristics
+of that model are described in this chapter.
+
+@section Flat Memory Model
+
+The PowerPC architecture supports a variety of memory models.
+RTEMS supports the PowerPC using a flat memory model with 
+paging disabled.  In this mode, the PowerPC automatically
+converts every address from a logical to a physical address
+each time it is used.  The PowerPC uses information provided
+in the Block Address Translation (BAT) to convert these addresses.
+
+Implementations of the PowerPC architecture may be thirty-two or sixty-four bit.
+The PowerPC architecture supports a flat thirty-two or sixty-four bit address
+space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
+gigabytes) in thirty-two bit implementations or to 0xFFFFFFFFFFFFFFFF 
+in sixty-four bit implementations.  Each address is represented
+by either a thirty-two bit or sixty-four bit value and is byte addressable.  
+The address may be used to reference a single byte, half-word
+(2-bytes), word (4 bytes), or in sixty-four bit implementations a
+doubleword (8 bytes).  Memory accesses within the address space are
+performed in big or little endian fashion by the PowerPC based
+upon the current setting of the Little-endian mode enable bit (LE)
+in the Machine State Register (MSR).  While the processor is in
+big endian mode, memory accesses which are not properly aligned
+generate an "alignment exception" (vector offset 0x00600).  In
+little endian mode, the PowerPC architecture does not require
+the processor to generate alignment exceptions.
+
+The following table lists the alignment requirements for a variety
+of data accesses:
+
+@ifset use-ascii
+@example
+@group
+          +--------------+-----------------------+
+          |   Data Type  | Alignment Requirement |
+          +--------------+-----------------------+
+          |     byte     |          1            |
+          |   half-word  |          2            |
+          |     word     |          4            |
+          |  doubleword  |          8            |
+          +--------------+-----------------------+
+@end group
+@end example
+@end ifset
+
+@ifset use-tex
+@sp 1
+@tex
+\centerline{\vbox{\offinterlineskip\halign{
+\vrule\strut#&
+\hbox to 1.75in{\enskip\hfil#\hfil}&
+\vrule#&
+\hbox to 1.75in{\enskip\hfil#\hfil}&
+\vrule#\cr
+\noalign{\hrule}
+&\bf Data Type &&\bf Alignment Requirement&\cr\noalign{\hrule}
+&byte&&1&\cr\noalign{\hrule}
+&half-word&&2&\cr\noalign{\hrule}
+&word&&4&\cr\noalign{\hrule}
+&doubleword&&8&\cr\noalign{\hrule}
+}}\hfil}
+@end tex
+@end ifset
+ 
+@ifset use-html
+@html
+<CENTER>
+  <TABLE COLS=2 WIDTH="60%" BORDER=2>
+<TR><TD ALIGN=center><STRONG>Data Type</STRONG></TD>
+    <TD ALIGN=center><STRONG>Alignment Requirement</STRONG></TD></TR>
+<TR><TD ALIGN=center>byte</TD>
+    <TD ALIGN=center>1</TD></TR>
+<TR><TD ALIGN=center>half-word</TD>
+    <TD ALIGN=center>2</TD></TR>
+<TR><TD ALIGN=center>word</TD>
+    <TD ALIGN=center>4</TD></TR>
+<TR><TD ALIGN=center>doubleword</TD>
+    <TD ALIGN=center>8</TD></TR>
+  </TABLE>
+</CENTER>
+@end html
+@end ifset
+
+Doubleword load and store operations are only available in 
+PowerPC CPU models which are sixty-four bit implementations.
+
+RTEMS does not directly support any PowerPC Memory Management
+Units, therefore, virtual memory or segmentation systems
+involving the PowerPC  are not supported.
+