diff options
Diffstat (limited to 'cpukit')
| -rw-r--r-- | cpukit/score/cpu/microblaze/__tls_get_addr.c | 54 | ||||
| -rw-r--r-- | cpukit/score/cpu/microblaze/cpu.c | 192 | ||||
| -rw-r--r-- | cpukit/score/cpu/microblaze/cpu_asm.S | 194 | ||||
| -rw-r--r-- | cpukit/score/cpu/microblaze/include/rtems/asm.h (renamed from cpukit/score/cpu/microblaze/rtems/asm.h) | 51 | ||||
| -rw-r--r-- | cpukit/score/cpu/microblaze/include/rtems/score/cpu.h | 305 | ||||
| -rw-r--r-- | cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h | 41 | ||||
| -rw-r--r-- | cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h | 96 | ||||
| -rw-r--r-- | cpukit/score/cpu/microblaze/include/rtems/score/microblaze.h (renamed from cpukit/score/cpu/microblaze/rtems/score/microblaze.h) | 70 | ||||
| -rw-r--r-- | cpukit/score/cpu/microblaze/microblaze-context-switch.S | 25 | ||||
| -rw-r--r-- | cpukit/score/cpu/microblaze/microblaze-context-validate.S | 117 | ||||
| -rw-r--r-- | cpukit/score/cpu/microblaze/microblaze-context-volatile-clobber.S | 28 | ||||
| -rw-r--r-- | cpukit/score/cpu/microblaze/rtems/score/cpu.h | 1280 |
12 files changed, 963 insertions, 1490 deletions
diff --git a/cpukit/score/cpu/microblaze/__tls_get_addr.c b/cpukit/score/cpu/microblaze/__tls_get_addr.c new file mode 100644 index 0000000000..e779a63488 --- /dev/null +++ b/cpukit/score/cpu/microblaze/__tls_get_addr.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPUMicroBlaze + * + * @brief MicroBlaze thread-local storage implementation + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/score/threadimpl.h> +#include <rtems/score/tls.h> + +#include <assert.h> + +void *__tls_get_addr( const TLS_Index *ti ); + +void *__tls_get_addr( const TLS_Index *ti ) +{ + const Thread_Control *executing = _Thread_Get_executing(); + void *tls_block = (char *) executing->Start.tls_area + + _TLS_Get_thread_control_block_area_size( (uintptr_t) _TLS_Alignment ); + + return (char *) tls_block + ti->offset; +} diff --git a/cpukit/score/cpu/microblaze/cpu.c b/cpukit/score/cpu/microblaze/cpu.c index ca4a3ec2f6..de8fbfbba1 100644 --- a/cpukit/score/cpu/microblaze/cpu.c +++ b/cpukit/score/cpu/microblaze/cpu.c @@ -1,7 +1,16 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPUMicroBlaze + * + * @brief MicroBlaze architecture support implementation + */ + /* - * Copyright (c) 2015, Hesham Almatary - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). + * Copyright (c) 2015, Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -9,8 +18,8 @@ * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE @@ -29,31 +38,12 @@ #include "config.h" #endif -#include <rtems/system.h> #include <rtems/score/isr.h> +#include <rtems/score/tls.h> #include <rtems/score/wkspace.h> -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: NONE - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Initialize(void) +void _CPU_Initialize( void ) { - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ } void _CPU_Context_Initialize( @@ -66,136 +56,66 @@ void _CPU_Context_Initialize( void *tls_area ) { - uint32_t stack = ((uint32_t) stack_area_begin); + uint32_t stack = (uint32_t) stack_area_begin; uint32_t stack_high = stack + stack_area_size; - memset(context, 0, sizeof(*context)); + memset( context, 0, sizeof(*context) ) ; - context->r[0] = stack_high; - context->r[3] = (uint32_t) entry_point; -} - -/*PAGE - * - * _CPU_ISR_Get_level - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ + context->r1 = stack_high - 64; + context->r15 = (uint32_t) entry_point; -uint32_t _CPU_ISR_Get_level( void ) -{ - /* - * This routine returns the current interrupt level. - */ + uint32_t msr; + _CPU_MSR_GET( msr ); + context->rmsr = msr; - return 0; + if ( tls_area != NULL ) { + _TLS_TCB_at_area_begin_initialize( tls_area ); + } } -/*PAGE - * - * _CPU_ISR_install_raw_handler - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -) +void _CPU_Exception_frame_print( const CPU_Exception_frame *ctx ) { - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ } -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -) +void _CPU_ISR_Set_level( uint32_t level ) { - *old_handler = _ISR_Vector_table[ vector ]; + uint32_t microblaze_switch_reg; - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ + _CPU_MSR_GET( microblaze_switch_reg ); - _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); + if ( level == 0 ) { + microblaze_switch_reg |= (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); + } else { + microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); + } - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; + _CPU_MSR_SET( microblaze_switch_reg ); } -/*PAGE - * - * _CPU_Install_interrupt_stack - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Install_interrupt_stack( void ) +uint32_t _CPU_ISR_Get_level( void ) { + uint32_t level; + + _CPU_MSR_GET( level ); + + /* This is unique. The MSR register contains an interrupt enable flag where + * most other architectures have an interrupt disable flag. */ + return ( level & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE) ) == 0; } -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ +void _CPU_ISR_install_vector( + uint32_t vector, + CPU_ISR_handler new_handler, + CPU_ISR_handler *old_handler +) +{ + *old_handler = _ISR_Vector_table[ vector ]; + _ISR_Vector_table[ vector ] = new_handler; +} void *_CPU_Thread_Idle_body( uintptr_t ignored ) { - - for( ; ; ) - /* insert your "halt" instruction here */ ; - return NULL; + while ( true ) { + __asm__ volatile ( "sleep" ); + } } diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S b/cpukit/score/cpu/microblaze/cpu_asm.S new file mode 100644 index 0000000000..d095e62f69 --- /dev/null +++ b/cpukit/score/cpu/microblaze/cpu_asm.S @@ -0,0 +1,194 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPUMicroBlaze + * + * @brief MicroBlaze interrupt handler implementation + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <rtems/asm.h> +#include <rtems/score/percpu.h> + + .text + .globl _ISR_Handler + .align 2 + +_ISR_Handler: + /* Save stack frame */ + swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3 + swi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4 + swi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6 + swi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7 + swi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8 + swi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9 + swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10 + swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11 + swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12 + swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15 + swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18 + + xori r3, r5, 0xFFFF + beqi r3, do_exception + + /* Disable dispatching */ + lwi r3, r0, _Per_CPU_Information + 16 + addik r3, r3, 1 + swi r3, r0, _Per_CPU_Information + 16 + + swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14 + + /* Is SP < INTERRUPT_STACK_LOW? */ + lwi r4, r0, _Per_CPU_Information + rsubk r3, r4, r1 + blei r3, switch_to_interrupt_stack + + /* Is SP > INTERRUPT_STACK_HIGH? */ + lwi r4, r0, _Per_CPU_Information + 4 + rsubk r3, r4, r1 + bgei r3, switch_to_interrupt_stack + + bri on_interrupt_stack + +switch_to_interrupt_stack: + add r4, r0, r1 + lwi r1, r0, _Per_CPU_Information + 4 + addik r1, r1, -52 + swi r4, r1, 0 + +on_interrupt_stack: + /* Add 1 to ISR_NEST_LEVEL */ + lwi r3, r0, _Per_CPU_Information + 8 + addik r3, r3, 1 + swi r3, r0, _Per_CPU_Information + 8 + + bralid r15, bsp_interrupt_dispatch + nop + + /* Subtract 1 from ISR_NEST_LEVEL */ + lwi r3, r0, _Per_CPU_Information + 8 + addik r3, r3, -1 + swi r3, r0, _Per_CPU_Information + 8 + + /* Is ISR_NEST_LEVEL > 0? */ + bgti r3, after_stack_switch + + /* Switch back to interrupted thread stack */ + lwi r1, r1, 0 + +after_stack_switch: + /* Subtract 1 from THREAD_DISPATCH_DISABLE_LEVEL */ + lwi r3, r0, _Per_CPU_Information + 16 + addik r3, r3, -1 + swi r3, r0, _Per_CPU_Information + 16 + + /* Is THREAD_DISPATCH_DISABLE_LEVEL != 0? */ + bnei r3, quick_exit + + /* Is DISPATCH_NEEDED == 0? */ + lwi r3, r0, _Per_CPU_Information + 20 + beqi r3, quick_exit + + /* Return to interrupted thread and make it do a dispatch */ + addik r14, r0, thread_dispatch + rtid r14, 0 + nop + +quick_exit: + /* Simple return from nested interrupt */ + /* Restore registers */ + lwi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3 + lwi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4 + lwi r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5 + lwi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6 + lwi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7 + lwi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8 + lwi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9 + lwi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10 + lwi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11 + lwi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12 + lwi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14 + lwi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15 + lwi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18 + + /* Remove stack frame */ + addik r1, r1, 52 + + rtid r14, 0 + nop + +thread_dispatch: + /* Reserve stack */ + addik r1, r1, -52 + /* Save scratch registers */ + swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3 + swi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4 + swi r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5 + swi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6 + swi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7 + swi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8 + swi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9 + swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10 + swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11 + swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12 + swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14 + swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15 + swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18 + + bralid r15, _Thread_Dispatch + nop + + /* Restore scratch registers */ + lwi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3 + lwi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4 + lwi r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5 + lwi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6 + lwi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7 + lwi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8 + lwi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9 + lwi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10 + lwi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11 + lwi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12 + lwi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14 + lwi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15 + lwi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18 + /* Free stack space */ + addik r1, r1, 52 + + bri quick_exit + +do_exception: + /* exception no longer in progress */ + mfs r3, rmsr + andni r3, r3, 0x200 + mts rmsr, r3 + addi r5, r0, 9 + add r6, r0, r1 + + brai _Terminate diff --git a/cpukit/score/cpu/microblaze/rtems/asm.h b/cpukit/score/cpu/microblaze/include/rtems/asm.h index b5a8702f02..2e35a66294 100644 --- a/cpukit/score/cpu/microblaze/rtems/asm.h +++ b/cpukit/score/cpu/microblaze/include/rtems/asm.h @@ -1,29 +1,41 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** - * @file rtems/asm.h + * @file + * + * @brief MicroBlaze assembler support * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. */ /* - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: + * Copyright (c) 2015, Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * Copyright (c) 2015, Hesham Almatary - * COPYRIGHT (c) 1994-2006. - * On-Line Applications Research Corporation (OAR). - * - * $Id: asm.h,v 1.16 2006/01/16 15:12:12 joel Exp $ + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _RTEMS_ASM_H @@ -36,6 +48,7 @@ #ifndef ASM #define ASM #endif + #include <rtems/score/cpuopts.h> #ifndef __USER_LABEL_PREFIX__ diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h new file mode 100644 index 0000000000..4b11625463 --- /dev/null +++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h @@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPU + * + * @brief MicroBlaze architecture support + */ + +/* + * Copyright (c) 2015, Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#include <rtems/score/basedefs.h> +#include <rtems/score/microblaze.h> + +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +#define CPU_ISR_PASSES_FRAME_POINTER FALSE + +#define CPU_HARDWARE_FP FALSE + +#define CPU_SOFTWARE_FP FALSE + +#define CPU_ALL_TASKS_ARE_FP FALSE + +#define CPU_IDLE_TASK_IS_FP FALSE + +#define CPU_USE_DEFERRED_FP_SWITCH FALSE + +#define CPU_STACK_GROWS_UP FALSE + +/** + * The maximum cache-line size is 16 words. + */ +#define CPU_CACHE_LINE_BYTES 64 + +#define CPU_STRUCTURE_ALIGNMENT + +#define CPU_MODES_INTERRUPT_MASK 0x00000001 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup CPUContext Management + * This defines the minimal set of integer and processor state registers + * that must be saved during a voluntary context switch from one thread + * to another. + */ +typedef struct { + uint32_t r1; + uint32_t r13; + uint32_t r14; + uint32_t r15; + uint32_t r16; + uint32_t r17; + uint32_t r18; + uint32_t r19; + uint32_t r20; + uint32_t r21; + uint32_t r22; + uint32_t r23; + uint32_t r24; + uint32_t r25; + uint32_t r26; + uint32_t r27; + uint32_t r28; + uint32_t r29; + uint32_t r30; + uint32_t r31; + uint32_t rmsr; +} Context_Control; + +/** + * @ingroup CPUContext Management + * + * This macro returns the stack pointer associated with @a _context. + * + * @param[in] _context is the thread context area to access + * + * @return This method returns the stack pointer. + */ +#define _CPU_Context_Get_SP( _context ) \ + (_context)->r1 + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 + +#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE + +#define CPU_MAXIMUM_PROCESSORS 32 + +/** + * @ingroup CPUInterrupt + * This defines the highest interrupt vector number for this port. + */ +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) + +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +#define CPU_STACK_MINIMUM_SIZE (1024*4) + +#define CPU_ALIGNMENT 4 + +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT + +#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES + +#define MICROBLAZE_MSR_IE (1 << 1) +#define MICROBLAZE_MSR_EE (1 << 8) + +#define _CPU_MSR_GET( _msr_value ) \ + do { \ + (_msr_value) = 0; \ + __asm__ volatile ("mfs %0, rmsr" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \ + } while (0) + +#define _CPU_MSR_SET( _msr_value ) \ +{ __asm__ volatile ("mts rmsr, %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } + +#define _CPU_ISR_Disable( _isr_cookie ) \ + { \ + unsigned int _new_msr; \ + _CPU_MSR_GET(_isr_cookie); \ + _new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \ + _CPU_MSR_SET(_new_msr); \ + } + +#define _CPU_ISR_Enable( _isr_cookie ) \ + { \ + uint32_t _microblaze_interrupt_enable; \ + uint32_t _microblaze_switch_reg; \ + \ + _microblaze_interrupt_enable = (_isr_cookie) & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \ + _CPU_MSR_GET(_microblaze_switch_reg); \ + _microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \ + _microblaze_switch_reg |= _microblaze_interrupt_enable; \ + _CPU_MSR_SET(_microblaze_switch_reg); \ + } + +#define _CPU_ISR_Flash( _isr_cookie ) \ + { \ + unsigned int _new_msr; \ + _CPU_MSR_SET(_isr_cookie); \ + _new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \ + _CPU_MSR_SET(_new_msr); \ + } + +void _CPU_ISR_Set_level( uint32_t level ); + +uint32_t _CPU_ISR_Get_level( void ); + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return ( level & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE) ) != 0; +} + +void _CPU_Context_Initialize( + Context_Control *context, + void *stack_area_begin, + size_t stack_area_size, + uint32_t new_level, + void (*entry_point)( void ), + bool is_fp, + void *tls_area +); + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +#define _CPU_Context_Initialize_fp( _destination ) \ + { \ + *(*(_destination)) = _CPU_Null_fp_context; \ + } + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/* TODO */ +#define _CPU_Fatal_halt(_source, _error ) \ + do { \ + __asm__ volatile ( "sleep" ); \ + for(;;) {} \ + } while (0) + +/* end of Fatal Error manager macros */ + +/* Bitfield handler macros */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +#define CPU_SIZEOF_POINTER 4 + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +typedef struct { + /* TODO: enumerate registers */ + uint32_t r[32]; +} CPU_Exception_frame; + +/* end of Priority handler macros */ + +/* functions */ + +void _CPU_Initialize( void ); + +typedef void ( *CPU_ISR_handler )( uint32_t ); + +void _CPU_ISR_install_vector( + uint32_t vector, + CPU_ISR_handler new_handler, + CPU_ISR_handler *old_handler +); + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +RTEMS_NO_RETURN void _CPU_Context_restore( + Context_Control *new_context +); + +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return swapped; +} + +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +typedef uint32_t CPU_Counter_ticks; + +uint32_t _CPU_Counter_frequency( void ); + +CPU_Counter_ticks _CPU_Counter_read( void ); + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +void bsp_interrupt_dispatch( uint32_t source ); + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPU_H */ diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..6dc769b95a --- /dev/null +++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPU + * + * @brief MicroBlaze atomic support + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include <rtems/score/cpustdatomic.h> + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..3d0167dd40 --- /dev/null +++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPU + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include <rtems/score/cpu.h> + +/** + * @defgroup RTEMSScoreCPUMicroBlaze MicroBlaze + * + * @ingroup RTEMSScoreCPU + * + * @brief MicroBlaze Architecture Support + * + * @{ + */ + +#define CPU_PER_CPU_CONTROL_SIZE 0 +#define CPU_INTERRUPT_FRAME_SIZE 52 + +#define MICROBLAZE_INTERRUPT_FRAME_R3 0 +#define MICROBLAZE_INTERRUPT_FRAME_R4 4 +#define MICROBLAZE_INTERRUPT_FRAME_R5 8 +#define MICROBLAZE_INTERRUPT_FRAME_R6 12 +#define MICROBLAZE_INTERRUPT_FRAME_R7 16 +#define MICROBLAZE_INTERRUPT_FRAME_R8 20 +#define MICROBLAZE_INTERRUPT_FRAME_R9 24 +#define MICROBLAZE_INTERRUPT_FRAME_R10 28 +#define MICROBLAZE_INTERRUPT_FRAME_R11 32 +#define MICROBLAZE_INTERRUPT_FRAME_R12 36 +#define MICROBLAZE_INTERRUPT_FRAME_R14 40 +#define MICROBLAZE_INTERRUPT_FRAME_R15 44 +#define MICROBLAZE_INTERRUPT_FRAME_R18 48 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +void _CPU_Context_volatile_clobber( uintptr_t pattern ); + +void _CPU_Context_validate( uintptr_t pattern ); + +RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +{ + __asm__ volatile ( ".word 0x0" ); +} + +RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +{ + __asm__ volatile ( "nop" ); +} + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +/** @} */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/microblaze/rtems/score/microblaze.h b/cpukit/score/cpu/microblaze/include/rtems/score/microblaze.h index 19e26314e8..6310b4b17d 100644 --- a/cpukit/score/cpu/microblaze/rtems/score/microblaze.h +++ b/cpukit/score/cpu/microblaze/include/rtems/score/microblaze.h @@ -1,7 +1,16 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPU + * + * @brief MicroBlaze architecture support + */ + /* - * Copyright (c) 2015, Hesham Almatary - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). + * Copyright (c) 2015, Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -9,8 +18,8 @@ * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE @@ -25,58 +34,15 @@ * POSSIBILITY OF SUCH DAMAGE. */ -/* - * This file sets up basic CPU dependency settings based on - * compiler settings. For example, it can determine if - * floating point is available. This particular implementation - * is specified to the NO CPU port. - * - * $Id: no_cpu.h,v 1.9 2009/12/02 09:48:25 ralf Exp $ - * - */ - - -#ifndef _RTEMS_SCORE_NO_CPU_H -#define _RTEMS_SCORE_NO_CPU_H +#ifndef _RTEMS_SCORE_MICROBLAZE_H +#define _RTEMS_SCORE_MICROBLAZE_H #ifdef __cplusplus extern "C" { #endif -/* - * This file contains the information required to build - * RTEMS for a particular member of the NO CPU family. - * It does this by setting variables to indicate which - * implementation dependent features are present in a particular - * member of the family. - * - * This is a good place to list all the known CPU models - * that this port supports and which RTEMS CPU model they correspond - * to. - */ - -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" -#define NOCPU_HAS_FPU 1 - -#else -/* if defined(__MICROBLAZE__) */ - #define CPU_MODEL_NAME "MicroBlaze" -#define NOCPU_HAS_FPU 1 - -/* -#else - -#error "Unsupported CPU Model" -*/ - -#endif +#define NOCPU_HAS_FPU 1 /* * Define the name of the CPU family. @@ -88,4 +54,4 @@ extern "C" { } #endif -#endif /* _RTEMS_SCORE_NO_CPU_H */ +#endif /* _RTEMS_SCORE_MICROBLAZE_H */ diff --git a/cpukit/score/cpu/microblaze/microblaze-context-switch.S b/cpukit/score/cpu/microblaze/microblaze-context-switch.S index e2ec760080..523e836398 100644 --- a/cpukit/score/cpu/microblaze/microblaze-context-switch.S +++ b/cpukit/score/cpu/microblaze/microblaze-context-switch.S @@ -1,5 +1,16 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPUMicroBlaze + * + * @brief MicroBlaze context switch implementation + */ + /* - * Copyright (c) 2015, Hesham Almatary + * Copyright (c) 2015, Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -7,8 +18,8 @@ * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE @@ -59,6 +70,10 @@ SYM(_CPU_Context_switch): swi r30, r5, 72 swi r31, r5, 76 + mfs r21, rmsr + swi r21, r5, 80 + + SYM(restore): lwi r1, r6, 0 lwi r13, r6, 4 @@ -79,6 +94,10 @@ SYM(restore): lwi r28, r6, 64 lwi r29, r6, 68 lwi r30, r6, 72 + + lwi r31, r6, 80 + mts rmsr, r31 + lwi r31, r6, 76 rtsd r15, 8 diff --git a/cpukit/score/cpu/microblaze/microblaze-context-validate.S b/cpukit/score/cpu/microblaze/microblaze-context-validate.S new file mode 100644 index 0000000000..b12d5930f6 --- /dev/null +++ b/cpukit/score/cpu/microblaze/microblaze-context-validate.S @@ -0,0 +1,117 @@ +#ifdef HAVE_CONFIG_H + #include "config.h" +#endif + +#include <rtems/asm.h> + +#define FRAME_OFFSET_R19 0 +#define FRAME_OFFSET_R20 4 +#define FRAME_OFFSET_R21 8 +#define FRAME_OFFSET_R22 12 +#define FRAME_OFFSET_R23 16 +#define FRAME_OFFSET_R24 20 +#define FRAME_OFFSET_R25 24 +#define FRAME_OFFSET_R26 28 +#define FRAME_OFFSET_R27 32 +#define FRAME_OFFSET_R28 36 +#define FRAME_OFFSET_R29 40 +#define FRAME_OFFSET_R30 44 +#define FRAME_OFFSET_R31 48 + +#define FRAME_SIZE (FRAME_OFFSET_R31 + 4) + +.text +.align 4 + +PUBLIC(_CPU_Context_validate) + +SYM(_CPU_Context_validate): + + /* Save */ + addik r1, r1, -FRAME_SIZE + swi r19, r1, FRAME_OFFSET_R19 + swi r20, r1, FRAME_OFFSET_R20 + swi r21, r1, FRAME_OFFSET_R21 + swi r22, r1, FRAME_OFFSET_R22 + swi r23, r1, FRAME_OFFSET_R23 + swi r24, r1, FRAME_OFFSET_R24 + swi r25, r1, FRAME_OFFSET_R25 + swi r26, r1, FRAME_OFFSET_R26 + swi r27, r1, FRAME_OFFSET_R27 + swi r28, r1, FRAME_OFFSET_R28 + swi r29, r1, FRAME_OFFSET_R29 + swi r30, r1, FRAME_OFFSET_R30 + swi r31, r1, FRAME_OFFSET_R31 + + /* Fill */ + + add r4, r0, r3 + + /* r7 contains the stack pointer */ + add r7, r0, r1 + +.macro fill_register reg + addi r4, r4, 1 + add \reg, r0, r4 +.endm + + fill_register r21 + fill_register r22 + fill_register r23 + fill_register r24 + fill_register r25 + fill_register r26 + fill_register r27 + fill_register r28 + fill_register r29 + fill_register r30 + fill_register r31 + + /* Check */ +check: + +.macro check_register reg + addi r4, r4, 1 + cmp r6, \reg, r4 + bnei r6, restore +.endm + + cmp r6, r7, r1 + bnei r6, restore + + add r4, r0, r3 + + check_register r21 + check_register r22 + check_register r23 + check_register r24 + check_register r25 + check_register r26 + check_register r27 + check_register r28 + check_register r29 + check_register r30 + check_register r31 + + brai check + + /* Restore */ +restore: + + lwi r19, r1, FRAME_OFFSET_R19 + lwi r20, r1, FRAME_OFFSET_R20 + lwi r21, r1, FRAME_OFFSET_R21 + lwi r22, r1, FRAME_OFFSET_R22 + lwi r23, r1, FRAME_OFFSET_R23 + lwi r24, r1, FRAME_OFFSET_R24 + lwi r25, r1, FRAME_OFFSET_R25 + lwi r26, r1, FRAME_OFFSET_R26 + lwi r27, r1, FRAME_OFFSET_R27 + lwi r28, r1, FRAME_OFFSET_R28 + lwi r29, r1, FRAME_OFFSET_R29 + lwi r30, r1, FRAME_OFFSET_R30 + lwi r31, r1, FRAME_OFFSET_R31 + + addik r1, r1, FRAME_SIZE + + bra r15 diff --git a/cpukit/score/cpu/microblaze/microblaze-context-volatile-clobber.S b/cpukit/score/cpu/microblaze/microblaze-context-volatile-clobber.S new file mode 100644 index 0000000000..fb49dc5e40 --- /dev/null +++ b/cpukit/score/cpu/microblaze/microblaze-context-volatile-clobber.S @@ -0,0 +1,28 @@ +#ifdef HAVE_CONFIG_H + #include "config.h" +#endif + +#include <rtems/asm.h> + +.text +.align 4 + +PUBLIC(_CPU_Context_volatile_clobber) + +SYM(_CPU_Context_volatile_clobber): + +.macro clobber_register reg + addi r5, r5, -1 + add \reg, r0, r5 +.endm + + clobber_register r3 + clobber_register r4 + clobber_register r6 + clobber_register r7 + clobber_register r8 + clobber_register r9 + clobber_register r10 + + rtsd r15, 8 + nop diff --git a/cpukit/score/cpu/microblaze/rtems/score/cpu.h b/cpukit/score/cpu/microblaze/rtems/score/cpu.h deleted file mode 100644 index d9f9e8add5..0000000000 --- a/cpukit/score/cpu/microblaze/rtems/score/cpu.h +++ /dev/null @@ -1,1280 +0,0 @@ -/* - * Copyright (c) 2015, Hesham Almatary - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file rtems/score/cpu.h - */ - -/* - * This include file contains information pertaining to the XXX - * processor. - * - * @note This file is part of a porting template that is intended - * to be used as the starting point when porting RTEMS to a new - * CPU family. The following needs to be done when using this as - * the starting point for a new port: - * - * + Anywhere there is an XXX, it should be replaced - * with information about the CPU family being ported to. - * - * + At the end of each comment section, there is a heading which - * says "Port Specific Information:". When porting to RTEMS, - * add CPU family specific information in this section - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/microblaze.h> - -/* conditional compilation parameters */ - -/** - * Should the calls to @ref _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * This conditional is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * - * @note In general, the @ref _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls @ref _Thread_Enable_dispatch which in turns calls - * @ref _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/** - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if ( NO_CPU_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALL_TASKS_ARE_FP TRUE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_GROWS_UP TRUE - -/** - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * @note Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STRUCTURE_ALIGNMENT - -/** - * @defgroup CPUEndian Processor Dependent Endianness Support - * - * This group assists in issues related to processor endianness. - */ - -/** - * @ingroup CPUEndian - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_LITTLE_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_BIG_ENDIAN TRUE - -/** - * @ingroup CPUEndian - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_BIG_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_LITTLE_ENDIAN FALSE - -/** - * @ingroup CPUInterrupt - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures required for cpukit/score. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/** - * @ingroup CPUContext Management - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ -typedef struct { - uint32_t r[32]; -} Context_Control; - -/** - * @ingroup CPUContext Management - * - * This macro returns the stack pointer associated with @a _context. - * - * @param[in] _context is the thread context area to access - * - * @return This method returns the stack pointer. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r[0] - -/** - * @ingroup CPUContext Management - * This defines the complete set of floating point registers that must - * be saved during any context switch from one thread to another. - */ -typedef struct { - /** FPU registers are listed here */ - double some_float_register; -} Context_Control_fp; - -/** - * @ingroup CPUContext Management - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - /** This field is a hint that a port will have a number of integer - * registers that need to be saved when an interrupt occurs or - * when a context switch occurs at the end of an ISR. - */ - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/** - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * @ref _CPU_Initialize and copied into the task's FP context area during - * @ref _CPU_Context_Initialize. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * @note These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/** - * @ingroup CPUContext - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * @ingroup CPUInterrupt - * This defines the number of entries in the @ref _ISR_Vector_table managed - * by RTEMS. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 - -/** - * @ingroup CPUInterrupt - * This defines the highest interrupt vector number for this port. - */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/** - * @ingroup CPUInterrupt - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** - * @ingroup CPUContext - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALIGNMENT 8 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. If the - * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be - * set to 0. - * - * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/** - * @ingroup CPUInterrupt - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Initialize_vectors() - -/** - * @ingroup CPUInterrupt - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_MSR_GET( _msr_value ) \ - do { \ - _msr_value = 0; \ - __asm__ volatile ("mfs %0, rmsr" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \ - } while (0) - -#define _CPU_MSR_SET( _msr_value ) \ -{ __asm__ volatile ("mts rmsr, %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } - -#define _CPU_ISR_Disable( _isr_cookie ) \ - { \ - unsigned int _new_msr; \ - _CPU_MSR_GET(_isr_cookie); \ - _new_msr = _isr_cookie & ~0x02; \ - _CPU_MSR_SET(_new_msr); \ - } - -/** - * @ingroup CPUInterrupt - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - { \ - _CPU_MSR_SET(_isr_cookie); \ - } - -/** - * @ingroup CPUInterrupt - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - { \ - unsigned int _new_msr; \ - _CPU_MSR_SET(_isr_cookie); \ - _new_msr = _isr_cookie & ~0x02; \ - _CPU_MSR_SET(_new_msr); \ - } - -/** - * @ingroup CPUInterrupt - * - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Set_level( new_level ) \ - { \ - } - -/** - * @ingroup CPUInterrupt - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * @note This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/** - * @brief Initializes the CPU context. - * - * The following steps are performed: - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - * @param[in] context points to the context area - * @param[in] stack_area_begin is the low address of the allocated stack area - * @param[in] stack_area_size is the size of the stack area in bytes - * @param[in] new_level is the interrupt level for the task - * @param[in] entry_point is the task's entry point - * @param[in] is_fp is set to @c true if the task is a floating point task - * @param[in] tls_area is the thread-local storage (TLS) area - */ -void _CPU_Context_Initialize( - Context_Control *context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/** - * @ingroup CPUContext - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * @param[in] _base is the lowest physical address of the floating point - * context area - * @param[in] _offset is the offset into the floating point area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param[in] _destination is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Fatal_halt(_source, _error ) \ - printk("Fatal Error %d.%d Halted\n",_source, _error); \ - for(;;) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/** - * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation - * - * This set of routines are used to implement fast searches for - * the most important ready task. - */ - -/** - * @ingroup CPUBitfield - * This definition is set to TRUE if the port uses the generic bitfield - * manipulation implementation. - */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/** - * @ingroup CPUBitfield - * This definition is set to TRUE if the port uses the data tables provided - * by the generic bitfield manipulation implementation. - * This can occur when actually using the generic bitfield manipulation - * implementation or when implementing the same algorithm in assembly - * language for improved performance. It is unlikely that a port will use - * the data if it has a bitfield scan instruction. - */ -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -/** - * @ingroup CPUBitfield - * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type - * @a Priority_bit_map_Control. This type may be either 16 or 32 bits - * wide although only the 16 least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * -# What happens when run on a value of zero? - * -# Bits may be numbered from MSB to LSB or vice-versa. - * -# The numbering may be zero or one based. - * -# The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and - * @ref _CPU_Priority_bits_index. These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by @ref _CPU_Priority_Mask. - * The basic major and minor values calculated by @ref _Priority_Major - * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for @ref _Priority_Get_highest to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * -@verbatim - - a series of 16 bit test instructions - - a "binary search using if's" - - _number = 0 - if _value > 0x00ff - _value >>=8 - _number = 8; - - if _value > 0x0000f - _value >=8 - _number += 4 - - _number += bit_set_table[ _value ] -@endverbatim - - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * @param[in] _value is the value to be scanned - * @param[in] _output is the first bit set - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/* end of Bitfield handler macros */ - -/** - * This routine builds the mask which corresponds to the bit fields - * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion - * for that routine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/** - * @ingroup CPUBitfield - * This routine translates the bit numbers returned by - * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * @param[in] _priority is the major or minor number to translate - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE -#define CPU_TIMESTAMP_USE_INT64 TRUE -#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE - -typedef struct { -/* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -#define CPU_SIZEOF_POINTER 4 -#define CPU_PER_CPU_CONTROL_SIZE 0 - -typedef struct { - uint32_t r[32]; -} CPU_Exception_frame; - -/* end of Priority handler macros */ - -/* functions */ - -/** - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Initialize(void); - -/** - * @ingroup CPUInterrupt - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the raw ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the RTEMS ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs the hardware interrupt stack pointer. - * - * @note It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Install_interrupt_stack( void ); - -/** - * This routine is the CPU dependent IDLE thread body. - * - * @note It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/** - * @ingroup CPUContext - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * @ingroup CPUContext - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * @note May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; - -/** - * @ingroup CPUContext - * This routine saves the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_restore_fp to restore this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * @ingroup CPUContext - * This routine restores the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area to restore - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_save_fp to save this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * @ingroup CPUEndian - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return swapped; -} - -/** - * @ingroup CPUEndian - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - */ -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -#ifdef __cplusplus -} -#endif - -#endif |