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-rw-r--r--cpukit/score/cpu/bfin/rtems/asm.h58
-rw-r--r--cpukit/score/cpu/bfin/rtems/bfin/bf52x.h23
-rw-r--r--cpukit/score/cpu/bfin/rtems/bfin/bf533.h20
-rw-r--r--cpukit/score/cpu/bfin/rtems/bfin/bfin.h10
-rw-r--r--cpukit/score/cpu/bfin/rtems/score/bfin.h16
-rw-r--r--cpukit/score/cpu/bfin/rtems/score/cpu.h1211
-rw-r--r--cpukit/score/cpu/bfin/rtems/score/cpu_asm.h8
-rw-r--r--cpukit/score/cpu/bfin/rtems/score/types.h12
-rw-r--r--cpukit/score/cpu/nios2/rtems/score/cpu.h19
-rw-r--r--cpukit/score/cpu/nios2/rtems/score/cpu_asm.h12
-rw-r--r--cpukit/score/cpu/nios2/rtems/score/types.h10
-rw-r--r--cpukit/score/cpu/sh/rtems/asm.h21
-rw-r--r--cpukit/score/cpu/sh/rtems/score/sh.h10
-rw-r--r--cpukit/score/cpu/sh/rtems/score/sh_io.h10
-rw-r--r--cpukit/score/cpu/sh/rtems/score/types.h10
-rw-r--r--cpukit/score/cpu/v850/rtems/asm.h62
-rw-r--r--cpukit/score/cpu/v850/rtems/score/cpu.h1248
-rw-r--r--cpukit/score/cpu/v850/rtems/score/types.h10
-rw-r--r--cpukit/score/cpu/v850/rtems/score/v850.h14
19 files changed, 1429 insertions, 1355 deletions
diff --git a/cpukit/score/cpu/bfin/rtems/asm.h b/cpukit/score/cpu/bfin/rtems/asm.h
index dbe0d7f407..5d133ddbdd 100644
--- a/cpukit/score/cpu/bfin/rtems/asm.h
+++ b/cpukit/score/cpu/bfin/rtems/asm.h
@@ -1,17 +1,20 @@
/**
- * @file rtems/asm.h
+ * @file
*
- * This include file attempts to address the problems
- * caused by incompatible flavors of assemblers and
- * toolsets. It primarily addresses variations in the
- * use of leading underscores on symbols and the requirement
- * that register names be preceded by a %.
+ * @brief Address the Problems Caused by Incompatible Flavor of
+ * Assemblers and Toolsets
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets. It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ *
+ * @note The spacing in the use of these macros
+ * is critical to them working as advertised.
*/
/*
- * NOTE: The spacing in the use of these macros
- * is critical to them working as advertised.
- *
* COPYRIGHT:
*
* This file is based on similar code found in newlib available
@@ -38,24 +41,24 @@
#ifndef __USER_LABEL_PREFIX__
/**
- * Recent versions of GNU cpp define variables which indicate the
- * need for underscores and percents. If not using GNU cpp or
- * the version does not support this, then you will obviously
- * have to define these as appropriate.
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents. If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
*
- * This symbol is prefixed to all C program symbols.
+ * This symbol is prefixed to all C program symbols.
*/
#define __USER_LABEL_PREFIX__ _
#endif
#ifndef __REGISTER_PREFIX__
/**
- * Recent versions of GNU cpp define variables which indicate the
- * need for underscores and percents. If not using GNU cpp or
- * the version does not support this, then you will obviously
- * have to define these as appropriate.
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents. If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
*
- * This symbol is prefixed to all register names.
+ * This symbol is prefixed to all register names.
*/
#define __REGISTER_PREFIX__
#endif
@@ -95,8 +98,9 @@
#define BEGIN_DATA
/** This macro is used to denote the end of a data section. */
#define END_DATA
-/** This macro is used to denote the beginning of the
- * unitialized data section.
+/**
+ * This macro is used to denote the beginning of the
+ * unitialized data section.
*/
#define BEGIN_BSS
/** This macro is used to denote the end of the unitialized data section. */
@@ -105,18 +109,18 @@
#define END
/**
- * This macro is used to declare a public global symbol.
+ * This macro is used to declare a public global symbol.
*
- * @note This must be tailored for a particular flavor of the C compiler.
- * They may need to put underscores in front of the symbols.
+ * @note This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
*/
#define PUBLIC(sym) .globl SYM (sym)
/**
- * This macro is used to prototype a public global symbol.
+ * This macro is used to prototype a public global symbol.
*
- * @note This must be tailored for a particular flavor of the C compiler.
- * They may need to put underscores in front of the symbols.
+ * @note This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
*/
#define EXTERN(sym) .globl SYM (sym)
diff --git a/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h b/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h
index 3c5bf7b3ef..7b4a41ac05 100644
--- a/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h
+++ b/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h
@@ -1,13 +1,17 @@
/**
- *@file bf52x.h
+ * @file
*
- * This file defines basic MMR for the Blackfin 52x CPU.
- * The MMR have been taken from the ADSP-BF52x Blackfin Processor
- * Hardware Reference from Analog Devices. Mentioned Chapters
- * refer to this Documentation.
+ * @brief Basic MMR for the Blackfin 52x CPU
*
- * Based on bf533.h
+ * This file defines basic MMR for the Blackfin 52x CPU.
+ * The MMR have been taken from the ADSP-BF52x Blackfin Processor
+ * Hardware Reference from Analog Devices. Mentioned Chapters
+ * refer to this Documentation.
*
+ * Based on bf533.h
+ */
+
+/*
* COPYRIGHT (c) 2006.
* Atos Automacao Industrial LTDA.
* modified by Alain Schaefer <alain.schaefer@easc.ch>
@@ -18,11 +22,8 @@
* http://www.rtems.com/license/LICENSE.
*
*
- * @author Rohan Kangralkar, ECE Department Northeastern University
- * @date 02/15/2011
- *
- * HISTORY:
- *
+ * Author: Rohan Kangralkar, ECE Department Northeastern University
+ * Date: 02/15/2011
*/
#ifndef _RTEMS_BFIN_52x_H
diff --git a/cpukit/score/cpu/bfin/rtems/bfin/bf533.h b/cpukit/score/cpu/bfin/rtems/bfin/bf533.h
index 005a6fbb81..3ebff2cd90 100644
--- a/cpukit/score/cpu/bfin/rtems/bfin/bf533.h
+++ b/cpukit/score/cpu/bfin/rtems/bfin/bf533.h
@@ -1,14 +1,18 @@
-/* bfin.h
+/**
+ * @file
*
- * This file defines basic MMR for the Blackfin 531/532/533 CPU.
- * The MMR have been taken from the ADSP-BF533 Blackfin Processor
- * Hardware Reference from Analog Devices. Mentioned Chapters
- * refer to this Documentation.
+ * @brief Basic MMR for the Blackfin 531/532/533 CPU
*
- * The Blackfins MMRs are divided into core MMRs (0xFFE0 0000–0xFFFF FFFF)
- * and System MMRs (0xFFC0 0000–0xFFE0 0000). The core MMRs are defined
- * in bfin.h which is included.
+ * This file defines basic MMR for the Blackfin 531/532/533 CPU.
+ * The MMR have been taken from the ADSP-BF533 Blackfin Processor
+ * Hardware Reference from Analog Devices. Mentioned Chapters
+ * refer to this Documentation.
*
+ * The Blackfins MMRs are divided into core MMRs (0xFFE0 0000–0xFFFF FFFF)
+ * and System MMRs (0xFFC0 0000–0xFFE0 0000). The core MMRs are defined
+ * in bfin.h which is included.
+ */
+/*
* COPYRIGHT (c) 2006.
* Atos Automacao Industrial LTDA.
* modified by Alain Schaefer <alain.schaefer@easc.ch>
diff --git a/cpukit/score/cpu/bfin/rtems/bfin/bfin.h b/cpukit/score/cpu/bfin/rtems/bfin/bfin.h
index f3d6341d5c..ad7631d054 100644
--- a/cpukit/score/cpu/bfin/rtems/bfin/bfin.h
+++ b/cpukit/score/cpu/bfin/rtems/bfin/bfin.h
@@ -1,8 +1,12 @@
-/* bfin.h
+/**
+ * @file
*
- * This file defines Macros for MMR register common to all Blackfin
- * Processors.
+ * @brief Macros for MMR register common to all Blackfin Processors
*
+ * This file defines Macros for MMR register common to all Blackfin
+ * Processors.
+ */
+/*
* COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
* modified by Alain Schaefer <alain.schaefer@easc.ch>
* and Antonio Giovanini <antonio@atos.com.br>
diff --git a/cpukit/score/cpu/bfin/rtems/score/bfin.h b/cpukit/score/cpu/bfin/rtems/score/bfin.h
index 9eda79fd2d..2907840680 100644
--- a/cpukit/score/cpu/bfin/rtems/score/bfin.h
+++ b/cpukit/score/cpu/bfin/rtems/score/bfin.h
@@ -1,10 +1,16 @@
-/* bfin.h
+/**
+ * @file
*
- * This file sets up basic CPU dependency settings based on
- * compiler settings. For example, it can determine if
- * floating point is available. This particular implementation
- * is specified to the Blackfin port.
+ * @brief Blackfin Set up Basic CPU Dependency Settings Based on
+ * Compiler Settings
*
+ * This file sets up basic CPU dependency settings based on
+ * compiler settings. For example, it can determine if
+ * floating point is available. This particular implementation
+ * is specified to the Blackfin port.
+ */
+
+/*
*
* COPYRIGHT (c) 1989-2006.
* On-Line Applications Research Corporation (OAR).
diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h b/cpukit/score/cpu/bfin/rtems/score/cpu.h
index f6fab7543b..425fc68fa7 100644
--- a/cpukit/score/cpu/bfin/rtems/score/cpu.h
+++ b/cpukit/score/cpu/bfin/rtems/score/cpu.h
@@ -1,11 +1,13 @@
/**
- * @file rtems/score/cpu.h
+ * @file
+ *
+ * @brief Blackfin CPU Department Source
+ *
+ * This include file contains information pertaining to the Blackfin
+ * processor.
*/
/*
- * This include file contains information pertaining to the Blackfin
- * processor.
- *
* COPYRIGHT (c) 1989-2006.
* On-Line Applications Research Corporation (OAR).
* adapted to Blackfin by Alain Schaefer <alain.schaefer@easc.ch>
@@ -29,77 +31,77 @@ extern "C" {
/* conditional compilation parameters */
/**
- * Should the calls to @ref _Thread_Enable_dispatch be inlined?
+ * Should the calls to @ref _Thread_Enable_dispatch be inlined?
*
- * If TRUE, then they are inlined.
- * If FALSE, then a subroutine call is made.
+ * If TRUE, then they are inlined.
+ * If FALSE, then a subroutine call is made.
*
- * This conditional is an example of the classic trade-off of size
- * versus speed. Inlining the call (TRUE) typically increases the
- * size of RTEMS while speeding up the enabling of dispatching.
+ * This conditional is an example of the classic trade-off of size
+ * versus speed. Inlining the call (TRUE) typically increases the
+ * size of RTEMS while speeding up the enabling of dispatching.
*
- * @note In general, the @ref _Thread_Dispatch_disable_level will
- * only be 0 or 1 unless you are in an interrupt handler and that
- * interrupt handler invokes the executive.] When not inlined
- * something calls @ref _Thread_Enable_dispatch which in turns calls
- * @ref _Thread_Dispatch. If the enable dispatch is inlined, then
- * one subroutine call is avoided entirely.
+ * @note In general, the @ref _Thread_Dispatch_disable_level will
+ * only be 0 or 1 unless you are in an interrupt handler and that
+ * interrupt handler invokes the executive.] When not inlined
+ * something calls @ref _Thread_Enable_dispatch which in turns calls
+ * @ref _Thread_Dispatch. If the enable dispatch is inlined, then
+ * one subroutine call is avoided entirely.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_INLINE_ENABLE_DISPATCH FALSE
/**
- * Should the body of the search loops in _Thread_queue_Enqueue_priority
- * be unrolled one time? In unrolled each iteration of the loop examines
- * two "nodes" on the chain being searched. Otherwise, only one node
- * is examined per iteration.
+ * Should the body of the search loops in _Thread_queue_Enqueue_priority
+ * be unrolled one time? In unrolled each iteration of the loop examines
+ * two "nodes" on the chain being searched. Otherwise, only one node
+ * is examined per iteration.
*
- * If TRUE, then the loops are unrolled.
- * If FALSE, then the loops are not unrolled.
+ * If TRUE, then the loops are unrolled.
+ * If FALSE, then the loops are not unrolled.
*
- * The primary factor in making this decision is the cost of disabling
- * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
- * body of the loop. On some CPUs, the flash is more expensive than
- * one iteration of the loop body. In this case, it might be desirable
- * to unroll the loop. It is important to note that on some CPUs, this
- * code is the longest interrupt disable period in RTEMS. So it is
- * necessary to strike a balance when setting this parameter.
+ * The primary factor in making this decision is the cost of disabling
+ * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
+ * body of the loop. On some CPUs, the flash is more expensive than
+ * one iteration of the loop body. In this case, it might be desirable
+ * to unroll the loop. It is important to note that on some CPUs, this
+ * code is the longest interrupt disable period in RTEMS. So it is
+ * necessary to strike a balance when setting this parameter.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
/**
- * Does RTEMS manage a dedicated interrupt stack in software?
+ * Does RTEMS manage a dedicated interrupt stack in software?
*
- * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
- * If FALSE, nothing is done.
+ * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
+ * If FALSE, nothing is done.
*
- * If the CPU supports a dedicated interrupt stack in hardware,
- * then it is generally the responsibility of the BSP to allocate it
- * and set it up.
+ * If the CPU supports a dedicated interrupt stack in hardware,
+ * then it is generally the responsibility of the BSP to allocate it
+ * and set it up.
*
- * If the CPU does not support a dedicated interrupt stack, then
- * the porter has two options: (1) execute interrupts on the
- * stack of the interrupted task, and (2) have RTEMS manage a dedicated
- * interrupt stack.
+ * If the CPU does not support a dedicated interrupt stack, then
+ * the porter has two options: (1) execute interrupts on the
+ * stack of the interrupted task, and (2) have RTEMS manage a dedicated
+ * interrupt stack.
*
- * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
*
- * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
- * possible that both are FALSE for a particular CPU. Although it
- * is unclear what that would imply about the interrupt processing
- * procedure on that CPU.
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
+ * possible that both are FALSE for a particular CPU. Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
@@ -130,84 +132,84 @@ extern "C" {
#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
/**
- * Does this CPU have hardware support for a dedicated interrupt stack?
+ * Does this CPU have hardware support for a dedicated interrupt stack?
*
- * If TRUE, then it must be installed during initialization.
- * If FALSE, then no installation is performed.
+ * If TRUE, then it must be installed during initialization.
+ * If FALSE, then no installation is performed.
*
- * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
*
- * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
- * possible that both are FALSE for a particular CPU. Although it
- * is unclear what that would imply about the interrupt processing
- * procedure on that CPU.
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
+ * possible that both are FALSE for a particular CPU. Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
/**
- * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
+ * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
*
- * If TRUE, then the memory is allocated during initialization.
- * If FALSE, then the memory is allocated during initialization.
+ * If TRUE, then the memory is allocated during initialization.
+ * If FALSE, then the memory is allocated during initialization.
*
- * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
+ * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/**
- * Does the RTEMS invoke the user's ISR with the vector number and
- * a pointer to the saved interrupt frame (1) or just the vector
- * number (0)?
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_ISR_PASSES_FRAME_POINTER 1
/**
- * @def CPU_HARDWARE_FP
+ * @def CPU_HARDWARE_FP
*
- * Does the CPU have hardware floating point?
+ * Does the CPU have hardware floating point?
*
- * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
- * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
*
- * If there is a FP coprocessor such as the i387 or mc68881, then
- * the answer is TRUE.
+ * If there is a FP coprocessor such as the i387 or mc68881, then
+ * the answer is TRUE.
*
- * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
- * It indicates whether or not this CPU model has FP support. For
- * example, it would be possible to have an i386_nofp CPU model
- * which set this to false to indicate that you have an i386 without
- * an i387 and wish to leave floating point support out of RTEMS.
+ * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
+ * It indicates whether or not this CPU model has FP support. For
+ * example, it would be possible to have an i386_nofp CPU model
+ * which set this to false to indicate that you have an i386 without
+ * an i387 and wish to leave floating point support out of RTEMS.
*/
/**
- * @def CPU_SOFTWARE_FP
+ * @def CPU_SOFTWARE_FP
*
- * Does the CPU have no hardware floating point and GCC provides a
- * software floating point implementation which must be context
- * switched?
+ * Does the CPU have no hardware floating point and GCC provides a
+ * software floating point implementation which must be context
+ * switched?
*
- * This feature conditional is used to indicate whether or not there
- * is software implemented floating point that must be context
- * switched. The determination of whether or not this applies
- * is very tool specific and the state saved/restored is also
- * compiler specific.
+ * This feature conditional is used to indicate whether or not there
+ * is software implemented floating point that must be context
+ * switched. The determination of whether or not this applies
+ * is very tool specific and the state saved/restored is also
+ * compiler specific.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#if ( BLACKFIN_CPU_HAS_FPU == 1 )
#define CPU_HARDWARE_FP TRUE
@@ -217,192 +219,194 @@ extern "C" {
#define CPU_SOFTWARE_FP FALSE
/**
- * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
+ * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
*
- * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
- * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
*
- * So far, the only CPUs in which this option has been used are the
- * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and
- * gcc both implicitly used the floating point registers to perform
- * integer multiplies. Similarly, the PowerPC port of gcc has been
- * seen to allocate floating point local variables and touch the FPU
- * even when the flow through a subroutine (like vfprintf()) might
- * not use floating point formats.
+ * So far, the only CPUs in which this option has been used are the
+ * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and
+ * gcc both implicitly used the floating point registers to perform
+ * integer multiplies. Similarly, the PowerPC port of gcc has been
+ * seen to allocate floating point local variables and touch the FPU
+ * even when the flow through a subroutine (like vfprintf()) might
+ * not use floating point formats.
*
- * If a function which you would not think utilize the FP unit DOES,
- * then one can not easily predict which tasks will use the FP hardware.
- * In this case, this option should be TRUE.
+ * If a function which you would not think utilize the FP unit DOES,
+ * then one can not easily predict which tasks will use the FP hardware.
+ * In this case, this option should be TRUE.
*
- * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_ALL_TASKS_ARE_FP FALSE
/**
- * Should the IDLE task have a floating point context?
+ * Should the IDLE task have a floating point context?
*
- * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
- * and it has a floating point context which is switched in and out.
- * If FALSE, then the IDLE task does not have a floating point context.
+ * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
+ * and it has a floating point context which is switched in and out.
+ * If FALSE, then the IDLE task does not have a floating point context.
*
- * Setting this to TRUE negatively impacts the time required to preempt
- * the IDLE task from an interrupt because the floating point context
- * must be saved as part of the preemption.
+ * Setting this to TRUE negatively impacts the time required to preempt
+ * the IDLE task from an interrupt because the floating point context
+ * must be saved as part of the preemption.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_IDLE_TASK_IS_FP FALSE
/**
- * Should the saving of the floating point registers be deferred
- * until a context switch is made to another different floating point
- * task?
+ * Should the saving of the floating point registers be deferred
+ * until a context switch is made to another different floating point
+ * task?
*
- * If TRUE, then the floating point context will not be stored until
- * necessary. It will remain in the floating point registers and not
- * disturned until another floating point task is switched to.
+ * If TRUE, then the floating point context will not be stored until
+ * necessary. It will remain in the floating point registers and not
+ * disturned until another floating point task is switched to.
*
- * If FALSE, then the floating point context is saved when a floating
- * point task is switched out and restored when the next floating point
- * task is restored. The state of the floating point registers between
- * those two operations is not specified.
+ * If FALSE, then the floating point context is saved when a floating
+ * point task is switched out and restored when the next floating point
+ * task is restored. The state of the floating point registers between
+ * those two operations is not specified.
*
- * If the floating point context does NOT have to be saved as part of
- * interrupt dispatching, then it should be safe to set this to TRUE.
+ * If the floating point context does NOT have to be saved as part of
+ * interrupt dispatching, then it should be safe to set this to TRUE.
*
- * Setting this flag to TRUE results in using a different algorithm
- * for deciding when to save and restore the floating point context.
- * The deferred FP switch algorithm minimizes the number of times
- * the FP context is saved and restored. The FP context is not saved
- * until a context switch is made to another, different FP task.
- * Thus in a system with only one FP task, the FP context will never
- * be saved or restored.
+ * Setting this flag to TRUE results in using a different algorithm
+ * for deciding when to save and restore the floating point context.
+ * The deferred FP switch algorithm minimizes the number of times
+ * the FP context is saved and restored. The FP context is not saved
+ * until a context switch is made to another, different FP task.
+ * Thus in a system with only one FP task, the FP context will never
+ * be saved or restored.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_USE_DEFERRED_FP_SWITCH TRUE
/**
- * Does this port provide a CPU dependent IDLE task implementation?
+ * Does this port provide a CPU dependent IDLE task implementation?
*
- * If TRUE, then the routine @ref _CPU_Thread_Idle_body
- * must be provided and is the default IDLE thread body instead of
- * @ref _CPU_Thread_Idle_body.
+ * If TRUE, then the routine @ref _CPU_Thread_Idle_body
+ * must be provided and is the default IDLE thread body instead of
+ * @ref _CPU_Thread_Idle_body.
*
- * If FALSE, then use the generic IDLE thread body if the BSP does
- * not provide one.
+ * If FALSE, then use the generic IDLE thread body if the BSP does
+ * not provide one.
*
- * This is intended to allow for supporting processors which have
- * a low power or idle mode. When the IDLE thread is executed, then
- * the CPU can be powered down.
+ * This is intended to allow for supporting processors which have
+ * a low power or idle mode. When the IDLE thread is executed, then
+ * the CPU can be powered down.
*
- * The order of precedence for selecting the IDLE thread body is:
+ * The order of precedence for selecting the IDLE thread body is:
*
- * -# BSP provided
- * -# CPU dependent (if provided)
- * -# generic (if no BSP and no CPU dependent)
+ * -# BSP provided
+ * -# CPU dependent (if provided)
+ * -# generic (if no BSP and no CPU dependent)
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
/**
- * Does the stack grow up (toward higher addresses) or down
- * (toward lower addresses)?
+ * Does the stack grow up (toward higher addresses) or down
+ * (toward lower addresses)?
*
- * If TRUE, then the grows upward.
- * If FALSE, then the grows toward smaller addresses.
+ * If TRUE, then the grows upward.
+ * If FALSE, then the grows toward smaller addresses.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_STACK_GROWS_UP FALSE
/**
- * The following is the variable attribute used to force alignment
- * of critical RTEMS structures. On some processors it may make
- * sense to have these aligned on tighter boundaries than
- * the minimum requirements of the compiler in order to have as
- * much of the critical data area as possible in a cache line.
+ * The following is the variable attribute used to force alignment
+ * of critical RTEMS structures. On some processors it may make
+ * sense to have these aligned on tighter boundaries than
+ * the minimum requirements of the compiler in order to have as
+ * much of the critical data area as possible in a cache line.
*
- * The placement of this macro in the declaration of the variables
- * is based on the syntactically requirements of the GNU C
- * "__attribute__" extension. For example with GNU C, use
- * the following to force a structures to a 32 byte boundary.
+ * The placement of this macro in the declaration of the variables
+ * is based on the syntactically requirements of the GNU C
+ * "__attribute__" extension. For example with GNU C, use
+ * the following to force a structures to a 32 byte boundary.
*
- * __attribute__ ((aligned (32)))
+ * __attribute__ ((aligned (32)))
*
- * @note Currently only the Priority Bit Map table uses this feature.
- * To benefit from using this, the data must be heavily
- * used so it will stay in the cache and used frequently enough
- * in the executive to justify turning this on.
+ * @note Currently only the Priority Bit Map table uses this feature.
+ * To benefit from using this, the data must be heavily
+ * used so it will stay in the cache and used frequently enough
+ * in the executive to justify turning this on.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_STRUCTURE_ALIGNMENT
#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
/**
- * @defgroup CPUEndian Processor Dependent Endianness Support
+ * @defgroup CPUEndian Processor Dependent Endianness Support
+ *
+ * This group assists in issues related to processor endianness.
*
- * This group assists in issues related to processor endianness.
+ * @{
*/
/**
- * @ingroup CPUEndian
- * Define what is required to specify how the network to host conversion
- * routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
*
- * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
- * same values.
+ * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
*
- * @see CPU_LITTLE_ENDIAN
+ * @see CPU_LITTLE_ENDIAN
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_BIG_ENDIAN FALSE
/**
- * @ingroup CPUEndian
- * Define what is required to specify how the network to host conversion
- * routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
*
- * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
- * same values.
+ * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
*
- * @see CPU_BIG_ENDIAN
+ * @see CPU_BIG_ENDIAN
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_LITTLE_ENDIAN TRUE
+/** @} */
+
/**
- * @ingroup CPUInterrupt
- * The following defines the number of bits actually used in the
- * interrupt field of the task mode. How those bits map to the
- * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
+ * @ingroup CPUInterrupt
+ * The following defines the number of bits actually used in the
+ * interrupt field of the task mode. How those bits map to the
+ * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_MODES_INTERRUPT_MASK 0x00000001
@@ -419,52 +423,53 @@ extern "C" {
/**
* @defgroup CPUContext Processor Dependent Context Management
*
- * From the highest level viewpoint, there are 2 types of context to save.
+ * From the highest level viewpoint, there are 2 types of context to save.
*
- * -# Interrupt registers to save
- * -# Task level registers to save
+ * -# Interrupt registers to save
+ * -# Task level registers to save
*
- * Since RTEMS handles integer and floating point contexts separately, this
- * means we have the following 3 context items:
+ * Since RTEMS handles integer and floating point contexts separately, this
+ * means we have the following 3 context items:
*
- * -# task level context stuff:: Context_Control
- * -# floating point task stuff:: Context_Control_fp
- * -# special interrupt level context :: CPU_Interrupt_frame
+ * -# task level context stuff:: Context_Control
+ * -# floating point task stuff:: Context_Control_fp
+ * -# special interrupt level context :: CPU_Interrupt_frame
*
- * On some processors, it is cost-effective to save only the callee
- * preserved registers during a task context switch. This means
- * that the ISR code needs to save those registers which do not
- * persist across function calls. It is not mandatory to make this
- * distinctions between the caller/callee saves registers for the
- * purpose of minimizing context saved during task switch and on interrupts.
- * If the cost of saving extra registers is minimal, simplicity is the
- * choice. Save the same context on interrupt entry as for tasks in
- * this case.
+ * On some processors, it is cost-effective to save only the callee
+ * preserved registers during a task context switch. This means
+ * that the ISR code needs to save those registers which do not
+ * persist across function calls. It is not mandatory to make this
+ * distinctions between the caller/callee saves registers for the
+ * purpose of minimizing context saved during task switch and on interrupts.
+ * If the cost of saving extra registers is minimal, simplicity is the
+ * choice. Save the same context on interrupt entry as for tasks in
+ * this case.
*
- * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
- * care should be used in designing the context area.
+ * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
+ * care should be used in designing the context area.
*
- * On some CPUs with hardware floating point support, the Context_Control_fp
- * structure will not be used or it simply consist of an array of a
- * fixed number of bytes. This is done when the floating point context
- * is dumped by a "FP save context" type instruction and the format
- * is not really defined by the CPU. In this case, there is no need
- * to figure out the exact format -- only the size. Of course, although
- * this is enough information for RTEMS, it is probably not enough for
- * a debugger such as gdb. But that is another problem.
+ * On some CPUs with hardware floating point support, the Context_Control_fp
+ * structure will not be used or it simply consist of an array of a
+ * fixed number of bytes. This is done when the floating point context
+ * is dumped by a "FP save context" type instruction and the format
+ * is not really defined by the CPU. In this case, there is no need
+ * to figure out the exact format -- only the size. Of course, although
+ * this is enough information for RTEMS, it is probably not enough for
+ * a debugger such as gdb. But that is another problem.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
+ *
+ * @{
*/
#ifndef ASM
/**
- * @ingroup CPUContext Management
- * This defines the minimal set of integer and processor state registers
- * that must be saved during a voluntary context switch from one thread
- * to another.
+ * This defines the minimal set of integer and processor state registers
+ * that must be saved during a voluntary context switch from one thread
+ * to another.
*/
/* make sure this stays in sync with the assembly function
@@ -490,9 +495,8 @@ typedef struct {
(_context)->register_sp
/**
- * @ingroup CPUContext Management
- * This defines the complete set of floating point registers that must
- * be saved during any context switch from one thread to another.
+ * This defines the complete set of floating point registers that must
+ * be saved during any context switch from one thread to another.
*/
typedef struct {
/* FPU registers are listed here */
@@ -500,48 +504,51 @@ typedef struct {
} Context_Control_fp;
/**
- * @ingroup CPUContext Management
- * This defines the set of integer and processor state registers that must
- * be saved during an interrupt. This set does not include any which are
- * in @ref Context_Control.
+ * This defines the set of integer and processor state registers that must
+ * be saved during an interrupt. This set does not include any which are
+ * in @ref Context_Control.
*/
typedef struct {
/** This field is a hint that a port will have a number of integer
- * registers that need to be saved when an interrupt occurs or
- * when a context switch occurs at the end of an ISR.
+ * registers that need to be saved when an interrupt occurs or
+ * when a context switch occurs at the end of an ISR.
*/
/*uint32_t special_interrupt_register;*/
} CPU_Interrupt_frame;
/**
- * This variable is optional. It is used on CPUs on which it is difficult
- * to generate an "uninitialized" FP context. It is filled in by
- * @ref _CPU_Initialize and copied into the task's FP context area during
- * @ref _CPU_Context_Initialize.
+ * This variable is optional. It is used on CPUs on which it is difficult
+ * to generate an "uninitialized" FP context. It is filled in by
+ * @ref _CPU_Initialize and copied into the task's FP context area during
+ * @ref _CPU_Context_Initialize.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
+/** @} */
+
/**
- * @defgroup CPUInterrupt Processor Dependent Interrupt Management
+ * @defgroup CPUInterrupt Processor Dependent Interrupt Management
*
- * On some CPUs, RTEMS supports a software managed interrupt stack.
- * This stack is allocated by the Interrupt Manager and the switch
- * is performed in @ref _ISR_Handler. These variables contain pointers
- * to the lowest and highest addresses in the chunk of memory allocated
- * for the interrupt stack. Since it is unknown whether the stack
- * grows up or down (in general), this give the CPU dependent
- * code the option of picking the version it wants to use.
+ * On some CPUs, RTEMS supports a software managed interrupt stack.
+ * This stack is allocated by the Interrupt Manager and the switch
+ * is performed in @ref _ISR_Handler. These variables contain pointers
+ * to the lowest and highest addresses in the chunk of memory allocated
+ * for the interrupt stack. Since it is unknown whether the stack
+ * grows up or down (in general), this give the CPU dependent
+ * code the option of picking the version it wants to use.
*
- * @note These two variables are required if the macro
- * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
+ * @note These two variables are required if the macro
+ * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
+ *
+ * @{
*/
/*
@@ -555,133 +562,135 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
/* XXX: if needed, put more variables here */
/**
- * @ingroup CPUContext
- * The size of the floating point context area. On some CPUs this
- * will not be a "sizeof" because the format of the floating point
- * area is not defined -- only the size is. This is usually on
- * CPUs with a "floating point save context" instruction.
+ * @ingroup CPUContext
+ * The size of the floating point context area. On some CPUs this
+ * will not be a "sizeof" because the format of the floating point
+ * area is not defined -- only the size is. This is usually on
+ * CPUs with a "floating point save context" instruction.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
#endif /* ASM */
/**
- * Amount of extra stack (above minimum stack size) required by
- * MPCI receive server thread. Remember that in a multiprocessor
- * system this thread must exist and be able to process all directives.
+ * Amount of extra stack (above minimum stack size) required by
+ * MPCI receive server thread. Remember that in a multiprocessor
+ * system this thread must exist and be able to process all directives.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
/**
- * @ingroup CPUInterrupt
- * This defines the number of entries in the @ref _ISR_Vector_table managed
- * by RTEMS.
+ * @ingroup CPUInterrupt
+ * This defines the number of entries in the @ref _ISR_Vector_table managed
+ * by RTEMS.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_INTERRUPT_NUMBER_OF_VECTORS 16
/**
- * @ingroup CPUInterrupt
- * This defines the highest interrupt vector number for this port.
+ * @ingroup CPUInterrupt
+ * This defines the highest interrupt vector number for this port.
*/
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
/**
- * @ingroup CPUInterrupt
- * This is defined if the port has a special way to report the ISR nesting
- * level. Most ports maintain the variable @a _ISR_Nest_level.
+ * @ingroup CPUInterrupt
+ * This is defined if the port has a special way to report the ISR nesting
+ * level. Most ports maintain the variable @a _ISR_Nest_level.
*/
#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
+/** @} */
+
/**
- * @ingroup CPUContext
- * Should be large enough to run all RTEMS tests. This ensures
- * that a "reasonable" small application should not have any problems.
+ * @ingroup CPUContext
+ * Should be large enough to run all RTEMS tests. This ensures
+ * that a "reasonable" small application should not have any problems.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_STACK_MINIMUM_SIZE (1024*8)
#define CPU_SIZEOF_POINTER 4
/**
- * CPU's worst alignment requirement for data types on a byte boundary. This
- * alignment does not take into account the requirements for the stack.
+ * CPU's worst alignment requirement for data types on a byte boundary. This
+ * alignment does not take into account the requirements for the stack.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_ALIGNMENT 8
/**
- * This number corresponds to the byte alignment requirement for the
- * heap handler. This alignment requirement may be stricter than that
- * for the data types alignment specified by @ref CPU_ALIGNMENT. It is
- * common for the heap to follow the same alignment requirement as
- * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for
- * the heap, then this should be set to @ref CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for the
+ * heap handler. This alignment requirement may be stricter than that
+ * for the data types alignment specified by @ref CPU_ALIGNMENT. It is
+ * common for the heap to follow the same alignment requirement as
+ * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for
+ * the heap, then this should be set to @ref CPU_ALIGNMENT.
*
- * @note This does not have to be a power of 2 although it should be
- * a multiple of 2 greater than or equal to 2. The requirement
- * to be a multiple of 2 is because the heap uses the least
- * significant field of the front and back flags to indicate
- * that a block is in use or free. So you do not want any odd
- * length blocks really putting length data in that bit.
+ * @note This does not have to be a power of 2 although it should be
+ * a multiple of 2 greater than or equal to 2. The requirement
+ * to be a multiple of 2 is because the heap uses the least
+ * significant field of the front and back flags to indicate
+ * that a block is in use or free. So you do not want any odd
+ * length blocks really putting length data in that bit.
*
- * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
- * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
- * elements allocated from the heap meet all restrictions.
+ * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
+ * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
+ * elements allocated from the heap meet all restrictions.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
/**
- * This number corresponds to the byte alignment requirement for memory
- * buffers allocated by the partition manager. This alignment requirement
- * may be stricter than that for the data types alignment specified by
- * @ref CPU_ALIGNMENT. It is common for the partition to follow the same
- * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is
- * strict enough for the partition, then this should be set to
- * @ref CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for memory
+ * buffers allocated by the partition manager. This alignment requirement
+ * may be stricter than that for the data types alignment specified by
+ * @ref CPU_ALIGNMENT. It is common for the partition to follow the same
+ * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is
+ * strict enough for the partition, then this should be set to
+ * @ref CPU_ALIGNMENT.
*
- * @note This does not have to be a power of 2. It does have to
- * be greater or equal to than @ref CPU_ALIGNMENT.
+ * @note This does not have to be a power of 2. It does have to
+ * be greater or equal to than @ref CPU_ALIGNMENT.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
/**
- * This number corresponds to the byte alignment requirement for the
- * stack. This alignment requirement may be stricter than that for the
- * data types alignment specified by @ref CPU_ALIGNMENT. If the
- * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
- * set to 0.
+ * This number corresponds to the byte alignment requirement for the
+ * stack. This alignment requirement may be stricter than that for the
+ * data types alignment specified by @ref CPU_ALIGNMENT. If the
+ * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
+ * set to 0.
*
- * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
+ * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_STACK_ALIGNMENT 8
@@ -690,25 +699,29 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
*/
/**
- * @ingroup CPUInterrupt
- * Support routine to initialize the RTEMS vector table after it is allocated.
+ * @addtogroup CPUInterrupt
*
- * Port Specific Information:
+ * @{
+ */
+
+/**
+ * Support routine to initialize the RTEMS vector table after it is allocated.
*
- * XXX document implementation including references if appropriate
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
*/
#define _CPU_Initialize_vectors()
/**
- * @ingroup CPUInterrupt
- * Disable all interrupts for an RTEMS critical section. The previous
- * level is returned in @a _isr_cookie.
+ * Disable all interrupts for an RTEMS critical section. The previous
+ * level is returned in @a _isr_cookie.
*
- * @param[out] _isr_cookie will contain the previous level cookie
+ * @param[out] _isr_cookie will contain the previous level cookie
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define _CPU_ISR_Disable( _level ) \
{ \
@@ -717,33 +730,31 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
/**
- * @ingroup CPUInterrupt
- * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- * This indicates the end of an RTEMS critical section. The parameter
- * @a _isr_cookie is not modified.
+ * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
+ * This indicates the end of an RTEMS critical section. The parameter
+ * @a _isr_cookie is not modified.
*
- * @param[in] _isr_cookie contain the previous level cookie
+ * @param[in] _isr_cookie contain the previous level cookie
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define _CPU_ISR_Enable( _level ) { \
__asm__ __volatile__ ("sti %0; csync \n" : : "d" (_level) ); \
}
/**
- * @ingroup CPUInterrupt
- * This temporarily restores the interrupt to @a _isr_cookie before immediately
- * disabling them again. This is used to divide long RTEMS critical
- * sections into two or more parts. The parameter @a _isr_cookie is not
- * modified.
+ * This temporarily restores the interrupt to @a _isr_cookie before immediately
+ * disabling them again. This is used to divide long RTEMS critical
+ * sections into two or more parts. The parameter @a _isr_cookie is not
+ * modified.
*
- * @param[in] _isr_cookie contain the previous level cookie
+ * @param[in] _isr_cookie contain the previous level cookie
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define _CPU_ISR_Flash( _level ) { \
__asm__ __volatile__ ("sti %0; csync; cli r0; csync" \
@@ -751,21 +762,19 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
}
/**
- * @ingroup CPUInterrupt
+ * This routine and @ref _CPU_ISR_Get_level
+ * Map the interrupt level in task mode onto the hardware that the CPU
+ * actually provides. Currently, interrupt levels which do not
+ * map onto the CPU in a generic fashion are undefined. Someday,
+ * it would be nice if these were "mapped" by the application
+ * via a callout. For example, m68k has 8 levels 0 - 7, levels
+ * 8 - 255 would be available for bsp/application specific meaning.
+ * This could be used to manage a programmable interrupt controller
+ * via the rtems_task_mode directive.
*
- * This routine and @ref _CPU_ISR_Get_level
- * Map the interrupt level in task mode onto the hardware that the CPU
- * actually provides. Currently, interrupt levels which do not
- * map onto the CPU in a generic fashion are undefined. Someday,
- * it would be nice if these were "mapped" by the application
- * via a callout. For example, m68k has 8 levels 0 - 7, levels
- * 8 - 255 would be available for bsp/application specific meaning.
- * This could be used to manage a programmable interrupt controller
- * via the rtems_task_mode directive.
+ * Port Specific Information:
*
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define _CPU_ISR_Set_level( _new_level ) \
{ \
@@ -775,52 +784,53 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
#ifndef ASM
/**
- * @ingroup CPUInterrupt
- * Return the current interrupt disable level for this task in
- * the format used by the interrupt level portion of the task mode.
+ * Return the current interrupt disable level for this task in
+ * the format used by the interrupt level portion of the task mode.
*
- * @note This routine usually must be implemented as a subroutine.
+ * @note This routine usually must be implemented as a subroutine.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
uint32_t _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
+/** @} */
+
/* Context handler macros */
/**
- * @ingroup CPUContext
- * Initialize the context to a state suitable for starting a
- * task after a context restore operation. Generally, this
- * involves:
- *
- * - setting a starting address
- * - preparing the stack
- * - preparing the stack and frame pointers
- * - setting the proper interrupt level in the context
- * - initializing the floating point context
- *
- * This routine generally does not set any unnecessary register
- * in the context. The state of the "general data" registers is
- * undefined at task start time.
- *
- * @param[in] _the_context is the context structure to be initialized
- * @param[in] _stack_base is the lowest physical address of this task's stack
- * @param[in] _size is the size of this task's stack
- * @param[in] _isr is the interrupt disable level
- * @param[in] _entry_point is the thread's entry point. This is
- * always @a _Thread_Handler
- * @param[in] _is_fp is TRUE if the thread is to be a floating
- * point thread. This is typically only used on CPUs where the
- * FPU may be easily disabled by software such as on the SPARC
- * where the PSR contains an enable FPU bit.
- *
- * Port Specific Information:
- *
- * See implementation in cpu.c
+ * @ingroup CPUContext
+ * Initialize the context to a state suitable for starting a
+ * task after a context restore operation. Generally, this
+ * involves:
+ *
+ * - setting a starting address
+ * - preparing the stack
+ * - preparing the stack and frame pointers
+ * - setting the proper interrupt level in the context
+ * - initializing the floating point context
+ *
+ * This routine generally does not set any unnecessary register
+ * in the context. The state of the "general data" registers is
+ * undefined at task start time.
+ *
+ * @param[in] _the_context is the context structure to be initialized
+ * @param[in] _stack_base is the lowest physical address of this task's stack
+ * @param[in] _size is the size of this task's stack
+ * @param[in] _isr is the interrupt disable level
+ * @param[in] _entry_point is the thread's entry point. This is
+ * always @a _Thread_Handler
+ * @param[in] _is_fp is TRUE if the thread is to be a floating
+ * point thread. This is typically only used on CPUs where the
+ * FPU may be easily disabled by software such as on the SPARC
+ * where the PSR contains an enable FPU bit.
+ *
+ * Port Specific Information:
+ *
+ * See implementation in cpu.c
*/
void _CPU_Context_Initialize(
Context_Control *the_context,
@@ -832,65 +842,65 @@ void _CPU_Context_Initialize(
);
/**
- * This routine is responsible for somehow restarting the currently
- * executing task. If you are lucky, then all that is necessary
- * is restoring the context. Otherwise, there will need to be
- * a special assembly routine which does something special in this
- * case. For many ports, simply adding a label to the restore path
- * of @ref _CPU_Context_switch will work. On other ports, it may be
- * possibly to load a few arguments and jump to the restore path. It will
- * not work if restarting self conflicts with the stack frame
- * assumptions of restoring a context.
+ * This routine is responsible for somehow restarting the currently
+ * executing task. If you are lucky, then all that is necessary
+ * is restoring the context. Otherwise, there will need to be
+ * a special assembly routine which does something special in this
+ * case. For many ports, simply adding a label to the restore path
+ * of @ref _CPU_Context_switch will work. On other ports, it may be
+ * possibly to load a few arguments and jump to the restore path. It will
+ * not work if restarting self conflicts with the stack frame
+ * assumptions of restoring a context.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define _CPU_Context_Restart_self( _the_context ) \
_CPU_Context_restore( (_the_context) );
/**
- * @ingroup CPUContext
- * The purpose of this macro is to allow the initial pointer into
- * a floating point context area (used to save the floating point
- * context) to be at an arbitrary place in the floating point
- * context area.
+ * @ingroup CPUContext
+ * The purpose of this macro is to allow the initial pointer into
+ * a floating point context area (used to save the floating point
+ * context) to be at an arbitrary place in the floating point
+ * context area.
*
- * This is necessary because some FP units are designed to have
- * their context saved as a stack which grows into lower addresses.
- * Other FP units can be saved by simply moving registers into offsets
- * from the base of the context area. Finally some FP units provide
- * a "dump context" instruction which could fill in from high to low
- * or low to high based on the whim of the CPU designers.
+ * This is necessary because some FP units are designed to have
+ * their context saved as a stack which grows into lower addresses.
+ * Other FP units can be saved by simply moving registers into offsets
+ * from the base of the context area. Finally some FP units provide
+ * a "dump context" instruction which could fill in from high to low
+ * or low to high based on the whim of the CPU designers.
*
- * @param[in] _base is the lowest physical address of the floating point
- * context area
- * @param[in] _offset is the offset into the floating point area
+ * @param[in] _base is the lowest physical address of the floating point
+ * context area
+ * @param[in] _offset is the offset into the floating point area
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define _CPU_Context_Fp_start( _base, _offset ) \
( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
/**
- * This routine initializes the FP context area passed to it to.
- * There are a few standard ways in which to initialize the
- * floating point context. The code included for this macro assumes
- * that this is a CPU in which a "initial" FP context was saved into
- * @a _CPU_Null_fp_context and it simply copies it to the destination
- * context passed to it.
+ * This routine initializes the FP context area passed to it to.
+ * There are a few standard ways in which to initialize the
+ * floating point context. The code included for this macro assumes
+ * that this is a CPU in which a "initial" FP context was saved into
+ * @a _CPU_Null_fp_context and it simply copies it to the destination
+ * context passed to it.
*
- * Other floating point context save/restore models include:
- * -# not doing anything, and
- * -# putting a "null FP status word" in the correct place in the FP context.
+ * Other floating point context save/restore models include:
+ * -# not doing anything, and
+ * -# putting a "null FP status word" in the correct place in the FP context.
*
- * @param[in] _destination is the floating point context area
+ * @param[in] _destination is the floating point context area
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define _CPU_Context_Initialize_fp( _destination ) \
{ \
@@ -902,13 +912,13 @@ void _CPU_Context_Initialize(
/* Fatal Error manager macros */
/**
- * This routine copies _error into a known place -- typically a stack
- * location or a register, optionally disables interrupts, and
- * halts/stops the CPU.
+ * This routine copies _error into a known place -- typically a stack
+ * location or a register, optionally disables interrupts, and
+ * halts/stops the CPU.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define _CPU_Fatal_halt( _error ) \
{ \
@@ -925,68 +935,67 @@ void _CPU_Context_Initialize(
/* Bitfield handler macros */
/**
- * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
+ * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
+ *
+ * This set of routines are used to implement fast searches for
+ * the most important ready task.
*
- * This set of routines are used to implement fast searches for
- * the most important ready task.
+ * @{
*/
/**
- * @ingroup CPUBitfield
- * This definition is set to TRUE if the port uses the generic bitfield
- * manipulation implementation.
+ * This definition is set to TRUE if the port uses the generic bitfield
+ * manipulation implementation.
*/
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
/**
- * @ingroup CPUBitfield
- * This definition is set to TRUE if the port uses the data tables provided
- * by the generic bitfield manipulation implementation.
- * This can occur when actually using the generic bitfield manipulation
- * implementation or when implementing the same algorithm in assembly
- * language for improved performance. It is unlikely that a port will use
- * the data if it has a bitfield scan instruction.
+ * This definition is set to TRUE if the port uses the data tables provided
+ * by the generic bitfield manipulation implementation.
+ * This can occur when actually using the generic bitfield manipulation
+ * implementation or when implementing the same algorithm in assembly
+ * language for improved performance. It is unlikely that a port will use
+ * the data if it has a bitfield scan instruction.
*/
#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
/**
- * @ingroup CPUBitfield
- * This routine sets @a _output to the bit number of the first bit
- * set in @a _value. @a _value is of CPU dependent type
- * @a Priority_bit_map_Control. This type may be either 16 or 32 bits
- * wide although only the 16 least significant bits will be used.
- *
- * There are a number of variables in using a "find first bit" type
- * instruction.
- *
- * -# What happens when run on a value of zero?
- * -# Bits may be numbered from MSB to LSB or vice-versa.
- * -# The numbering may be zero or one based.
- * -# The "find first bit" instruction may search from MSB or LSB.
- *
- * RTEMS guarantees that (1) will never happen so it is not a concern.
- * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
- * @ref _CPU_Priority_bits_index. These three form a set of routines
- * which must logically operate together. Bits in the _value are
- * set and cleared based on masks built by @ref _CPU_Priority_Mask.
- * The basic major and minor values calculated by @ref _Priority_Major
- * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
- * to properly range between the values returned by the "find first bit"
- * instruction. This makes it possible for @ref _Priority_Get_highest to
- * calculate the major and directly index into the minor table.
- * This mapping is necessary to ensure that 0 (a high priority major/minor)
- * is the first bit found.
- *
- * This entire "find first bit" and mapping process depends heavily
- * on the manner in which a priority is broken into a major and minor
- * components with the major being the 4 MSB of a priority and minor
- * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
- * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
- * to the lowest priority.
- *
- * If your CPU does not have a "find first bit" instruction, then
- * there are ways to make do without it. Here are a handful of ways
- * to implement this in software:
+ * This routine sets @a _output to the bit number of the first bit
+ * set in @a _value. @a _value is of CPU dependent type
+ * @a Priority_bit_map_Control. This type may be either 16 or 32 bits
+ * wide although only the 16 least significant bits will be used.
+ *
+ * There are a number of variables in using a "find first bit" type
+ * instruction.
+ *
+ * -# What happens when run on a value of zero?
+ * -# Bits may be numbered from MSB to LSB or vice-versa.
+ * -# The numbering may be zero or one based.
+ * -# The "find first bit" instruction may search from MSB or LSB.
+ *
+ * RTEMS guarantees that (1) will never happen so it is not a concern.
+ * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
+ * @ref _CPU_Priority_bits_index. These three form a set of routines
+ * which must logically operate together. Bits in the _value are
+ * set and cleared based on masks built by @ref _CPU_Priority_Mask.
+ * The basic major and minor values calculated by @ref _Priority_Major
+ * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
+ * to properly range between the values returned by the "find first bit"
+ * instruction. This makes it possible for @ref _Priority_Get_highest to
+ * calculate the major and directly index into the minor table.
+ * This mapping is necessary to ensure that 0 (a high priority major/minor)
+ * is the first bit found.
+ *
+ * This entire "find first bit" and mapping process depends heavily
+ * on the manner in which a priority is broken into a major and minor
+ * components with the major being the 4 MSB of a priority and minor
+ * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
+ * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
+ * to the lowest priority.
+ *
+ * If your CPU does not have a "find first bit" instruction, then
+ * there are ways to make do without it. Here are a handful of ways
+ * to implement this in software:
*
@verbatim
- a series of 16 bit test instructions
@@ -1003,15 +1012,15 @@ void _CPU_Context_Initialize(
_number += bit_set_table[ _value ]
@endverbatim
- * where bit_set_table[ 16 ] has values which indicate the first
- * bit set
+ * where bit_set_table[ 16 ] has values which indicate the first
+ * bit set
*
- * @param[in] _value is the value to be scanned
- * @param[in] _output is the first bit set
+ * @param[in] _value is the value to be scanned
+ * @param[in] _output is the first bit set
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
@@ -1024,14 +1033,16 @@ void _CPU_Context_Initialize(
/* end of Bitfield handler macros */
+/** @} */
+
/**
- * This routine builds the mask which corresponds to the bit fields
- * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion
- * for that routine.
+ * This routine builds the mask which corresponds to the bit fields
+ * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion
+ * for that routine.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
@@ -1041,17 +1052,17 @@ void _CPU_Context_Initialize(
#endif
/**
- * @ingroup CPUBitfield
- * This routine translates the bit numbers returned by
- * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
- * a major or minor component of a priority. See the discussion
- * for that routine.
+ * @ingroup CPUBitfield
+ * This routine translates the bit numbers returned by
+ * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
+ * a major or minor component of a priority. See the discussion
+ * for that routine.
*
- * @param[in] _priority is the major or minor number to translate
+ * @param[in] _priority is the major or minor number to translate
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
@@ -1065,27 +1076,27 @@ void _CPU_Context_Initialize(
/* functions */
/**
- * @brief CPU Initialize
- * This routine performs CPU dependent initialization.
+ * @brief CPU initialize.
+ * This routine performs CPU dependent initialization.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
void _CPU_Initialize(void);
/**
- * @ingroup CPUInterrupt
- * This routine installs a "raw" interrupt handler directly into the
- * processor's vector table.
+ * @ingroup CPUInterrupt
+ * This routine installs a "raw" interrupt handler directly into the
+ * processor's vector table.
*
- * @param[in] vector is the vector number
- * @param[in] new_handler is the raw ISR handler to install
- * @param[in] old_handler is the previously installed ISR Handler
+ * @param[in] vector is the vector number
+ * @param[in] new_handler is the raw ISR handler to install
+ * @param[in] old_handler is the previously installed ISR Handler
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
@@ -1094,16 +1105,16 @@ void _CPU_ISR_install_raw_handler(
);
/**
- * @ingroup CPUInterrupt
- * This routine installs an interrupt vector.
+ * @ingroup CPUInterrupt
+ * This routine installs an interrupt vector.
*
- * @param[in] vector is the vector number
- * @param[in] new_handler is the RTEMS ISR handler to install
- * @param[in] old_handler is the previously installed ISR Handler
+ * @param[in] vector is the vector number
+ * @param[in] new_handler is the RTEMS ISR handler to install
+ * @param[in] old_handler is the previously installed ISR Handler
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
void _CPU_ISR_install_vector(
uint32_t vector,
@@ -1112,40 +1123,45 @@ void _CPU_ISR_install_vector(
);
/**
- * @ingroup CPUInterrupt
- * This routine installs the hardware interrupt stack pointer.
+ * @ingroup CPUInterrupt
+ * This routine installs the hardware interrupt stack pointer.
*
- * @note It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
- * is TRUE.
+ * @note It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
+ * is TRUE.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
void _CPU_Install_interrupt_stack( void );
/**
- * This routine is the CPU dependent IDLE thread body.
+ * This routine is the CPU dependent IDLE thread body.
*
- * @note It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
- * is TRUE.
+ * @note It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
+ * is TRUE.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
void *_CPU_Thread_Idle_body( uintptr_t ignored );
/**
- * @ingroup CPUContext
- * This routine switches from the run context to the heir context.
+ * @addtogroup CPUContext
*
- * @param[in] run points to the context of the currently executing task
- * @param[in] heir points to the context of the heir task
+ * @{
+ */
+
+/**
+ * This routine switches from the run context to the heir context.
*
- * Port Specific Information:
+ * @param[in] run points to the context of the currently executing task
+ * @param[in] heir points to the context of the heir task
*
- * XXX document implementation including references if appropriate
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
*/
void _CPU_Context_switch(
Context_Control *run,
@@ -1153,90 +1169,89 @@ void _CPU_Context_switch(
);
/**
- * @ingroup CPUContext
- * This routine is generally used only to restart self in an
- * efficient manner. It may simply be a label in @ref _CPU_Context_switch.
+ * This routine is generally used only to restart self in an
+ * efficient manner. It may simply be a label in @ref _CPU_Context_switch.
*
- * @param[in] new_context points to the context to be restored.
+ * @param[in] new_context points to the context to be restored.
*
- * @note May be unnecessary to reload some registers.
+ * @note May be unnecessary to reload some registers.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
void _CPU_Context_restore(
Context_Control *new_context
) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
/**
- * @ingroup CPUContext
- * This routine saves the floating point context passed to it.
+ * This routine saves the floating point context passed to it.
*
- * @param[in] fp_context_ptr is a pointer to a pointer to a floating
- * point context area
+ * @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ * point context area
*
- * @return on output @a *fp_context_ptr will contain the address that
- * should be used with @ref _CPU_Context_restore_fp to restore this context.
+ * @return on output @a *fp_context_ptr will contain the address that
+ * should be used with @ref _CPU_Context_restore_fp to restore this context.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
void _CPU_Context_save_fp(
Context_Control_fp **fp_context_ptr
);
/**
- * @ingroup CPUContext
- * This routine restores the floating point context passed to it.
+ * This routine restores the floating point context passed to it.
*
- * @param[in] fp_context_ptr is a pointer to a pointer to a floating
- * point context area to restore
+ * @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ * point context area to restore
*
- * @return on output @a *fp_context_ptr will contain the address that
- * should be used with @ref _CPU_Context_save_fp to save this context.
+ * @return on output @a *fp_context_ptr will contain the address that
+ * should be used with @ref _CPU_Context_save_fp to save this context.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
void _CPU_Context_restore_fp(
Context_Control_fp **fp_context_ptr
);
+/** @} */
+
/* FIXME */
typedef CPU_Interrupt_frame CPU_Exception_frame;
void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
/**
- * @ingroup CPUEndian
- * The following routine swaps the endian format of an unsigned int.
- * It must be static because it is referenced indirectly.
+ * @ingroup CPUEndian
+ * The following routine swaps the endian format of an unsigned int.
+ * It must be static because it is referenced indirectly.
*
- * This version will work on any processor, but if there is a better
- * way for your CPU PLEASE use it. The most common way to do this is to:
+ * This version will work on any processor, but if there is a better
+ * way for your CPU PLEASE use it. The most common way to do this is to:
*
- * swap least significant two bytes with 16-bit rotate
- * swap upper and lower 16-bits
- * swap most significant two bytes with 16-bit rotate
+ * swap least significant two bytes with 16-bit rotate
+ * swap upper and lower 16-bits
+ * swap most significant two bytes with 16-bit rotate
*
- * Some CPUs have special instructions which swap a 32-bit quantity in
- * a single instruction (e.g. i486). It is probably best to avoid
- * an "endian swapping control bit" in the CPU. One good reason is
- * that interrupts would probably have to be disabled to ensure that
- * an interrupt does not try to access the same "chunk" with the wrong
- * endian. Another good reason is that on some CPUs, the endian bit
- * endianness for ALL fetches -- both code and data -- so the code
- * will be fetched incorrectly.
+ * Some CPUs have special instructions which swap a 32-bit quantity in
+ * a single instruction (e.g. i486). It is probably best to avoid
+ * an "endian swapping control bit" in the CPU. One good reason is
+ * that interrupts would probably have to be disabled to ensure that
+ * an interrupt does not try to access the same "chunk" with the wrong
+ * endian. Another good reason is that on some CPUs, the endian bit
+ * endianness for ALL fetches -- both code and data -- so the code
+ * will be fetched incorrectly.
*
- * @param[in] value is the value to be swapped
- * @return the value after being endian swapped
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
static inline uint32_t CPU_swap_u32(
uint32_t value
@@ -1254,11 +1269,11 @@ static inline uint32_t CPU_swap_u32(
}
/**
- * @ingroup CPUEndian
- * This routine swaps a 16 bir quantity.
+ * @ingroup CPUEndian
+ * This routine swaps a 16 bir quantity.
*
- * @param[in] value is the value to be swapped
- * @return the value after being endian swapped
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
*/
#define CPU_swap_u16( value ) \
(((value&0xff) << 8) | ((value >> 8)&0xff))
diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h b/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h
index 7d23bc5a9a..f9543f15a7 100644
--- a/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h
+++ b/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h
@@ -1,10 +1,12 @@
/**
- * @file rtems/score/cpu_asm.h
+ * @file
+ *
+ * @brief Blackfin Assembly File
+ *
+ * Defines a couple of Macros used in cpu_asm.S
*/
/*
- * Defines a couple of Macros used in cpu_asm.S
- *
* COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
* written by Alain Schaefer <alain.schaefer@easc.ch>
* and Antonio Giovanini <antonio@atos.com.br>
diff --git a/cpukit/score/cpu/bfin/rtems/score/types.h b/cpukit/score/cpu/bfin/rtems/score/types.h
index 4f734bb033..5d4e12eb95 100644
--- a/cpukit/score/cpu/bfin/rtems/score/types.h
+++ b/cpukit/score/cpu/bfin/rtems/score/types.h
@@ -1,7 +1,13 @@
-/*
- * This include file contains type definitions pertaining to the
- * Blackfin processor family.
+/**
+ * @file
+ *
+ * @brief Blackfin CPU Type Definitions
*
+ * This include file contains type definitions pertaining to the
+ * Blackfin processor family.
+ */
+
+/*
* COPYRIGHT (c) 1989-2006.
* On-Line Applications Research Corporation (OAR).
*
diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu.h b/cpukit/score/cpu/nios2/rtems/score/cpu.h
index 7beb4ec06f..6db6d1d46c 100644
--- a/cpukit/score/cpu/nios2/rtems/score/cpu.h
+++ b/cpukit/score/cpu/nios2/rtems/score/cpu.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief Altera Nios II CPU Department Source
+ */
+
/*
* Copyright (c) 2011 embedded brains GmbH
*
@@ -253,8 +259,8 @@ void _CPU_Initialize_vectors( void );
* _CPU_ISR_Disable(). The value is not modified.
*
* This flash code is optimal for all Nios II configurations. The rdctl does
- * not flush the pipeline and has only a late result penalty. The wrctl on the
- * other hand leads to a pipeline flush.
+ * not flush the pipeline and has only a late result penalty. The wrctl on
+ * the other hand leads to a pipeline flush.
*/
#define _CPU_ISR_Flash( _isr_cookie ) \
do { \
@@ -319,14 +325,12 @@ void _CPU_Context_Initialize(
void _CPU_Fatal_halt( uint32_t _error ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
/**
- * @brief CPU Initialize
- *
+ * @brief CPU initialization.
*/
void _CPU_Initialize( void );
/**
- * @brief CPU ISR Install Raw Handler
- *
+ * @brief CPU ISR install raw handler.
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
@@ -335,8 +339,7 @@ void _CPU_ISR_install_raw_handler(
);
/**
- * @brief CPU ISR Install Vector.
- *
+ * @brief CPU ISR install vector.
*/
void _CPU_ISR_install_vector(
uint32_t vector,
diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h b/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h
index d0572d8b2a..8c0e046c34 100644
--- a/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h
+++ b/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h
@@ -1,12 +1,14 @@
/**
- * @file rtems/score/cpu_asm.h
+ * @file
+ *
+ * @brief Altera Nios II Assembly File
+ *
+ * Very loose template for an include file for the cpu_asm.? file
+ * if it is implemented as a ".S" file (preprocessed by cpp) instead
+ * of a ".s" file (preprocessed by gm4 or gasp).
*/
/*
- * Very loose template for an include file for the cpu_asm.? file
- * if it is implemented as a ".S" file (preprocessed by cpp) instead
- * of a ".s" file (preprocessed by gm4 or gasp).
- *
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
diff --git a/cpukit/score/cpu/nios2/rtems/score/types.h b/cpukit/score/cpu/nios2/rtems/score/types.h
index 48c1ebacb9..13a4ecba94 100644
--- a/cpukit/score/cpu/nios2/rtems/score/types.h
+++ b/cpukit/score/cpu/nios2/rtems/score/types.h
@@ -1,11 +1,13 @@
/**
- * @file rtems/score/types.h
+ * @file
+ *
+ * @brief Altera Nios II CPU Type Definitions
+ *
+ * This include file contains type definitions pertaining to the
+ * Altera Nios II processor family.
*/
/*
- * This include file contains type definitions pertaining to the
- * Altera Nios II processor family.
- *
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
diff --git a/cpukit/score/cpu/sh/rtems/asm.h b/cpukit/score/cpu/sh/rtems/asm.h
index b2cbce6020..d7ad694365 100644
--- a/cpukit/score/cpu/sh/rtems/asm.h
+++ b/cpukit/score/cpu/sh/rtems/asm.h
@@ -1,20 +1,23 @@
/**
- * @file rtems/asm.h
+ * @file
*
- * This include file attempts to address the problems
- * caused by incompatible flavors of assemblers and
- * toolsets. It primarily addresses variations in the
- * use of leading underscores on symbols and the requirement
- * that register names be preceded by a %.
+ * @brief Address the Problems Caused by Incompatible Flavor of
+ * Assemblers and Toolsets
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets. It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ *
+ * @note The spacing in the use of these macros
+ * is critical to them working as advertised.
*/
/*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
- * NOTE: The spacing in the use of these macros
- * is critical to them working as advertised.
- *
* COPYRIGHT:
*
* This file is based on similar code found in newlib available
diff --git a/cpukit/score/cpu/sh/rtems/score/sh.h b/cpukit/score/cpu/sh/rtems/score/sh.h
index 507a812bc7..e7ab9c0850 100644
--- a/cpukit/score/cpu/sh/rtems/score/sh.h
+++ b/cpukit/score/cpu/sh/rtems/score/sh.h
@@ -1,11 +1,13 @@
/**
- * @file rtems/score/sh.h
+ * @file
+ *
+ * @brief Hitachi SH CPU Department Source
+ *
+ * This include file contains information pertaining to the Hitachi SH
+ * processor.
*/
/*
- * This include file contains information pertaining to the Hitachi SH
- * processor.
- *
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
diff --git a/cpukit/score/cpu/sh/rtems/score/sh_io.h b/cpukit/score/cpu/sh/rtems/score/sh_io.h
index 6cb1ffcb0f..fcbdbcee42 100644
--- a/cpukit/score/cpu/sh/rtems/score/sh_io.h
+++ b/cpukit/score/cpu/sh/rtems/score/sh_io.h
@@ -1,11 +1,13 @@
/**
- * @file rtems/score/sh_io.h
+ * @file
+ *
+ * @brief Macros to Access Memory Mapped Devices on the SH7000-Architecture
+ *
+ * These are some macros to access memory mapped devices
+ * on the SH7000-architecture.
*/
/*
- * These are some macros to access memory mapped devices
- * on the SH7000-architecture.
- *
* Inspired from the linux kernel's include/asm/io.h
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
diff --git a/cpukit/score/cpu/sh/rtems/score/types.h b/cpukit/score/cpu/sh/rtems/score/types.h
index 8f0b06c79c..5943a42bc9 100644
--- a/cpukit/score/cpu/sh/rtems/score/types.h
+++ b/cpukit/score/cpu/sh/rtems/score/types.h
@@ -1,11 +1,13 @@
/**
- * @file rtems/score/types.h
+ * @file
+ *
+ * @brief Hitachi SH CPU Type Definitions
+ *
+ * This include file contains information pertaining to the Hitachi SH
+ * processor.
*/
/*
- * This include file contains information pertaining to the Hitachi SH
- * processor.
- *
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
diff --git a/cpukit/score/cpu/v850/rtems/asm.h b/cpukit/score/cpu/v850/rtems/asm.h
index 09e64da442..265e4967ae 100644
--- a/cpukit/score/cpu/v850/rtems/asm.h
+++ b/cpukit/score/cpu/v850/rtems/asm.h
@@ -1,26 +1,27 @@
/**
- * @file rtems/asm.h
+ * @file
*
- * This include file attempts to address the problems
- * caused by incompatible flavors of assemblers and
- * toolsets. It primarily addresses variations in the
- * use of leading underscores on symbols and the requirement
- * that register names be preceded by a %.
+ * @brief Address the Problems Caused by Incompatible Flavor of
+ * Assemblers and Toolsets
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets. It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ *
+ * @note The spacing in the use of these macros
+ * is critical to them working as advertised.
*/
/*
- * NOTE: The spacing in the use of these macros
- * is critical to them working as advertised.
- *
* COPYRIGHT:
*
* This file is based on similar code found in newlib available
* from ftp.cygnus.com. The file which was used had no copyright
* notice. This file is freely distributable as long as the source
* of the file is noted. This file is:
- */
-
-/*
+ *
* COPYRIGHT (c) 1994-2012.
* On-Line Applications Research Corporation (OAR).
*/
@@ -40,24 +41,24 @@
#ifndef __USER_LABEL_PREFIX__
/**
- * Recent versions of GNU cpp define variables which indicate the
- * need for underscores and percents. If not using GNU cpp or
- * the version does not support this, then you will obviously
- * have to define these as appropriate.
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents. If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
*
- * This symbol is prefixed to all C program symbols.
+ * This symbol is prefixed to all C program symbols.
*/
#define __USER_LABEL_PREFIX__ _
#endif
#ifndef __REGISTER_PREFIX__
/**
- * Recent versions of GNU cpp define variables which indicate the
- * need for underscores and percents. If not using GNU cpp or
- * the version does not support this, then you will obviously
- * have to define these as appropriate.
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents. If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
*
- * This symbol is prefixed to all register names.
+ * This symbol is prefixed to all register names.
*/
#define __REGISTER_PREFIX__
#endif
@@ -97,8 +98,9 @@
#define BEGIN_DATA
/** This macro is used to denote the end of a data section. */
#define END_DATA
-/** This macro is used to denote the beginning of the
- * unitialized data section.
+/**
+ * This macro is used to denote the beginning of the
+ * unitialized data section.
*/
#define BEGIN_BSS
/** This macro is used to denote the end of the unitialized data section. */
@@ -107,18 +109,18 @@
#define END
/**
- * This macro is used to declare a public global symbol.
+ * This macro is used to declare a public global symbol.
*
- * @note This must be tailored for a particular flavor of the C compiler.
- * They may need to put underscores in front of the symbols.
+ * @note This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
*/
#define PUBLIC(sym) .globl SYM (sym)
/**
- * This macro is used to prototype a public global symbol.
+ * This macro is used to prototype a public global symbol.
*
- * @note This must be tailored for a particular flavor of the C compiler.
- * They may need to put underscores in front of the symbols.
+ * @note This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
*/
#define EXTERN(sym) .globl SYM (sym)
diff --git a/cpukit/score/cpu/v850/rtems/score/cpu.h b/cpukit/score/cpu/v850/rtems/score/cpu.h
index b6fb59d7b6..0e3f8eebab 100644
--- a/cpukit/score/cpu/v850/rtems/score/cpu.h
+++ b/cpukit/score/cpu/v850/rtems/score/cpu.h
@@ -1,10 +1,10 @@
/**
- * @file rtems/score/cpu.h
- */
-
-/*
- * This include file contains information pertaining to the v850
- * processor.
+ * @file
+ *
+ * @brief V850 CPU Department Source
+ *
+ * This include file contains information pertaining to the v850
+ * processor.
*/
/*
@@ -29,418 +29,421 @@ extern "C" {
/* conditional compilation parameters */
/**
- * Should the calls to @ref _Thread_Enable_dispatch be inlined?
+ * Should the calls to @ref _Thread_Enable_dispatch be inlined?
*
- * If TRUE, then they are inlined.
- * If FALSE, then a subroutine call is made.
+ * If TRUE, then they are inlined.
+ * If FALSE, then a subroutine call is made.
*
- * This conditional is an example of the classic trade-off of size
- * versus speed. Inlining the call (TRUE) typically increases the
- * size of RTEMS while speeding up the enabling of dispatching.
+ * This conditional is an example of the classic trade-off of size
+ * versus speed. Inlining the call (TRUE) typically increases the
+ * size of RTEMS while speeding up the enabling of dispatching.
*
- * @note In general, the @ref _Thread_Dispatch_disable_level will
- * only be 0 or 1 unless you are in an interrupt handler and that
- * interrupt handler invokes the executive.] When not inlined
- * something calls @ref _Thread_Enable_dispatch which in turns calls
- * @ref _Thread_Dispatch. If the enable dispatch is inlined, then
- * one subroutine call is avoided entirely.
+ * @note In general, the @ref _Thread_Dispatch_disable_level will
+ * only be 0 or 1 unless you are in an interrupt handler and that
+ * interrupt handler invokes the executive.] When not inlined
+ * something calls @ref _Thread_Enable_dispatch which in turns calls
+ * @ref _Thread_Dispatch. If the enable dispatch is inlined, then
+ * one subroutine call is avoided entirely.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * The v850 is a RISC CPU which typically has enough memory to justify
- * the inlining of this method.
+ * The v850 is a RISC CPU which typically has enough memory to justify
+ * the inlining of this method.
*/
#define CPU_INLINE_ENABLE_DISPATCH TRUE
/**
- * Should the body of the search loops in _Thread_queue_Enqueue_priority
- * be unrolled one time? In unrolled each iteration of the loop examines
- * two "nodes" on the chain being searched. Otherwise, only one node
- * is examined per iteration.
- *
- * If TRUE, then the loops are unrolled.
- * If FALSE, then the loops are not unrolled.
- *
- * The primary factor in making this decision is the cost of disabling
- * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
- * body of the loop. On some CPUs, the flash is more expensive than
- * one iteration of the loop body. In this case, it might be desirable
- * to unroll the loop. It is important to note that on some CPUs, this
- * code is the longest interrupt disable period in RTEMS. So it is
- * necessary to strike a balance when setting this parameter.
- *
- * Port Specific Information:
- *
- * The v850 is a RISC CPU which typically has enough memory to justify
- * the unrolling of this method.
+ * Should the body of the search loops in _Thread_queue_Enqueue_priority
+ * be unrolled one time? In unrolled each iteration of the loop examines
+ * two "nodes" on the chain being searched. Otherwise, only one node
+ * is examined per iteration.
+ *
+ * If TRUE, then the loops are unrolled.
+ * If FALSE, then the loops are not unrolled.
+ *
+ * The primary factor in making this decision is the cost of disabling
+ * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
+ * body of the loop. On some CPUs, the flash is more expensive than
+ * one iteration of the loop body. In this case, it might be desirable
+ * to unroll the loop. It is important to note that on some CPUs, this
+ * code is the longest interrupt disable period in RTEMS. So it is
+ * necessary to strike a balance when setting this parameter.
+ *
+ * Port Specific Information:
+ *
+ * The v850 is a RISC CPU which typically has enough memory to justify
+ * the unrolling of this method.
*/
#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
/**
- * Does RTEMS manage a dedicated interrupt stack in software?
+ * Does RTEMS manage a dedicated interrupt stack in software?
*
- * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
- * If FALSE, nothing is done.
+ * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
+ * If FALSE, nothing is done.
*
- * If the CPU supports a dedicated interrupt stack in hardware,
- * then it is generally the responsibility of the BSP to allocate it
- * and set it up.
+ * If the CPU supports a dedicated interrupt stack in hardware,
+ * then it is generally the responsibility of the BSP to allocate it
+ * and set it up.
*
- * If the CPU does not support a dedicated interrupt stack, then
- * the porter has two options: (1) execute interrupts on the
- * stack of the interrupted task, and (2) have RTEMS manage a dedicated
- * interrupt stack.
+ * If the CPU does not support a dedicated interrupt stack, then
+ * the porter has two options: (1) execute interrupts on the
+ * stack of the interrupted task, and (2) have RTEMS manage a dedicated
+ * interrupt stack.
*
- * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
*
- * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
- * possible that both are FALSE for a particular CPU. Although it
- * is unclear what that would imply about the interrupt processing
- * procedure on that CPU.
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
+ * possible that both are FALSE for a particular CPU. Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * The v850 does not have support for a hardware interrupt stack.
+ * The v850 does not have support for a hardware interrupt stack.
*/
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
/**
- * Does the CPU follow the simple vectored interrupt model?
+ * Does the CPU follow the simple vectored interrupt model?
*
- * If TRUE, then RTEMS allocates the vector table it internally manages.
- * If FALSE, then the BSP is assumed to allocate and manage the vector
- * table
+ * If TRUE, then RTEMS allocates the vector table it internally manages.
+ * If FALSE, then the BSP is assumed to allocate and manage the vector
+ * table
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * This port uses the Progammable Interrupt Controller interrupt model.
+ * This port uses the Progammable Interrupt Controller interrupt model.
*/
#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
/**
- * Does this CPU have hardware support for a dedicated interrupt stack?
+ * Does this CPU have hardware support for a dedicated interrupt stack?
*
- * If TRUE, then it must be installed during initialization.
- * If FALSE, then no installation is performed.
+ * If TRUE, then it must be installed during initialization.
+ * If FALSE, then no installation is performed.
*
- * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
*
- * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
- * possible that both are FALSE for a particular CPU. Although it
- * is unclear what that would imply about the interrupt processing
- * procedure on that CPU.
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
+ * possible that both are FALSE for a particular CPU. Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * The v850 does not have support for a hardware interrupt stack.
+ * The v850 does not have support for a hardware interrupt stack.
*/
#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
/**
- * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
+ * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
*
- * If TRUE, then the memory is allocated during initialization.
- * If FALSE, then the memory is allocated during initialization.
+ * If TRUE, then the memory is allocated during initialization.
+ * If FALSE, then the memory is allocated during initialization.
*
- * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
+ * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/**
- * @def CPU_HARDWARE_FP
+ * @def CPU_HARDWARE_FP
*
- * Does the CPU have hardware floating point?
+ * Does the CPU have hardware floating point?
*
- * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
- * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
*
- * If there is a FP coprocessor such as the i387 or mc68881, then
- * the answer is TRUE.
+ * If there is a FP coprocessor such as the i387 or mc68881, then
+ * the answer is TRUE.
*
- * The macro name "V850_HAS_FPU" should be made CPU specific.
- * It indicates whether or not this CPU model has FP support. For
- * example, it would be possible to have an i386_nofp CPU model
- * which set this to false to indicate that you have an i386 without
- * an i387 and wish to leave floating point support out of RTEMS.
+ * The macro name "V850_HAS_FPU" should be made CPU specific.
+ * It indicates whether or not this CPU model has FP support. For
+ * example, it would be possible to have an i386_nofp CPU model
+ * which set this to false to indicate that you have an i386 without
+ * an i387 and wish to leave floating point support out of RTEMS.
*/
/**
- * @def CPU_SOFTWARE_FP
- *
- * Does the CPU have no hardware floating point and GCC provides a
- * software floating point implementation which must be context
- * switched?
- *
- * This feature conditional is used to indicate whether or not there
- * is software implemented floating point that must be context
- * switched. The determination of whether or not this applies
- * is very tool specific and the state saved/restored is also
- * compiler specific.
- *
- * Port Specific Information:
- *
- * Some v850 models do have IEEE hardware floating point support but
- * they do not have any special registers to save or bit(s) which
- * determine if the FPU is enabled. In short, there appears to be nothing
- * related to the floating point operations which impact the RTEMS
- * thread context switch. Thus from an RTEMS perspective, there is really
- * no FPU to manage.
+ * @def CPU_SOFTWARE_FP
+ *
+ * Does the CPU have no hardware floating point and GCC provides a
+ * software floating point implementation which must be context
+ * switched?
+ *
+ * This feature conditional is used to indicate whether or not there
+ * is software implemented floating point that must be context
+ * switched. The determination of whether or not this applies
+ * is very tool specific and the state saved/restored is also
+ * compiler specific.
+ *
+ * Port Specific Information:
+ *
+ * Some v850 models do have IEEE hardware floating point support but
+ * they do not have any special registers to save or bit(s) which
+ * determine if the FPU is enabled. In short, there appears to be nothing
+ * related to the floating point operations which impact the RTEMS
+ * thread context switch. Thus from an RTEMS perspective, there is really
+ * no FPU to manage.
*/
#define CPU_HARDWARE_FP FALSE
#define CPU_SOFTWARE_FP FALSE
/**
- * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
+ * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
*
- * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
- * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
*
- * So far, the only CPUs in which this option has been used are the
- * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and
- * gcc both implicitly used the floating point registers to perform
- * integer multiplies. Similarly, the PowerPC port of gcc has been
- * seen to allocate floating point local variables and touch the FPU
- * even when the flow through a subroutine (like vfprintf()) might
- * not use floating point formats.
+ * So far, the only CPUs in which this option has been used are the
+ * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and
+ * gcc both implicitly used the floating point registers to perform
+ * integer multiplies. Similarly, the PowerPC port of gcc has been
+ * seen to allocate floating point local variables and touch the FPU
+ * even when the flow through a subroutine (like vfprintf()) might
+ * not use floating point formats.
*
- * If a function which you would not think utilize the FP unit DOES,
- * then one can not easily predict which tasks will use the FP hardware.
- * In this case, this option should be TRUE.
+ * If a function which you would not think utilize the FP unit DOES,
+ * then one can not easily predict which tasks will use the FP hardware.
+ * In this case, this option should be TRUE.
*
- * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * This should be false until it has been demonstrated that gcc for the
- * v850 generates FPU code when it is unexpected. But even this would
- * not matter since there are no FP specific registers or bits which
- * would be corrupted if an FP operation occurred in an integer only
- * thread.
+ * This should be false until it has been demonstrated that gcc for the
+ * v850 generates FPU code when it is unexpected. But even this would
+ * not matter since there are no FP specific registers or bits which
+ * would be corrupted if an FP operation occurred in an integer only
+ * thread.
*/
#define CPU_ALL_TASKS_ARE_FP FALSE
/**
- * Should the IDLE task have a floating point context?
+ * Should the IDLE task have a floating point context?
*
- * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
- * and it has a floating point context which is switched in and out.
- * If FALSE, then the IDLE task does not have a floating point context.
+ * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
+ * and it has a floating point context which is switched in and out.
+ * If FALSE, then the IDLE task does not have a floating point context.
*
- * Setting this to TRUE negatively impacts the time required to preempt
- * the IDLE task from an interrupt because the floating point context
- * must be saved as part of the preemption.
+ * Setting this to TRUE negatively impacts the time required to preempt
+ * the IDLE task from an interrupt because the floating point context
+ * must be saved as part of the preemption.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * The IDLE thread should not be using the FPU. Leave this off.
+ * The IDLE thread should not be using the FPU. Leave this off.
*/
#define CPU_IDLE_TASK_IS_FP FALSE
/**
- * Should the saving of the floating point registers be deferred
- * until a context switch is made to another different floating point
- * task?
+ * Should the saving of the floating point registers be deferred
+ * until a context switch is made to another different floating point
+ * task?
*
- * If TRUE, then the floating point context will not be stored until
- * necessary. It will remain in the floating point registers and not
- * disturned until another floating point task is switched to.
+ * If TRUE, then the floating point context will not be stored until
+ * necessary. It will remain in the floating point registers and not
+ * disturned until another floating point task is switched to.
*
- * If FALSE, then the floating point context is saved when a floating
- * point task is switched out and restored when the next floating point
- * task is restored. The state of the floating point registers between
- * those two operations is not specified.
+ * If FALSE, then the floating point context is saved when a floating
+ * point task is switched out and restored when the next floating point
+ * task is restored. The state of the floating point registers between
+ * those two operations is not specified.
*
- * If the floating point context does NOT have to be saved as part of
- * interrupt dispatching, then it should be safe to set this to TRUE.
+ * If the floating point context does NOT have to be saved as part of
+ * interrupt dispatching, then it should be safe to set this to TRUE.
*
- * Setting this flag to TRUE results in using a different algorithm
- * for deciding when to save and restore the floating point context.
- * The deferred FP switch algorithm minimizes the number of times
- * the FP context is saved and restored. The FP context is not saved
- * until a context switch is made to another, different FP task.
- * Thus in a system with only one FP task, the FP context will never
- * be saved or restored.
+ * Setting this flag to TRUE results in using a different algorithm
+ * for deciding when to save and restore the floating point context.
+ * The deferred FP switch algorithm minimizes the number of times
+ * the FP context is saved and restored. The FP context is not saved
+ * until a context switch is made to another, different FP task.
+ * Thus in a system with only one FP task, the FP context will never
+ * be saved or restored.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * See earlier comments. There is no FPU state to manage.
+ * See earlier comments. There is no FPU state to manage.
*/
#define CPU_USE_DEFERRED_FP_SWITCH TRUE
/**
- * Does this port provide a CPU dependent IDLE task implementation?
+ * Does this port provide a CPU dependent IDLE task implementation?
*
- * If TRUE, then the routine @ref _CPU_Thread_Idle_body
- * must be provided and is the default IDLE thread body instead of
- * @ref _CPU_Thread_Idle_body.
+ * If TRUE, then the routine @ref _CPU_Thread_Idle_body
+ * must be provided and is the default IDLE thread body instead of
+ * @ref _CPU_Thread_Idle_body.
*
- * If FALSE, then use the generic IDLE thread body if the BSP does
- * not provide one.
+ * If FALSE, then use the generic IDLE thread body if the BSP does
+ * not provide one.
*
- * This is intended to allow for supporting processors which have
- * a low power or idle mode. When the IDLE thread is executed, then
- * the CPU can be powered down.
+ * This is intended to allow for supporting processors which have
+ * a low power or idle mode. When the IDLE thread is executed, then
+ * the CPU can be powered down.
*
- * The order of precedence for selecting the IDLE thread body is:
+ * The order of precedence for selecting the IDLE thread body is:
*
- * -# BSP provided
- * -# CPU dependent (if provided)
- * -# generic (if no BSP and no CPU dependent)
+ * -# BSP provided
+ * -# CPU dependent (if provided)
+ * -# generic (if no BSP and no CPU dependent)
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * There does not appear to be a reason for the v850 port itself to provide
- * a special idle task.
+ * There does not appear to be a reason for the v850 port itself to provide
+ * a special idle task.
*/
#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
/**
- * Does the stack grow up (toward higher addresses) or down
- * (toward lower addresses)?
+ * Does the stack grow up (toward higher addresses) or down
+ * (toward lower addresses)?
*
- * If TRUE, then the grows upward.
- * If FALSE, then the grows toward smaller addresses.
+ * If TRUE, then the grows upward.
+ * If FALSE, then the grows toward smaller addresses.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * The v850 stack grows from high addresses to low addresses.
+ * The v850 stack grows from high addresses to low addresses.
*/
#define CPU_STACK_GROWS_UP FALSE
/**
- * The following is the variable attribute used to force alignment
- * of critical RTEMS structures. On some processors it may make
- * sense to have these aligned on tighter boundaries than
- * the minimum requirements of the compiler in order to have as
- * much of the critical data area as possible in a cache line.
+ * The following is the variable attribute used to force alignment
+ * of critical RTEMS structures. On some processors it may make
+ * sense to have these aligned on tighter boundaries than
+ * the minimum requirements of the compiler in order to have as
+ * much of the critical data area as possible in a cache line.
*
- * The placement of this macro in the declaration of the variables
- * is based on the syntactically requirements of the GNU C
- * "__attribute__" extension. For example with GNU C, use
- * the following to force a structures to a 32 byte boundary.
+ * The placement of this macro in the declaration of the variables
+ * is based on the syntactically requirements of the GNU C
+ * "__attribute__" extension. For example with GNU C, use
+ * the following to force a structures to a 32 byte boundary.
*
- * __attribute__ ((aligned (32)))
+ * __attribute__ ((aligned (32)))
*
- * @note Currently only the Priority Bit Map table uses this feature.
- * To benefit from using this, the data must be heavily
- * used so it will stay in the cache and used frequently enough
- * in the executive to justify turning this on.
+ * @note Currently only the Priority Bit Map table uses this feature.
+ * To benefit from using this, the data must be heavily
+ * used so it will stay in the cache and used frequently enough
+ * in the executive to justify turning this on.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * Until proven otherwise, use the compiler default.
+ * Until proven otherwise, use the compiler default.
*/
#define CPU_STRUCTURE_ALIGNMENT
/**
- * The v850 should use 64-bit timestamps and inline them.
+ * The v850 should use 64-bit timestamps and inline them.
*/
#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
/**
- * @defgroup CPUEndian Processor Dependent Endianness Support
+ * @defgroup CPUEndian Processor Dependent Endianness Support
+ *
+ * This group assists in issues related to processor endianness.
*
- * This group assists in issues related to processor endianness.
+ * @{
*/
/**
- * @ingroup CPUEndian
- * Define what is required to specify how the network to host conversion
- * routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
*
- * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
- * same values.
+ * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
*
- * @see CPU_LITTLE_ENDIAN
+ * @see CPU_LITTLE_ENDIAN
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * The v850 is little endian.
+ * The v850 is little endian.
*/
#define CPU_BIG_ENDIAN FALSE
/**
- * @ingroup CPUEndian
- * Define what is required to specify how the network to host conversion
- * routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
*
- * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
- * same values.
+ * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
*
- * @see CPU_BIG_ENDIAN
+ * @see CPU_BIG_ENDIAN
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * The v850 is little endian.
+ * The v850 is little endian.
*/
#define CPU_LITTLE_ENDIAN TRUE
+/** @} */
+
/**
- * @ingroup CPUInterrupt
- * The following defines the number of bits actually used in the
- * interrupt field of the task mode. How those bits map to the
- * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
+ * @ingroup CPUInterrupt
+ * The following defines the number of bits actually used in the
+ * interrupt field of the task mode. How those bits map to the
+ * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * The v850 only has a single bit in the CPU for interrupt disable/enable.
+ * The v850 only has a single bit in the CPU for interrupt disable/enable.
*/
#define CPU_MODES_INTERRUPT_MASK 0x00000001
/**
* @defgroup CPUContext Processor Dependent Context Management
*
- * From the highest level viewpoint, there are 2 types of context to save.
+ * From the highest level viewpoint, there are 2 types of context to save.
*
- * -# Interrupt registers to save
- * -# Task level registers to save
+ * -# Interrupt registers to save
+ * -# Task level registers to save
*
- * Since RTEMS handles integer and floating point contexts separately, this
- * means we have the following 3 context items:
+ * Since RTEMS handles integer and floating point contexts separately, this
+ * means we have the following 3 context items:
*
- * -# task level context stuff:: Context_Control
- * -# floating point task stuff:: Context_Control_fp
- * -# special interrupt level context :: CPU_Interrupt_frame
+ * -# task level context stuff:: Context_Control
+ * -# floating point task stuff:: Context_Control_fp
+ * -# special interrupt level context :: CPU_Interrupt_frame
*
- * On some processors, it is cost-effective to save only the callee
- * preserved registers during a task context switch. This means
- * that the ISR code needs to save those registers which do not
- * persist across function calls. It is not mandatory to make this
- * distinctions between the caller/callee saves registers for the
- * purpose of minimizing context saved during task switch and on interrupts.
- * If the cost of saving extra registers is minimal, simplicity is the
- * choice. Save the same context on interrupt entry as for tasks in
- * this case.
+ * On some processors, it is cost-effective to save only the callee
+ * preserved registers during a task context switch. This means
+ * that the ISR code needs to save those registers which do not
+ * persist across function calls. It is not mandatory to make this
+ * distinctions between the caller/callee saves registers for the
+ * purpose of minimizing context saved during task switch and on interrupts.
+ * If the cost of saving extra registers is minimal, simplicity is the
+ * choice. Save the same context on interrupt entry as for tasks in
+ * this case.
*
- * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
- * care should be used in designing the context area.
+ * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
+ * care should be used in designing the context area.
*
- * On some CPUs with hardware floating point support, the Context_Control_fp
- * structure will not be used or it simply consist of an array of a
- * fixed number of bytes. This is done when the floating point context
- * is dumped by a "FP save context" type instruction and the format
- * is not really defined by the CPU. In this case, there is no need
- * to figure out the exact format -- only the size. Of course, although
- * this is enough information for RTEMS, it is probably not enough for
- * a debugger such as gdb. But that is another problem.
+ * On some CPUs with hardware floating point support, the Context_Control_fp
+ * structure will not be used or it simply consist of an array of a
+ * fixed number of bytes. This is done when the floating point context
+ * is dumped by a "FP save context" type instruction and the format
+ * is not really defined by the CPU. In this case, there is no need
+ * to figure out the exact format -- only the size. Of course, although
+ * this is enough information for RTEMS, it is probably not enough for
+ * a debugger such as gdb. But that is another problem.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * On the v850, this port saves special registers and those that are
- * callee saved.
+ * On the v850, this port saves special registers and those that are
+ * callee saved.
+ *
+ * @{
*/
/**
- * @ingroup CPUContext Management
- * This defines the minimal set of integer and processor state registers
- * that must be saved during a voluntary context switch from one thread
- * to another.
+ * This defines the minimal set of integer and processor state registers
+ * that must be saved during a voluntary context switch from one thread
+ * to another.
*/
typedef struct {
uint32_t r1;
@@ -461,21 +464,18 @@ typedef struct {
} Context_Control;
/**
- * @ingroup CPUContext Management
- *
- * This macro returns the stack pointer associated with @a _context.
+ * This macro returns the stack pointer associated with @a _context.
*
- * @param[in] _context is the thread context area to access
+ * @param[in] _context is the thread context area to access
*
- * @return This method returns the stack pointer.
+ * @return This method returns the stack pointer.
*/
#define _CPU_Context_Get_SP( _context ) \
(_context)->r3_stack_pointer
/**
- * @ingroup CPUContext Management
- * This defines the complete set of floating point registers that must
- * be saved during any context switch from one thread to another.
+ * This defines the complete set of floating point registers that must
+ * be saved during any context switch from one thread to another.
*/
typedef struct {
/** FPU registers are listed here */
@@ -483,62 +483,65 @@ typedef struct {
} Context_Control_fp;
/**
- * @ingroup CPUContext Management
- * This defines the set of integer and processor state registers that must
- * be saved during an interrupt. This set does not include any which are
- * in @ref Context_Control.
+ * This defines the set of integer and processor state registers that must
+ * be saved during an interrupt. This set does not include any which are
+ * in @ref Context_Control.
*/
typedef struct {
/** This field is a hint that a port will have a number of integer
- * registers that need to be saved when an interrupt occurs or
- * when a context switch occurs at the end of an ISR.
+ * registers that need to be saved when an interrupt occurs or
+ * when a context switch occurs at the end of an ISR.
*/
uint32_t special_interrupt_register;
} CPU_Interrupt_frame;
+/** @} */
+
/**
- * @defgroup CPUInterrupt Processor Dependent Interrupt Management
+ * @defgroup CPUInterrupt Processor Dependent Interrupt Management
+ *
+ * On some CPUs, RTEMS supports a software managed interrupt stack.
+ * This stack is allocated by the Interrupt Manager and the switch
+ * is performed in @ref _ISR_Handler. These variables contain pointers
+ * to the lowest and highest addresses in the chunk of memory allocated
+ * for the interrupt stack. Since it is unknown whether the stack
+ * grows up or down (in general), this give the CPU dependent
+ * code the option of picking the version it wants to use.
*
- * On some CPUs, RTEMS supports a software managed interrupt stack.
- * This stack is allocated by the Interrupt Manager and the switch
- * is performed in @ref _ISR_Handler. These variables contain pointers
- * to the lowest and highest addresses in the chunk of memory allocated
- * for the interrupt stack. Since it is unknown whether the stack
- * grows up or down (in general), this give the CPU dependent
- * code the option of picking the version it wants to use.
+ * @note These two variables are required if the macro
+ * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
*
- * @note These two variables are required if the macro
- * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
+ * Port Specific Information:
*
- * Port Specific Information:
+ * XXX document implementation including references if appropriate
*
- * XXX document implementation including references if appropriate
+ * @{
*/
/**
- * @ingroup CPUContext
- * The size of the floating point context area. On some CPUs this
- * will not be a "sizeof" because the format of the floating point
- * area is not defined -- only the size is. This is usually on
- * CPUs with a "floating point save context" instruction.
+ * @ingroup CPUContext
+ * The size of the floating point context area. On some CPUs this
+ * will not be a "sizeof" because the format of the floating point
+ * area is not defined -- only the size is. This is usually on
+ * CPUs with a "floating point save context" instruction.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * The v850 does not need a floating point context but this needs to be
- * defined so confdefs.h.
+ * The v850 does not need a floating point context but this needs to be
+ * defined so confdefs.h.
*/
/* #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) */
#define CPU_CONTEXT_FP_SIZE 0
/**
- * Amount of extra stack (above minimum stack size) required by
- * MPCI receive server thread. Remember that in a multiprocessor
- * system this thread must exist and be able to process all directives.
+ * Amount of extra stack (above minimum stack size) required by
+ * MPCI receive server thread. Remember that in a multiprocessor
+ * system this thread must exist and be able to process all directives.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * There is no reason to think the v850 needs extra MPCI receive
- * server stack.
+ * There is no reason to think the v850 needs extra MPCI receive
+ * server stack.
*/
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
@@ -546,109 +549,108 @@ typedef struct {
/* XXX evaluate removing it */
#if 0
/**
- * @ingroup CPUInterrupt
- * This defines the number of entries in the @ref _ISR_Vector_table managed
- * by RTEMS.
+ * This defines the number of entries in the @ref _ISR_Vector_table managed
+ * by RTEMS.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
#endif
/**
- * @ingroup CPUInterrupt
- * This defines the highest interrupt vector number for this port.
+ * This defines the highest interrupt vector number for this port.
*/
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
/**
- * @ingroup CPUInterrupt
- * This is defined if the port has a special way to report the ISR nesting
- * level. Most ports maintain the variable @a _ISR_Nest_level.
+ * This is defined if the port has a special way to report the ISR nesting
+ * level. Most ports maintain the variable @a _ISR_Nest_level.
*/
#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
+/** @} */
+
/**
- * @ingroup CPUContext
- * Should be large enough to run all RTEMS tests. This ensures
- * that a "reasonable" small application should not have any problems.
+ * @ingroup CPUContext
+ * Should be large enough to run all RTEMS tests. This ensures
+ * that a "reasonable" small application should not have any problems.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * This should be very conservative on the v850.
+ * This should be very conservative on the v850.
*/
#define CPU_STACK_MINIMUM_SIZE (1024*4)
#define CPU_SIZEOF_POINTER 4
/**
- * CPU's worst alignment requirement for data types on a byte boundary. This
- * alignment does not take into account the requirements for the stack.
+ * CPU's worst alignment requirement for data types on a byte boundary. This
+ * alignment does not take into account the requirements for the stack.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * There is no apparent reason why this should be larger than 8.
+ * There is no apparent reason why this should be larger than 8.
*/
#define CPU_ALIGNMENT 8
/**
- * This number corresponds to the byte alignment requirement for the
- * heap handler. This alignment requirement may be stricter than that
- * for the data types alignment specified by @ref CPU_ALIGNMENT. It is
- * common for the heap to follow the same alignment requirement as
- * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for
- * the heap, then this should be set to @ref CPU_ALIGNMENT.
- *
- * @note This does not have to be a power of 2 although it should be
- * a multiple of 2 greater than or equal to 2. The requirement
- * to be a multiple of 2 is because the heap uses the least
- * significant field of the front and back flags to indicate
- * that a block is in use or free. So you do not want any odd
- * length blocks really putting length data in that bit.
- *
- * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
- * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
- * elements allocated from the heap meet all restrictions.
- *
- * Port Specific Information:
- *
- * There is no apparent reason why this should be larger than CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for the
+ * heap handler. This alignment requirement may be stricter than that
+ * for the data types alignment specified by @ref CPU_ALIGNMENT. It is
+ * common for the heap to follow the same alignment requirement as
+ * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for
+ * the heap, then this should be set to @ref CPU_ALIGNMENT.
+ *
+ * @note This does not have to be a power of 2 although it should be
+ * a multiple of 2 greater than or equal to 2. The requirement
+ * to be a multiple of 2 is because the heap uses the least
+ * significant field of the front and back flags to indicate
+ * that a block is in use or free. So you do not want any odd
+ * length blocks really putting length data in that bit.
+ *
+ * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
+ * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
+ * elements allocated from the heap meet all restrictions.
+ *
+ * Port Specific Information:
+ *
+ * There is no apparent reason why this should be larger than CPU_ALIGNMENT.
*/
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
/**
- * This number corresponds to the byte alignment requirement for memory
- * buffers allocated by the partition manager. This alignment requirement
- * may be stricter than that for the data types alignment specified by
- * @ref CPU_ALIGNMENT. It is common for the partition to follow the same
- * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is
- * strict enough for the partition, then this should be set to
- * @ref CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for memory
+ * buffers allocated by the partition manager. This alignment requirement
+ * may be stricter than that for the data types alignment specified by
+ * @ref CPU_ALIGNMENT. It is common for the partition to follow the same
+ * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is
+ * strict enough for the partition, then this should be set to
+ * @ref CPU_ALIGNMENT.
*
- * @note This does not have to be a power of 2. It does have to
- * be greater or equal to than @ref CPU_ALIGNMENT.
+ * @note This does not have to be a power of 2. It does have to
+ * be greater or equal to than @ref CPU_ALIGNMENT.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * There is no apparent reason why this should be larger than CPU_ALIGNMENT.
+ * There is no apparent reason why this should be larger than CPU_ALIGNMENT.
*/
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
/**
- * This number corresponds to the byte alignment requirement for the
- * stack. This alignment requirement may be stricter than that for the
- * data types alignment specified by @ref CPU_ALIGNMENT. If the
- * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
- * set to 0.
+ * This number corresponds to the byte alignment requirement for the
+ * stack. This alignment requirement may be stricter than that for the
+ * data types alignment specified by @ref CPU_ALIGNMENT. If the
+ * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
+ * set to 0.
*
- * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
+ * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * The v850 has enough RAM where alignment to 16 may be desirable depending
- * on the cache properties. But this remains to be demonstrated.
+ * The v850 has enough RAM where alignment to 16 may be desirable depending
+ * on the cache properties. But this remains to be demonstrated.
*/
#define CPU_STACK_ALIGNMENT 4
@@ -657,15 +659,20 @@ typedef struct {
*/
/**
- * @ingroup CPUInterrupt
- * Disable all interrupts for an RTEMS critical section. The previous
- * level is returned in @a _isr_cookie.
+ * @addtogroup CPUInterrupt
*
- * @param[out] _isr_cookie will contain the previous level cookie
+ * @{
+ */
+
+/**
+ * Disable all interrupts for an RTEMS critical section. The previous
+ * level is returned in @a _isr_cookie.
+ *
+ * @param[out] _isr_cookie will contain the previous level cookie
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * On the v850, we need to save the PSW and use "di" to disable interrupts.
+ * On the v850, we need to save the PSW and use "di" to disable interrupts.
*/
#define _CPU_ISR_Disable( _isr_cookie ) \
do { \
@@ -677,16 +684,15 @@ typedef struct {
} while (0)
/**
- * @ingroup CPUInterrupt
- * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- * This indicates the end of an RTEMS critical section. The parameter
- * @a _isr_cookie is not modified.
+ * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
+ * This indicates the end of an RTEMS critical section. The parameter
+ * @a _isr_cookie is not modified.
*
- * @param[in] _isr_cookie contain the previous level cookie
+ * @param[in] _isr_cookie contain the previous level cookie
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * On the v850, we simply need to restore the PSW.
+ * On the v850, we simply need to restore the PSW.
*/
#define _CPU_ISR_Enable( _isr_cookie ) \
do { \
@@ -696,17 +702,16 @@ typedef struct {
} while (0)
/**
- * @ingroup CPUInterrupt
- * This temporarily restores the interrupt to @a _isr_cookie before immediately
- * disabling them again. This is used to divide long RTEMS critical
- * sections into two or more parts. The parameter @a _isr_cookie is not
- * modified.
+ * This temporarily restores the interrupt to @a _isr_cookie before immediately
+ * disabling them again. This is used to divide long RTEMS critical
+ * sections into two or more parts. The parameter @a _isr_cookie is not
+ * modified.
*
- * @param[in] _isr_cookie contain the previous level cookie
+ * @param[in] _isr_cookie contain the previous level cookie
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * This saves at least one instruction over using enable/disable back to back.
+ * This saves at least one instruction over using enable/disable back to back.
*/
#define _CPU_ISR_Flash( _isr_cookie ) \
do { \
@@ -716,21 +721,19 @@ typedef struct {
} while (0)
/**
- * @ingroup CPUInterrupt
- *
- * This routine and @ref _CPU_ISR_Get_level
- * Map the interrupt level in task mode onto the hardware that the CPU
- * actually provides. Currently, interrupt levels which do not
- * map onto the CPU in a generic fashion are undefined. Someday,
- * it would be nice if these were "mapped" by the application
- * via a callout. For example, m68k has 8 levels 0 - 7, levels
- * 8 - 255 would be available for bsp/application specific meaning.
- * This could be used to manage a programmable interrupt controller
- * via the rtems_task_mode directive.
- *
- * Port Specific Information:
- *
- * On the v850, level 0 is enabled. Non-zero is disabled.
+ * This routine and @ref _CPU_ISR_Get_level
+ * Map the interrupt level in task mode onto the hardware that the CPU
+ * actually provides. Currently, interrupt levels which do not
+ * map onto the CPU in a generic fashion are undefined. Someday,
+ * it would be nice if these were "mapped" by the application
+ * via a callout. For example, m68k has 8 levels 0 - 7, levels
+ * 8 - 255 would be available for bsp/application specific meaning.
+ * This could be used to manage a programmable interrupt controller
+ * via the rtems_task_mode directive.
+ *
+ * Port Specific Information:
+ *
+ * On the v850, level 0 is enabled. Non-zero is disabled.
*/
#define _CPU_ISR_Set_level( new_level ) \
do { \
@@ -741,52 +744,53 @@ typedef struct {
} while (0)
/**
- * @ingroup CPUInterrupt
- * Return the current interrupt disable level for this task in
- * the format used by the interrupt level portion of the task mode.
+ * Return the current interrupt disable level for this task in
+ * the format used by the interrupt level portion of the task mode.
*
- * @note This routine usually must be implemented as a subroutine.
+ * @note This routine usually must be implemented as a subroutine.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * This method is implemented in C on the v850.
+ * This method is implemented in C on the v850.
*/
uint32_t _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
+/** @} */
+
/* Context handler macros */
/**
- * @ingroup CPUContext
- * Initialize the context to a state suitable for starting a
- * task after a context restore operation. Generally, this
- * involves:
- *
- * - setting a starting address
- * - preparing the stack
- * - preparing the stack and frame pointers
- * - setting the proper interrupt level in the context
- * - initializing the floating point context
- *
- * This routine generally does not set any unnecessary register
- * in the context. The state of the "general data" registers is
- * undefined at task start time.
- *
- * @param[in] _the_context is the context structure to be initialized
- * @param[in] _stack_base is the lowest physical address of this task's stack
- * @param[in] _size is the size of this task's stack
- * @param[in] _isr is the interrupt disable level
- * @param[in] _entry_point is the thread's entry point. This is
- * always @a _Thread_Handler
- * @param[in] _is_fp is TRUE if the thread is to be a floating
- * point thread. This is typically only used on CPUs where the
- * FPU may be easily disabled by software such as on the SPARC
- * where the PSR contains an enable FPU bit.
- *
- * Port Specific Information:
- *
- * This method is implemented in C on the v850.
+ * @ingroup CPUContext
+ * Initialize the context to a state suitable for starting a
+ * task after a context restore operation. Generally, this
+ * involves:
+ *
+ * - setting a starting address
+ * - preparing the stack
+ * - preparing the stack and frame pointers
+ * - setting the proper interrupt level in the context
+ * - initializing the floating point context
+ *
+ * This routine generally does not set any unnecessary register
+ * in the context. The state of the "general data" registers is
+ * undefined at task start time.
+ *
+ * @param[in] _the_context is the context structure to be initialized
+ * @param[in] _stack_base is the lowest physical address of this task's stack
+ * @param[in] _size is the size of this task's stack
+ * @param[in] _isr is the interrupt disable level
+ * @param[in] _entry_point is the thread's entry point. This is
+ * always @a _Thread_Handler
+ * @param[in] _is_fp is TRUE if the thread is to be a floating
+ * point thread. This is typically only used on CPUs where the
+ * FPU may be easily disabled by software such as on the SPARC
+ * where the PSR contains an enable FPU bit.
+ *
+ * Port Specific Information:
+ *
+ * This method is implemented in C on the v850.
*/
void _CPU_Context_Initialize(
Context_Control *the_context,
@@ -798,19 +802,19 @@ void _CPU_Context_Initialize(
);
/**
- * This routine is responsible for somehow restarting the currently
- * executing task. If you are lucky, then all that is necessary
- * is restoring the context. Otherwise, there will need to be
- * a special assembly routine which does something special in this
- * case. For many ports, simply adding a label to the restore path
- * of @ref _CPU_Context_switch will work. On other ports, it may be
- * possibly to load a few arguments and jump to the restore path. It will
- * not work if restarting self conflicts with the stack frame
- * assumptions of restoring a context.
- *
- * Port Specific Information:
- *
- * On the v850, we require a special entry point to restart a task.
+ * This routine is responsible for somehow restarting the currently
+ * executing task. If you are lucky, then all that is necessary
+ * is restoring the context. Otherwise, there will need to be
+ * a special assembly routine which does something special in this
+ * case. For many ports, simply adding a label to the restore path
+ * of @ref _CPU_Context_switch will work. On other ports, it may be
+ * possibly to load a few arguments and jump to the restore path. It will
+ * not work if restarting self conflicts with the stack frame
+ * assumptions of restoring a context.
+ *
+ * Port Specific Information:
+ *
+ * On the v850, we require a special entry point to restart a task.
*/
#define _CPU_Context_Restart_self( _the_context ) \
_CPU_Context_restore( (_the_context) );
@@ -818,26 +822,26 @@ void _CPU_Context_Initialize(
/* XXX this should be possible to remove */
#if 0
/**
- * @ingroup CPUContext
- * The purpose of this macro is to allow the initial pointer into
- * a floating point context area (used to save the floating point
- * context) to be at an arbitrary place in the floating point
- * context area.
- *
- * This is necessary because some FP units are designed to have
- * their context saved as a stack which grows into lower addresses.
- * Other FP units can be saved by simply moving registers into offsets
- * from the base of the context area. Finally some FP units provide
- * a "dump context" instruction which could fill in from high to low
- * or low to high based on the whim of the CPU designers.
- *
- * @param[in] _base is the lowest physical address of the floating point
- * context area
- * @param[in] _offset is the offset into the floating point area
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
+ * @ingroup CPUContext
+ * The purpose of this macro is to allow the initial pointer into
+ * a floating point context area (used to save the floating point
+ * context) to be at an arbitrary place in the floating point
+ * context area.
+ *
+ * This is necessary because some FP units are designed to have
+ * their context saved as a stack which grows into lower addresses.
+ * Other FP units can be saved by simply moving registers into offsets
+ * from the base of the context area. Finally some FP units provide
+ * a "dump context" instruction which could fill in from high to low
+ * or low to high based on the whim of the CPU designers.
+ *
+ * @param[in] _base is the lowest physical address of the floating point
+ * context area
+ * @param[in] _offset is the offset into the floating point area
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
*/
#define _CPU_Context_Fp_start( _base, _offset ) \
( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
@@ -846,22 +850,22 @@ void _CPU_Context_Initialize(
/* XXX this should be possible to remove */
#if 0
/**
- * This routine initializes the FP context area passed to it to.
- * There are a few standard ways in which to initialize the
- * floating point context. The code included for this macro assumes
- * that this is a CPU in which a "initial" FP context was saved into
- * @a _CPU_Null_fp_context and it simply copies it to the destination
- * context passed to it.
+ * This routine initializes the FP context area passed to it to.
+ * There are a few standard ways in which to initialize the
+ * floating point context. The code included for this macro assumes
+ * that this is a CPU in which a "initial" FP context was saved into
+ * @a _CPU_Null_fp_context and it simply copies it to the destination
+ * context passed to it.
*
- * Other floating point context save/restore models include:
- * -# not doing anything, and
- * -# putting a "null FP status word" in the correct place in the FP context.
+ * Other floating point context save/restore models include:
+ * -# not doing anything, and
+ * -# putting a "null FP status word" in the correct place in the FP context.
*
- * @param[in] _destination is the floating point context area
+ * @param[in] _destination is the floating point context area
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
#define _CPU_Context_Initialize_fp( _destination ) \
{ \
@@ -873,13 +877,13 @@ void _CPU_Context_Initialize(
/* Fatal Error manager macros */
/**
- * This routine copies _error into a known place -- typically a stack
- * location or a register, optionally disables interrupts, and
- * halts/stops the CPU.
+ * This routine copies _error into a known place -- typically a stack
+ * location or a register, optionally disables interrupts, and
+ * halts/stops the CPU.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * Move the error code into r10, disable interrupts and halt.
+ * Move the error code into r10, disable interrupts and halt.
*/
#define _CPU_Fatal_halt( _error ) \
do { \
@@ -893,75 +897,74 @@ void _CPU_Context_Initialize(
/* Bitfield handler macros */
/**
- * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
+ * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
+ *
+ * This set of routines are used to implement fast searches for
+ * the most important ready task.
*
- * This set of routines are used to implement fast searches for
- * the most important ready task.
+ * @{
*/
/**
- * @ingroup CPUBitfield
- * This definition is set to TRUE if the port uses the generic bitfield
- * manipulation implementation.
+ * This definition is set to TRUE if the port uses the generic bitfield
+ * manipulation implementation.
*/
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
/**
- * @ingroup CPUBitfield
- * This definition is set to TRUE if the port uses the data tables provided
- * by the generic bitfield manipulation implementation.
- * This can occur when actually using the generic bitfield manipulation
- * implementation or when implementing the same algorithm in assembly
- * language for improved performance. It is unlikely that a port will use
- * the data if it has a bitfield scan instruction.
- *
- * Port Specific Information:
- *
- * There is no single v850 instruction to do a bit scan so there is
- * no CPU specific implementation of bit field scanning. The empty
- * stub routines are left as a place holder in case someone figures
- * out how to do a v850 implementation better than the generic algorithm.
+ * This definition is set to TRUE if the port uses the data tables provided
+ * by the generic bitfield manipulation implementation.
+ * This can occur when actually using the generic bitfield manipulation
+ * implementation or when implementing the same algorithm in assembly
+ * language for improved performance. It is unlikely that a port will use
+ * the data if it has a bitfield scan instruction.
+ *
+ * Port Specific Information:
+ *
+ * There is no single v850 instruction to do a bit scan so there is
+ * no CPU specific implementation of bit field scanning. The empty
+ * stub routines are left as a place holder in case someone figures
+ * out how to do a v850 implementation better than the generic algorithm.
*/
#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
/**
- * @ingroup CPUBitfield
- * This routine sets @a _output to the bit number of the first bit
- * set in @a _value. @a _value is of CPU dependent type
- * @a Priority_bit_map_Control. This type may be either 16 or 32 bits
- * wide although only the 16 least significant bits will be used.
- *
- * There are a number of variables in using a "find first bit" type
- * instruction.
- *
- * -# What happens when run on a value of zero?
- * -# Bits may be numbered from MSB to LSB or vice-versa.
- * -# The numbering may be zero or one based.
- * -# The "find first bit" instruction may search from MSB or LSB.
- *
- * RTEMS guarantees that (1) will never happen so it is not a concern.
- * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
- * @ref _CPU_Priority_bits_index. These three form a set of routines
- * which must logically operate together. Bits in the _value are
- * set and cleared based on masks built by @ref _CPU_Priority_Mask.
- * The basic major and minor values calculated by @ref _Priority_Major
- * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
- * to properly range between the values returned by the "find first bit"
- * instruction. This makes it possible for @ref _Priority_Get_highest to
- * calculate the major and directly index into the minor table.
- * This mapping is necessary to ensure that 0 (a high priority major/minor)
- * is the first bit found.
- *
- * This entire "find first bit" and mapping process depends heavily
- * on the manner in which a priority is broken into a major and minor
- * components with the major being the 4 MSB of a priority and minor
- * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
- * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
- * to the lowest priority.
- *
- * If your CPU does not have a "find first bit" instruction, then
- * there are ways to make do without it. Here are a handful of ways
- * to implement this in software:
+ * This routine sets @a _output to the bit number of the first bit
+ * set in @a _value. @a _value is of CPU dependent type
+ * @a Priority_bit_map_Control. This type may be either 16 or 32 bits
+ * wide although only the 16 least significant bits will be used.
+ *
+ * There are a number of variables in using a "find first bit" type
+ * instruction.
+ *
+ * -# What happens when run on a value of zero?
+ * -# Bits may be numbered from MSB to LSB or vice-versa.
+ * -# The numbering may be zero or one based.
+ * -# The "find first bit" instruction may search from MSB or LSB.
+ *
+ * RTEMS guarantees that (1) will never happen so it is not a concern.
+ * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
+ * @ref _CPU_Priority_bits_index. These three form a set of routines
+ * which must logically operate together. Bits in the _value are
+ * set and cleared based on masks built by @ref _CPU_Priority_Mask.
+ * The basic major and minor values calculated by @ref _Priority_Major
+ * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
+ * to properly range between the values returned by the "find first bit"
+ * instruction. This makes it possible for @ref _Priority_Get_highest to
+ * calculate the major and directly index into the minor table.
+ * This mapping is necessary to ensure that 0 (a high priority major/minor)
+ * is the first bit found.
+ *
+ * This entire "find first bit" and mapping process depends heavily
+ * on the manner in which a priority is broken into a major and minor
+ * components with the major being the 4 MSB of a priority and minor
+ * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
+ * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
+ * to the lowest priority.
+ *
+ * If your CPU does not have a "find first bit" instruction, then
+ * there are ways to make do without it. Here are a handful of ways
+ * to implement this in software:
*
@verbatim
- a series of 16 bit test instructions
@@ -978,16 +981,16 @@ void _CPU_Context_Initialize(
_number += bit_set_table[ _value ]
@endverbatim
- * where bit_set_table[ 16 ] has values which indicate the first
- * bit set
+ * where bit_set_table[ 16 ] has values which indicate the first
+ * bit set
*
- * @param[in] _value is the value to be scanned
- * @param[in] _output is the first bit set
+ * @param[in] _value is the value to be scanned
+ * @param[in] _output is the first bit set
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * There is no single v850 instruction to do a bit scan so there is
- * no CPU specific implementation of bit field scanning.
+ * There is no single v850 instruction to do a bit scan so there is
+ * no CPU specific implementation of bit field scanning.
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
@@ -999,14 +1002,14 @@ void _CPU_Context_Initialize(
/* end of Bitfield handler macros */
/**
- * This routine builds the mask which corresponds to the bit fields
- * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion
- * for that routine.
+ * This routine builds the mask which corresponds to the bit fields
+ * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion
+ * for that routine.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * There is no single v850 instruction to do a bit scan so there is
- * no CPU specific implementation of bit field scanning.
+ * There is no single v850 instruction to do a bit scan so there is
+ * no CPU specific implementation of bit field scanning.
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
@@ -1016,18 +1019,17 @@ void _CPU_Context_Initialize(
#endif
/**
- * @ingroup CPUBitfield
- * This routine translates the bit numbers returned by
- * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
- * a major or minor component of a priority. See the discussion
- * for that routine.
+ * This routine translates the bit numbers returned by
+ * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
+ * a major or minor component of a priority. See the discussion
+ * for that routine.
*
- * @param[in] _priority is the major or minor number to translate
+ * @param[in] _priority is the major or minor number to translate
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * There is no single v850 instruction to do a bit scan so there is
- * no CPU specific implementation of bit field scanning.
+ * There is no single v850 instruction to do a bit scan so there is
+ * no CPU specific implementation of bit field scanning.
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
@@ -1038,30 +1040,37 @@ void _CPU_Context_Initialize(
/* end of Priority handler macros */
+/** @} */
+
/* functions */
/**
- * @brief CPU Initialize
- * This routine performs CPU dependent initialization.
+ * @brief CPU initialize.
+ * This routine performs CPU dependent initialization.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * This is implemented in C.
+ * This is implemented in C.
*
- * v850 CPU Dependent Source
+ * v850 CPU Dependent Source
*/
void _CPU_Initialize(void);
/**
- * @ingroup CPUContext
- * This routine switches from the run context to the heir context.
+ * @addtogroup CPUContext
+ *
+ * @{
+ */
+
+/**
+ * This routine switches from the run context to the heir context.
*
- * @param[in] run points to the context of the currently executing task
- * @param[in] heir points to the context of the heir task
+ * @param[in] run points to the context of the currently executing task
+ * @param[in] heir points to the context of the heir task
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * This is implemented in assembly on the v850.
+ * This is implemented in assembly on the v850.
*/
void _CPU_Context_switch(
Context_Control *run,
@@ -1069,17 +1078,16 @@ void _CPU_Context_switch(
);
/**
- * @ingroup CPUContext
- * This routine is generally used only to restart self in an
- * efficient manner. It may simply be a label in @ref _CPU_Context_switch.
+ * This routine is generally used only to restart self in an
+ * efficient manner. It may simply be a label in @ref _CPU_Context_switch.
*
- * @param[in] new_context points to the context to be restored.
+ * @param[in] new_context points to the context to be restored.
*
- * @note May be unnecessary to reload some registers.
+ * @note May be unnecessary to reload some registers.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * This is implemented in assembly on the v850.
+ * This is implemented in assembly on the v850.
*/
void _CPU_Context_restore(
Context_Control *new_context
@@ -1088,18 +1096,17 @@ void _CPU_Context_restore(
/* XXX this should be possible to remove */
#if 0
/**
- * @ingroup CPUContext
- * This routine saves the floating point context passed to it.
+ * This routine saves the floating point context passed to it.
*
- * @param[in] fp_context_ptr is a pointer to a pointer to a floating
- * point context area
+ * @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ * point context area
*
- * @return on output @a *fp_context_ptr will contain the address that
- * should be used with @ref _CPU_Context_restore_fp to restore this context.
+ * @return on output @a *fp_context_ptr will contain the address that
+ * should be used with @ref _CPU_Context_restore_fp to restore this context.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
void _CPU_Context_save_fp(
Context_Control_fp **fp_context_ptr
@@ -1109,56 +1116,57 @@ void _CPU_Context_save_fp(
/* XXX this should be possible to remove */
#if 0
/**
- * @ingroup CPUContext
- * This routine restores the floating point context passed to it.
+ * This routine restores the floating point context passed to it.
*
- * @param[in] fp_context_ptr is a pointer to a pointer to a floating
- * point context area to restore
+ * @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ * point context area to restore
*
- * @return on output @a *fp_context_ptr will contain the address that
- * should be used with @ref _CPU_Context_save_fp to save this context.
+ * @return on output @a *fp_context_ptr will contain the address that
+ * should be used with @ref _CPU_Context_save_fp to save this context.
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
*/
void _CPU_Context_restore_fp(
Context_Control_fp **fp_context_ptr
);
#endif
+/** @} */
+
/* FIXME */
typedef CPU_Interrupt_frame CPU_Exception_frame;
void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
/**
- * @ingroup CPUEndian
- * The following routine swaps the endian format of an unsigned int.
- * It must be static because it is referenced indirectly.
+ * @ingroup CPUEndian
+ * The following routine swaps the endian format of an unsigned int.
+ * It must be static because it is referenced indirectly.
*
- * This version will work on any processor, but if there is a better
- * way for your CPU PLEASE use it. The most common way to do this is to:
+ * This version will work on any processor, but if there is a better
+ * way for your CPU PLEASE use it. The most common way to do this is to:
*
- * swap least significant two bytes with 16-bit rotate
- * swap upper and lower 16-bits
- * swap most significant two bytes with 16-bit rotate
+ * swap least significant two bytes with 16-bit rotate
+ * swap upper and lower 16-bits
+ * swap most significant two bytes with 16-bit rotate
*
- * Some CPUs have special instructions which swap a 32-bit quantity in
- * a single instruction (e.g. i486). It is probably best to avoid
- * an "endian swapping control bit" in the CPU. One good reason is
- * that interrupts would probably have to be disabled to ensure that
- * an interrupt does not try to access the same "chunk" with the wrong
- * endian. Another good reason is that on some CPUs, the endian bit
- * endianness for ALL fetches -- both code and data -- so the code
- * will be fetched incorrectly.
+ * Some CPUs have special instructions which swap a 32-bit quantity in
+ * a single instruction (e.g. i486). It is probably best to avoid
+ * an "endian swapping control bit" in the CPU. One good reason is
+ * that interrupts would probably have to be disabled to ensure that
+ * an interrupt does not try to access the same "chunk" with the wrong
+ * endian. Another good reason is that on some CPUs, the endian bit
+ * endianness for ALL fetches -- both code and data -- so the code
+ * will be fetched incorrectly.
*
- * @param[in] value is the value to be swapped
- * @return the value after being endian swapped
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * The v850 has a single instruction to swap endianness on a 32 bit quantity.
+ * The v850 has a single instruction to swap endianness on a 32 bit quantity.
*/
static inline uint32_t CPU_swap_u32(
uint32_t value
@@ -1185,15 +1193,15 @@ static inline uint32_t CPU_swap_u32(
}
/**
- * @ingroup CPUEndian
- * This routine swaps a 16 bir quantity.
+ * @ingroup CPUEndian
+ * This routine swaps a 16 bir quantity.
*
- * @param[in] value is the value to be swapped
- * @return the value after being endian swapped
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
*
- * Port Specific Information:
+ * Port Specific Information:
*
- * The v850 has a single instruction to swap endianness on a 16 bit quantity.
+ * The v850 has a single instruction to swap endianness on a 16 bit quantity.
*/
static inline uint16_t CPU_swap_u16( uint16_t value )
{
diff --git a/cpukit/score/cpu/v850/rtems/score/types.h b/cpukit/score/cpu/v850/rtems/score/types.h
index 32ff881898..e831b2dc13 100644
--- a/cpukit/score/cpu/v850/rtems/score/types.h
+++ b/cpukit/score/cpu/v850/rtems/score/types.h
@@ -1,11 +1,13 @@
/**
- * @file rtems/score/types.h
+ * @file
+ *
+ * @brief V850 CPU Type Definitions
+ *
+ * This include file contains type definitions pertaining to the
+ * v850 processor family.
*/
/*
- * This include file contains type definitions pertaining to the
- * v850 processor family.
- *
* COPYRIGHT (c) 1989-2011.
* On-Line Applications Research Corporation (OAR).
*
diff --git a/cpukit/score/cpu/v850/rtems/score/v850.h b/cpukit/score/cpu/v850/rtems/score/v850.h
index 3e9bec56f3..df35925c7b 100644
--- a/cpukit/score/cpu/v850/rtems/score/v850.h
+++ b/cpukit/score/cpu/v850/rtems/score/v850.h
@@ -1,8 +1,12 @@
-/*
- * This file sets up basic CPU dependency settings based on
- * compiler settings. For example, it can determine if
- * floating point is available. This particular implementation
- * is specified to the Renesas v850 port.
+/**
+ * @file
+ *
+ * @brief V850 Set up Basic CPU Dependency Settings Based on Compiler Settings
+ *
+ * This file sets up basic CPU dependency settings based on
+ * compiler settings. For example, it can determine if
+ * floating point is available. This particular implementation
+ * is specified to the Renesas v850 port.
*/
/*