diff options
Diffstat (limited to 'cpukit/score')
| -rw-r--r-- | cpukit/score/cpu/bfin/irq.c | 4 | ||||
| -rw-r--r-- | cpukit/score/cpu/bfin/rtems/score/bfin.h | 14 | ||||
| -rw-r--r-- | cpukit/score/cpu/bfin/rtems/score/cpu.h | 46 | ||||
| -rw-r--r-- | cpukit/score/cpu/bfin/rtems/score/cpu_asm.h | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/c4x/cpu_asm.S | 20 | ||||
| -rw-r--r-- | cpukit/score/cpu/i386/cpu.c | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/i386/rtems/score/cpu.h | 6 | ||||
| -rw-r--r-- | cpukit/score/cpu/i386/sse_test.c | 26 | ||||
| -rw-r--r-- | cpukit/score/cpu/lm32/cpu.c | 4 | ||||
| -rw-r--r-- | cpukit/score/cpu/lm32/cpu_asm.S | 22 | ||||
| -rw-r--r-- | cpukit/score/cpu/lm32/rtems/score/cpu.h | 32 | ||||
| -rw-r--r-- | cpukit/score/cpu/lm32/rtems/score/lm32.h | 16 |
12 files changed, 97 insertions, 97 deletions
diff --git a/cpukit/score/cpu/bfin/irq.c b/cpukit/score/cpu/bfin/irq.c index d43f39ffa0..eccb03d3d5 100644 --- a/cpukit/score/cpu/bfin/irq.c +++ b/cpukit/score/cpu/bfin/irq.c @@ -10,10 +10,10 @@ * * $Id$ */ - + #if 0 /* this file no longer used */ - + #include <rtems/system.h> #include <rtems/score/cpu.h> #include <rtems/score/isr.h> diff --git a/cpukit/score/cpu/bfin/rtems/score/bfin.h b/cpukit/score/cpu/bfin/rtems/score/bfin.h index 252e5a6cf5..7568205ae7 100644 --- a/cpukit/score/cpu/bfin/rtems/score/bfin.h +++ b/cpukit/score/cpu/bfin/rtems/score/bfin.h @@ -1,6 +1,6 @@ /* bfin.h * - * This file sets up basic CPU dependency settings based on + * This file sets up basic CPU dependency settings based on * compiler settings. For example, it can determine if * floating point is available. This particular implementation * is specified to the Blackfin port. @@ -38,24 +38,24 @@ extern "C" { * that this port supports and which RTEMS CPU model they correspond * to. */ - + /* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. + * Figure out all CPU Model Feature Flags based upon compiler + * predefines. */ #if defined(__BFIN__) #define CPU_MODEL_NAME "BF533" #define BF_HAS_FPU 0 #else - + #error "Unsupported CPU Model" - + #endif /* * Define the name of the CPU family. */ - + #define CPU_NAME "BFIN" #ifdef __cplusplus diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h b/cpukit/score/cpu/bfin/rtems/score/cpu.h index 3f9df06b16..8cb689db3e 100644 --- a/cpukit/score/cpu/bfin/rtems/score/cpu.h +++ b/cpukit/score/cpu/bfin/rtems/score/cpu.h @@ -5,7 +5,7 @@ /* * This include file contains information pertaining to the Blackfin * processor. - * + * * COPYRIGHT (c) 1989-2006. * On-Line Applications Research Corporation (OAR). * adapted to Blackfin by Alain Schaefer <alain.schaefer@easc.ch> @@ -169,7 +169,7 @@ extern "C" { /** * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector + * a pointer to the saved interrupt frame (1) or just the vector * number (0)? * * Port Specific Information: @@ -196,7 +196,7 @@ extern "C" { * an i387 and wish to leave floating point support out of RTEMS. */ -/** +/** * @def CPU_SOFTWARE_FP * * Does the CPU have no hardware floating point and GCC provides a @@ -204,7 +204,7 @@ extern "C" { * switched? * * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context + * is software implemented floating point that must be context * switched. The determination of whether or not this applies * is very tool specific and the state saved/restored is also * compiler specific. @@ -356,7 +356,7 @@ extern "C" { * * XXX document implementation including references if appropriate */ -#define CPU_STRUCTURE_ALIGNMENT +#define CPU_STRUCTURE_ALIGNMENT /** * @defgroup CPUEndian Processor Dependent Endianness Support @@ -477,18 +477,18 @@ typedef struct { uint32_t register_p3; uint32_t register_p4; - uint32_t register_p5; + uint32_t register_p5; uint32_t register_fp; uint32_t register_sp; - + uint32_t register_l0; uint32_t register_l1; uint32_t register_l2; - uint32_t register_l3; - + uint32_t register_l3; + uint32_t register_rets; - uint32_t imask; + uint32_t imask; } Context_Control; #define _CPU_Context_Get_SP( _context ) \ @@ -511,7 +511,7 @@ typedef struct { * in @ref Context_Control. */ typedef struct { - /** This field is a hint that a port will have a number of integer + /** This field is a hint that a port will have a number of integer * registers that need to be saved when an interrupt occurs or * when a context switch occurs at the end of an ISR. */ @@ -551,14 +551,14 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; /** * @ingroup CPUInterrupt - * This variable points to the lowest physical address of the interrupt + * This variable points to the lowest physical address of the interrupt * stack. */ SCORE_EXTERN void *_CPU_Interrupt_stack_low; /** * @ingroup CPUInterrupt - * This variable points to the lowest physical address of the interrupt + * This variable points to the lowest physical address of the interrupt * stack. */ SCORE_EXTERN void *_CPU_Interrupt_stack_high; @@ -652,7 +652,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high; * * @note This does not have to be a power of 2 although it should be * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least + * to be a multiple of 2 is because the heap uses the least * significant field of the front and back flags to indicate * that a block is in use or free. So you do not want any odd * length blocks really putting length data in that bit. @@ -729,7 +729,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high; { \ asm volatile ("cli %0; csync \n" : "=d" (_level) ); \ } - + /** * @ingroup CPUInterrupt @@ -941,7 +941,7 @@ void _CPU_Context_Initialize( /** * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation * - * This set of routines are used to implement fast searches for + * This set of routines are used to implement fast searches for * the most important ready task. */ @@ -966,7 +966,7 @@ void _CPU_Context_Initialize( /** * @ingroup CPUBitfield * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type + * set in @a _value. @a _value is of CPU dependent type * @a Priority_Bit_map_control. This type may be either 16 or 32 bits * wide although only the 16 least significant bits will be used. * @@ -1009,14 +1009,14 @@ void _CPU_Context_Initialize( if _value > 0x00ff _value >>=8 _number = 8; - + if _value > 0x0000f _value >=8 _number += 4 - + _number += bit_set_table[ _value ] @endverbatim - + * where bit_set_table[ 16 ] has values which indicate the first * bit set * @@ -1089,7 +1089,7 @@ void _CPU_Initialize(void); /** * @ingroup CPUInterrupt - * This routine installs a "raw" interrupt handler directly into the + * This routine installs a "raw" interrupt handler directly into the * processor's vector table. * * @param[in] vector is the vector number @@ -1251,12 +1251,12 @@ static inline uint32_t CPU_swap_u32( ) { uint32_t byte1, byte2, byte3, byte4, swapped; - + byte4 = (value >> 24) & 0xff; byte3 = (value >> 16) & 0xff; byte2 = (value >> 8) & 0xff; byte1 = value & 0xff; - + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; return( swapped ); } diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h b/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h index 4708f37c50..a4c7be9a5e 100644 --- a/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h +++ b/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h @@ -4,7 +4,7 @@ /* * Defines a couple of Macros used in cpu_asm.S - * + * * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. * written by Alain Schaefer <alain.schaefer@easc.ch> * and Antonio Giovanini <antonio@atos.com.br> diff --git a/cpukit/score/cpu/c4x/cpu_asm.S b/cpukit/score/cpu/c4x/cpu_asm.S index 020c3a8d9e..95c2b31290 100644 --- a/cpukit/score/cpu/c4x/cpu_asm.S +++ b/cpukit/score/cpu/c4x/cpu_asm.S @@ -70,7 +70,7 @@ * ) * * TMS320C3x General-Purpose Applications User's Guide, section 2.4 - * (p 2-11 and following), Context Switching in Interrupts and + * (p 2-11 and following), Context Switching in Interrupts and * Subroutines states that "If the program is in a subroutine, it * must preserve the dedicated C registers as follows:" * @@ -136,7 +136,7 @@ _local_restore: * efficient manner. It may simply be a label in _CPU_Context_switch. * * NOTE: May be unnecessary to reload some registers. - * + * * void _CPU_Context_restore( * Context_Control *new_context * ) @@ -191,10 +191,10 @@ SYM(_CPU_Context_restore): * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) * restore stack * #endif - * + * * if ( !_Context_Switch_necessary ) * goto the label "exit interrupt (simple case)" - * + * * if ( !_ISR_Signals_to_thread_executing ) * _ISR_Signals_to_thread_executing = FALSE; * goto the label "exit interrupt (simple case)" @@ -211,7 +211,7 @@ SYM(_CPU_Context_restore): .global SYM(_ISR_Handler_save_registers) SYM(_ISR_Handler_save_registers): - ; no push st because it is already pushed + ; no push st because it is already pushed ; no push ar2 because it is already pushed and vector number loaded push ar0 push ar1 @@ -279,7 +279,7 @@ SYM(_ISR_Handler_save_registers): ; no pop r4 because other part of register is in basic context popf r4 pop r4 - popf r3 + popf r3 pop r3 popf r2 pop r2 @@ -287,7 +287,7 @@ SYM(_ISR_Handler_save_registers): pop r1 popf r0 pop r0 - + pop bk pop rc pop re @@ -305,9 +305,9 @@ SYM(_ISR_Handler_save_registers): * Prologues so we can know the vector number. Generated by this script: * * i=0 - * while test $i -lt 64 + * while test $i -lt 64 * do - * + * * printf "\t.global\tSYM(rtems_irq_prologue_%X)\n" $i * printf "SYM(rtems_irq_prologue_%X):\n" $i * printf "\tpush\tst\n" @@ -316,7 +316,7 @@ SYM(_ISR_Handler_save_registers): * printf "\tbr\tSYM(_ISR_Handler_save_registers)\n" * printf "\n" * i=`expr $i + 1` - * + * * done */ diff --git a/cpukit/score/cpu/i386/cpu.c b/cpukit/score/cpu/i386/cpu.c index e9c2dc64e0..d5300e1006 100644 --- a/cpukit/score/cpu/i386/cpu.c +++ b/cpukit/score/cpu/i386/cpu.c @@ -76,7 +76,7 @@ void _CPU_Initialize(void) * As a courtesy, we double-check here but it * may be too late (which is also why we don't * enable SSE here). - */ + */ { uint32_t cr4; __asm__ __volatile__("mov %%cr4, %0":"=r"(cr4)); diff --git a/cpukit/score/cpu/i386/rtems/score/cpu.h b/cpukit/score/cpu/i386/rtems/score/cpu.h index 77e6c6bff3..731fcd73c7 100644 --- a/cpukit/score/cpu/i386/rtems/score/cpu.h +++ b/cpukit/score/cpu/i386/rtems/score/cpu.h @@ -360,7 +360,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high; uint32_t _CPU_ISR_Get_level( void ); -/* Make sure interrupt stack has space for ISR +/* Make sure interrupt stack has space for ISR * 'vector' arg at the top and that it is aligned * properly. */ @@ -391,7 +391,7 @@ uint32_t _CPU_ISR_Get_level( void ); /* * Stack alignment note: - * + * * We want the stack to look to the '_entry_point' routine * like an ordinary stack frame as if '_entry_point' was * called from C-code. @@ -405,7 +405,7 @@ uint32_t _CPU_ISR_Get_level( void ); * ------ (alignment boundary) * SP-> return_addr return here when _entry_point returns which (never happens) * - * + * * Hence we must initialize the stack as follows * * [arg1 ]: n/a diff --git a/cpukit/score/cpu/i386/sse_test.c b/cpukit/score/cpu/i386/sse_test.c index a6e0fbd6bd..e54b77830b 100644 --- a/cpukit/score/cpu/i386/sse_test.c +++ b/cpukit/score/cpu/i386/sse_test.c @@ -1,18 +1,18 @@ /* $Id$ */ -/* +/* * Authorship * ---------- * This software was created by * Till Straumann <strauman@slac.stanford.edu>, 2009, * Stanford Linear Accelerator Center, Stanford University. - * + * * Acknowledgement of sponsorship * ------------------------------ * This software was produced by * the Stanford Linear Accelerator Center, Stanford University, * under Contract DE-AC03-76SFO0515 with the Department of Energy. - * + * * Government disclaimer of liability * ---------------------------------- * Neither the United States nor the United States Department of Energy, @@ -21,18 +21,18 @@ * completeness, or usefulness of any data, apparatus, product, or process * disclosed, or represents that its use would not infringe privately owned * rights. - * + * * Stanford disclaimer of liability * -------------------------------- * Stanford University makes no representations or warranties, express or * implied, nor assumes any liability for the use of this software. - * + * * Stanford disclaimer of copyright * -------------------------------- * Stanford University, owner of the copyright, hereby disclaims its * copyright and all other rights in this software. Hence, anyone may - * freely use it for any purpose without restriction. - * + * freely use it for any purpose without restriction. + * * Maintenance of notices * ---------------------- * In the interest of clarity regarding the origin and status of this @@ -41,10 +41,10 @@ * or distributed by the recipient and are to be affixed to any copy of * software made or distributed by the recipient that contains a copy or * derivative of this software. - * + * * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 */ - + /* Code for testing FPU/SSE context save/restore across exceptions * (including interrupts). @@ -60,7 +60,7 @@ * 2b loads context from 1) into FPU/SSE * 2c raises an exception or interrupt * - * * (2d save FPU/SSE context after irq/exception returns to + * * (2d save FPU/SSE context after irq/exception returns to * separate area for verification * 2e reload original FP/SSE context.) * @@ -228,7 +228,7 @@ fp_ld(Context_Control_sse *p_ctxt, int i) #define SSECLOBBER \ "xmm0","xmm1","xmm2","xmm3", \ - "xmm4","xmm5","xmm6","xmm7" + "xmm4","xmm5","xmm6","xmm7" static void sse_clobber(uint32_t x) @@ -308,7 +308,7 @@ stor_ctxt(Context_Control_sse *p_ctxt) rval = 1; \ if ( !quiet ) \ fprintf(stderr,#fld" mismatch ("fmt" != "fmt")\n",a->fld, b->fld); \ - } + } #define FLTCMP(i) \ do { \ @@ -664,7 +664,7 @@ int errs = 0; /* Test if FP/SSE context is saved/restored across an exception */ sse_test_ohdl = _currentExcHandler; - _currentExcHandler = sse_test_ehdl; + _currentExcHandler = sse_test_ehdl; if ( (sse_tests & SSE_TEST_FPU_EXC) ) { if ( (st = exc_raise(FP_EXC)) ) { diff --git a/cpukit/score/cpu/lm32/cpu.c b/cpukit/score/cpu/lm32/cpu.c index 825a70f96b..b796b6a1e6 100644 --- a/cpukit/score/cpu/lm32/cpu.c +++ b/cpukit/score/cpu/lm32/cpu.c @@ -50,7 +50,7 @@ void _CPU_Initialize(void) * * XXX document implementation including references if appropriate */ - + uint32_t _CPU_ISR_Get_level( void ) { /* @@ -68,7 +68,7 @@ uint32_t _CPU_ISR_Get_level( void ) * * XXX document implementation including references if appropriate */ - + void _CPU_ISR_install_raw_handler( uint32_t vector, proc_ptr new_handler, diff --git a/cpukit/score/cpu/lm32/cpu_asm.S b/cpukit/score/cpu/lm32/cpu_asm.S index 02e1f6928a..bfed8cb1af 100644 --- a/cpukit/score/cpu/lm32/cpu_asm.S +++ b/cpukit/score/cpu/lm32/cpu_asm.S @@ -108,7 +108,7 @@ _CPU_Context_switch_restore: _CPU_Context_restore: mv r2, r1 bi _CPU_Context_switch_restore - + /* void _ISR_Handler() * * This routine provides the RTEMS interrupt management. @@ -125,7 +125,7 @@ _CPU_Context_restore: * handles interrupt nesting, software interrupt stack setup etc and * finally calls the user ISR. * At the end the saved registers are restored. - * + * */ .globl _ISR_Handler @@ -180,18 +180,18 @@ found_irq: mvhi r3, hi(__ISR_Handler) ori r3, r3, lo(__ISR_Handler) call r3 - + exit_isr: /* Restore the saved registers */ lw r1, (sp+4) - lw r2, (sp+8) - lw r3, (sp+12) - lw r4, (sp+16) - lw r5, (sp+20) - lw r6, (sp+24) - lw r7, (sp+28) - lw r8, (sp+32) - lw r9, (sp+36) + lw r2, (sp+8) + lw r3, (sp+12) + lw r4, (sp+16) + lw r5, (sp+20) + lw r6, (sp+24) + lw r7, (sp+28) + lw r8, (sp+32) + lw r9, (sp+36) lw r10, (sp+40) lw ra, (sp+44) lw ea, (sp+48) diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu.h b/cpukit/score/cpu/lm32/rtems/score/cpu.h index f6b6a9210c..41c30ca099 100644 --- a/cpukit/score/cpu/lm32/rtems/score/cpu.h +++ b/cpukit/score/cpu/lm32/rtems/score/cpu.h @@ -13,7 +13,7 @@ * * + Anywhere there is an XXX, it should be replaced * with information about the CPU family being ported to. - * + * * + At the end of each comment section, there is a heading which * says "Port Specific Information:". When porting to RTEMS, * add CPU family specific information in this section @@ -168,7 +168,7 @@ extern "C" { /** * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector + * a pointer to the saved interrupt frame (1) or just the vector * number (0)? * * Port Specific Information: @@ -195,7 +195,7 @@ extern "C" { * an i387 and wish to leave floating point support out of RTEMS. */ -/** +/** * @def CPU_SOFTWARE_FP * * Does the CPU have no hardware floating point and GCC provides a @@ -203,7 +203,7 @@ extern "C" { * switched? * * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context + * is software implemented floating point that must be context * switched. The determination of whether or not this applies * is very tool specific and the state saved/restored is also * compiler specific. @@ -491,7 +491,7 @@ typedef struct { * This macro returns the stack pointer associated with @a _context. * * @param[in] _context is the thread context area to access - * + * * @return This method returns the stack pointer. */ #define _CPU_Context_Get_SP( _context ) \ @@ -562,14 +562,14 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; /** * @ingroup CPUInterrupt - * This variable points to the lowest physical address of the interrupt + * This variable points to the lowest physical address of the interrupt * stack. */ SCORE_EXTERN void *_CPU_Interrupt_stack_low; /** * @ingroup CPUInterrupt - * This variable points to the lowest physical address of the interrupt + * This variable points to the lowest physical address of the interrupt * stack. */ SCORE_EXTERN void *_CPU_Interrupt_stack_high; @@ -663,7 +663,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high; * * @note This does not have to be a power of 2 although it should be * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least + * to be a multiple of 2 is because the heap uses the least * significant field of the front and back flags to indicate * that a block is in use or free. So you do not want any odd * length blocks really putting length data in that bit. @@ -945,7 +945,7 @@ uint32_t _CPU_ISR_Get_level( void ); /** * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation * - * This set of routines are used to implement fast searches for + * This set of routines are used to implement fast searches for * the most important ready task. */ @@ -970,7 +970,7 @@ uint32_t _CPU_ISR_Get_level( void ); /** * @ingroup CPUBitfield * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type + * set in @a _value. @a _value is of CPU dependent type * @a Priority_Bit_map_control. This type may be either 16 or 32 bits * wide although only the 16 least significant bits will be used. * @@ -1013,14 +1013,14 @@ uint32_t _CPU_ISR_Get_level( void ); if _value > 0x00ff _value >>=8 _number = 8; - + if _value > 0x0000f _value >=8 _number += 4 - + _number += bit_set_table[ _value ] @endverbatim - + * where bit_set_table[ 16 ] has values which indicate the first * bit set * @@ -1092,7 +1092,7 @@ void _CPU_Initialize(void); /** * @ingroup CPUInterrupt - * This routine installs a "raw" interrupt handler directly into the + * This routine installs a "raw" interrupt handler directly into the * processor's vector table. * * @param[in] vector is the vector number @@ -1254,12 +1254,12 @@ static inline uint32_t CPU_swap_u32( ) { uint32_t byte1, byte2, byte3, byte4, swapped; - + byte4 = (value >> 24) & 0xff; byte3 = (value >> 16) & 0xff; byte2 = (value >> 8) & 0xff; byte1 = value & 0xff; - + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; return swapped; } diff --git a/cpukit/score/cpu/lm32/rtems/score/lm32.h b/cpukit/score/cpu/lm32/rtems/score/lm32.h index c8327f47a9..06ad7eb398 100644 --- a/cpukit/score/cpu/lm32/rtems/score/lm32.h +++ b/cpukit/score/cpu/lm32/rtems/score/lm32.h @@ -1,6 +1,6 @@ /* lm32.h * - * This file sets up basic CPU dependency settings based on + * This file sets up basic CPU dependency settings based on * compiler settings. For example, it can determine if * floating point is available. This particular implementation * is specified to the NO CPU port. @@ -37,25 +37,25 @@ extern "C" { * that this port supports and which RTEMS CPU model they correspond * to. */ - + #if defined(rtems_multilib) /* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. + * Figure out all CPU Model Feature Flags based upon compiler + * predefines. */ #define CPU_MODEL_NAME "rtems_multilib" #define LM32_HAS_FPU 0 #elif defined(__lm32__) - + #define CPU_MODEL_NAME "lm32" #define LM32_HAS_FPU 0 - + #else - + #error "Unsupported CPU Model" - + #endif /* |