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-rw-r--r--cpukit/score/cpu/aarch64/aarch64-exception-default.c20
-rw-r--r--cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c4
-rw-r--r--cpukit/score/cpu/aarch64/cpu.c24
-rw-r--r--cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h5
-rw-r--r--cpukit/score/cpu/aarch64/include/machine/elf_machdep.h256
-rw-r--r--cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h2
-rw-r--r--cpukit/score/cpu/aarch64/include/rtems/score/cpu.h38
-rw-r--r--cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h23
-rw-r--r--cpukit/score/cpu/arm/__aeabi_read_tp.c16
-rw-r--r--cpukit/score/cpu/arm/__tls_get_addr.c16
-rw-r--r--cpukit/score/cpu/arm/aarch32-psma-init-default.c2
-rw-r--r--cpukit/score/cpu/arm/aarch32-psma-init.c16
-rw-r--r--cpukit/score/cpu/arm/arm-context-validate.S2
-rw-r--r--cpukit/score/cpu/arm/arm-context-volatile-clobber.S2
-rw-r--r--cpukit/score/cpu/arm/arm-exception-default.c11
-rw-r--r--cpukit/score/cpu/arm/arm-exception-frame-print.c156
-rw-r--r--cpukit/score/cpu/arm/arm_exc_abort.S2
-rw-r--r--cpukit/score/cpu/arm/arm_exc_interrupt.S2
-rw-r--r--cpukit/score/cpu/arm/armv4-exception-default.S2
-rw-r--r--cpukit/score/cpu/arm/armv4-isr-install-vector.c (renamed from cpukit/score/src/coretodadjust.c)60
-rw-r--r--cpukit/score/cpu/arm/armv4-sync-synchronize.c10
-rw-r--r--cpukit/score/cpu/arm/armv7-thread-idle.c9
-rw-r--r--cpukit/score/cpu/arm/armv7m-context-initialize.c9
-rw-r--r--cpukit/score/cpu/arm/armv7m-context-restore.c7
-rw-r--r--cpukit/score/cpu/arm/armv7m-context-switch.c5
-rw-r--r--cpukit/score/cpu/arm/armv7m-exception-default.c11
-rw-r--r--cpukit/score/cpu/arm/armv7m-exception-handler-get.c7
-rw-r--r--cpukit/score/cpu/arm/armv7m-exception-handler-set.c7
-rw-r--r--cpukit/score/cpu/arm/armv7m-exception-priority-get.c8
-rw-r--r--cpukit/score/cpu/arm/armv7m-exception-priority-handler.c5
-rw-r--r--cpukit/score/cpu/arm/armv7m-exception-priority-set.c7
-rw-r--r--cpukit/score/cpu/arm/armv7m-initialize.c6
-rw-r--r--cpukit/score/cpu/arm/armv7m-isr-dispatch.c5
-rw-r--r--cpukit/score/cpu/arm/armv7m-isr-enter-leave.c7
-rw-r--r--cpukit/score/cpu/arm/armv7m-isr-level-get.c6
-rw-r--r--cpukit/score/cpu/arm/armv7m-isr-level-set.c6
-rw-r--r--cpukit/score/cpu/arm/armv7m-isr-vector-install.c7
-rw-r--r--cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c5
-rw-r--r--cpukit/score/cpu/arm/cpu.c46
-rw-r--r--cpukit/score/cpu/arm/cpu_asm.S2
-rw-r--r--cpukit/score/cpu/arm/include/libcpu/arm-cp15.h28
-rw-r--r--cpukit/score/cpu/arm/include/rtems/asm.h11
-rw-r--r--cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h2
-rw-r--r--cpukit/score/cpu/arm/include/rtems/score/aarch32-system-registers.h2
-rw-r--r--cpukit/score/cpu/arm/include/rtems/score/arm.h3
-rw-r--r--cpukit/score/cpu/arm/include/rtems/score/armv4.h19
-rw-r--r--cpukit/score/cpu/arm/include/rtems/score/armv7m.h19
-rw-r--r--cpukit/score/cpu/arm/include/rtems/score/cpu.h29
-rw-r--r--cpukit/score/cpu/arm/include/rtems/score/cpuatomic.h33
-rw-r--r--cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h33
-rw-r--r--cpukit/score/cpu/arm/include/rtems/score/paravirt.h6
-rw-r--r--cpukit/score/cpu/bfin/bfin-exception-frame-print.c2
-rw-r--r--cpukit/score/cpu/bfin/include/rtems/score/cpu.h10
-rw-r--r--cpukit/score/cpu/bfin/include/rtems/score/cpuatomic.h14
-rw-r--r--cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h31
-rw-r--r--cpukit/score/cpu/i386/cpu.c2
-rw-r--r--cpukit/score/cpu/i386/cpu_asm.S2
-rw-r--r--cpukit/score/cpu/i386/include/rtems/score/cpu.h23
-rw-r--r--cpukit/score/cpu/i386/include/rtems/score/cpuatomic.h33
-rw-r--r--cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h49
-rw-r--r--cpukit/score/cpu/i386/include/rtems/score/i386.h4
-rw-r--r--cpukit/score/cpu/lm32/include/rtems/score/cpu.h12
-rw-r--r--cpukit/score/cpu/lm32/include/rtems/score/cpuatomic.h14
-rw-r--r--cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h31
-rw-r--r--cpukit/score/cpu/lm32/lm32-exception-frame-print.c2
-rw-r--r--cpukit/score/cpu/m68k/__m68k_read_tp.c6
-rw-r--r--cpukit/score/cpu/m68k/cpu.c5
-rw-r--r--cpukit/score/cpu/m68k/include/rtems/score/cpu.h11
-rw-r--r--cpukit/score/cpu/m68k/include/rtems/score/cpuatomic.h33
-rw-r--r--cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h34
-rw-r--r--cpukit/score/cpu/m68k/m68k-exception-frame-print.c2
-rw-r--r--cpukit/score/cpu/microblaze/__tls_get_addr.c10
-rw-r--r--cpukit/score/cpu/microblaze/cpu.c2
-rw-r--r--cpukit/score/cpu/microblaze/include/machine/elf_machdep.h83
-rw-r--r--cpukit/score/cpu/microblaze/include/rtems/score/cpu.h11
-rw-r--r--cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h41
-rw-r--r--cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h25
-rw-r--r--cpukit/score/cpu/mips/include/rtems/score/cpu.h10
-rw-r--r--cpukit/score/cpu/mips/include/rtems/score/cpuatomic.h33
-rw-r--r--cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h31
-rw-r--r--cpukit/score/cpu/moxie/include/rtems/score/cpu.h12
-rw-r--r--cpukit/score/cpu/moxie/include/rtems/score/cpuatomic.h33
-rw-r--r--cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h31
-rw-r--r--cpukit/score/cpu/nios2/include/rtems/score/cpu.h10
-rw-r--r--cpukit/score/cpu/nios2/include/rtems/score/cpuatomic.h33
-rw-r--r--cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h27
-rw-r--r--cpukit/score/cpu/nios2/include/rtems/score/nios2-utility.h2
-rw-r--r--cpukit/score/cpu/nios2/nios2-context-initialize.c7
-rw-r--r--cpukit/score/cpu/nios2/nios2-context-switch.S2
-rw-r--r--cpukit/score/cpu/nios2/nios2-context-validate.S2
-rw-r--r--cpukit/score/cpu/nios2/nios2-context-volatile-clobber.S2
-rw-r--r--cpukit/score/cpu/nios2/nios2-eic-il-low-level.S2
-rw-r--r--cpukit/score/cpu/nios2/nios2-exception-frame-print.c2
-rw-r--r--cpukit/score/cpu/nios2/nios2-fatal-halt.c2
-rw-r--r--cpukit/score/cpu/nios2/nios2-iic-irq.c2
-rw-r--r--cpukit/score/cpu/nios2/nios2-isr-get-level.c2
-rw-r--r--cpukit/score/cpu/nios2/nios2-isr-is-in-progress.c2
-rw-r--r--cpukit/score/cpu/nios2/nios2-isr-set-level.c2
-rw-r--r--cpukit/score/cpu/nios2/nios2-mpu-add-region.c2
-rw-r--r--cpukit/score/cpu/nios2/nios2-mpu-configuration.c2
-rw-r--r--cpukit/score/cpu/nios2/nios2-mpu-descriptor.c2
-rw-r--r--cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c2
-rw-r--r--cpukit/score/cpu/nios2/nios2-mpu-reset.c2
-rw-r--r--cpukit/score/cpu/nios2/nios2-thread-dispatch-disabled.c2
-rw-r--r--cpukit/score/cpu/no_cpu/cpucounterfrequency.c2
-rw-r--r--cpukit/score/cpu/no_cpu/cpucounterread.c2
-rw-r--r--cpukit/score/cpu/no_cpu/cpuidle.c18
-rw-r--r--cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h44
-rw-r--r--cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h57
-rw-r--r--cpukit/score/cpu/or1k/include/rtems/score/cpu.h12
-rw-r--r--cpukit/score/cpu/or1k/include/rtems/score/cpuatomic.h33
-rw-r--r--cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h23
-rw-r--r--cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h10
-rw-r--r--cpukit/score/cpu/powerpc/cpu.c8
-rw-r--r--cpukit/score/cpu/powerpc/include/rtems/asm.h10
-rw-r--r--cpukit/score/cpu/powerpc/include/rtems/powerpc/registers.h4
-rw-r--r--cpukit/score/cpu/powerpc/include/rtems/score/cpu.h44
-rw-r--r--cpukit/score/cpu/powerpc/include/rtems/score/cpuatomic.h33
-rw-r--r--cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h31
-rw-r--r--cpukit/score/cpu/powerpc/ppc-context-validate.S77
-rw-r--r--cpukit/score/cpu/powerpc/ppc-context-volatile-clobber.S2
-rw-r--r--cpukit/score/cpu/powerpc/ppc-isr-disable-mask.S2
-rw-r--r--cpukit/score/cpu/riscv/cpu.c14
-rw-r--r--cpukit/score/cpu/riscv/include/libcpu/access.h25
-rw-r--r--cpukit/score/cpu/riscv/include/libcpu/byteorder.h2
-rw-r--r--cpukit/score/cpu/riscv/include/rtems/score/cpu.h44
-rw-r--r--cpukit/score/cpu/riscv/include/rtems/score/cpuatomic.h31
-rw-r--r--cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h39
-rw-r--r--cpukit/score/cpu/riscv/riscv-context-initialize.c4
-rw-r--r--cpukit/score/cpu/riscv/riscv-context-switch.S2
-rw-r--r--cpukit/score/cpu/riscv/riscv-context-validate.S2
-rw-r--r--cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S2
-rw-r--r--cpukit/score/cpu/riscv/riscv-counter.S2
-rw-r--r--cpukit/score/cpu/riscv/riscv-exception-frame-print.c2
-rw-r--r--cpukit/score/cpu/riscv/riscv-exception-handler.S2
-rw-r--r--cpukit/score/cpu/sh/include/rtems/score/cpu.h10
-rw-r--r--cpukit/score/cpu/sh/include/rtems/score/cpuatomic.h14
-rw-r--r--cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h31
-rw-r--r--cpukit/score/cpu/sh/sh-exception-frame-print.c2
-rw-r--r--cpukit/score/cpu/sparc/cpu.c4
-rw-r--r--cpukit/score/cpu/sparc/cpu_asm.S37
-rw-r--r--cpukit/score/cpu/sparc/include/libcpu/byteorder.h16
-rw-r--r--cpukit/score/cpu/sparc/include/libcpu/grlib-tn-0018.h11
-rw-r--r--cpukit/score/cpu/sparc/include/rtems/asm.h6
-rw-r--r--cpukit/score/cpu/sparc/include/rtems/score/cpu.h61
-rw-r--r--cpukit/score/cpu/sparc/include/rtems/score/cpuatomic.h33
-rw-r--r--cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h39
-rw-r--r--cpukit/score/cpu/sparc/include/rtems/score/sparc.h6
-rw-r--r--cpukit/score/cpu/sparc/include/rtems/score/sparcimpl.h97
-rw-r--r--cpukit/score/cpu/sparc/sparc-bad-trap.S2
-rw-r--r--cpukit/score/cpu/sparc/sparc-context-validate.S2
-rw-r--r--cpukit/score/cpu/sparc/sparc-context-volatile-clobber.S2
-rw-r--r--cpukit/score/cpu/sparc/sparc-counter-asm.S151
-rw-r--r--cpukit/score/cpu/sparc/sparc-exception-frame-print.c2
-rw-r--r--cpukit/score/cpu/sparc/sparc-isr-handler.S8
-rw-r--r--cpukit/score/cpu/sparc/syscall.S4
-rw-r--r--cpukit/score/cpu/sparc/syscall.h8
-rw-r--r--cpukit/score/cpu/sparc64/cpu.c2
-rw-r--r--cpukit/score/cpu/sparc64/include/rtems/score/cpu.h10
-rw-r--r--cpukit/score/cpu/sparc64/include/rtems/score/cpuatomic.h33
-rw-r--r--cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h31
-rw-r--r--cpukit/score/cpu/sparc64/sparc64-exception-frame-print.c2
-rw-r--r--cpukit/score/cpu/v850/include/rtems/score/cpu.h10
-rw-r--r--cpukit/score/cpu/v850/include/rtems/score/cpuatomic.h33
-rw-r--r--cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h31
-rw-r--r--cpukit/score/cpu/v850/v850-exception-frame-print.c2
-rw-r--r--cpukit/score/cpu/x86_64/include/rtems/score/cpu.h17
-rw-r--r--cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h20
-rw-r--r--cpukit/score/cpu/x86_64/include/rtems/score/cpuatomic.h14
-rw-r--r--cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h37
-rw-r--r--cpukit/score/src/allocatormutex.c2
-rw-r--r--cpukit/score/src/chainnodecount.c2
-rw-r--r--cpukit/score/src/condition.c2
-rw-r--r--cpukit/score/src/configstackspacesize.c2
-rw-r--r--cpukit/score/src/coremsgwkspace.c2
-rw-r--r--cpukit/score/src/coretodcheck.c2
-rw-r--r--cpukit/score/src/debugisthreaddispatchingallowed.c2
-rw-r--r--cpukit/score/src/debugunreachable.c (renamed from cpukit/score/src/ioprintf.c)24
-rw-r--r--cpukit/score/src/futex.c2
-rw-r--r--cpukit/score/src/hash.c6
-rw-r--r--cpukit/score/src/heap.c2
-rw-r--r--cpukit/score/src/heapallocate.c2
-rw-r--r--cpukit/score/src/heapextend.c2
-rw-r--r--cpukit/score/src/heapgreedy.c2
-rw-r--r--cpukit/score/src/heapiterate.c2
-rw-r--r--cpukit/score/src/heapnoextend.c2
-rw-r--r--cpukit/score/src/heapresizeblock.c2
-rw-r--r--cpukit/score/src/iobase64.c111
-rw-r--r--cpukit/score/src/iorelax.c53
-rw-r--r--cpukit/score/src/iovprintf.c377
-rw-r--r--cpukit/score/src/isr.c2
-rw-r--r--cpukit/score/src/isrisinprogress.c2
-rw-r--r--cpukit/score/src/isrvectortable.c2
-rw-r--r--cpukit/score/src/kern_ntptime.c59
-rw-r--r--cpukit/score/src/kern_tc.c169
-rw-r--r--cpukit/score/src/libatomic.c2
-rw-r--r--cpukit/score/src/memoryallocate.c2
-rw-r--r--cpukit/score/src/memorydirtyfreeareas.c9
-rw-r--r--cpukit/score/src/memoryfill.c2
-rw-r--r--cpukit/score/src/memorynoinit.c (renamed from cpukit/score/cpu/aarch64/include/rtems/score/cpuatomic.h)23
-rw-r--r--cpukit/score/src/memoryzerobeforeuse.c2
-rw-r--r--cpukit/score/src/memoryzerofreeareas.c9
-rw-r--r--cpukit/score/src/mpci.c2
-rw-r--r--cpukit/score/src/mutex.c2
-rw-r--r--cpukit/score/src/objectactivecount.c20
-rw-r--r--cpukit/score/src/objectallocate.c2
-rw-r--r--cpukit/score/src/objectallocatenone.c2
-rw-r--r--cpukit/score/src/objectallocatestatic.c2
-rw-r--r--cpukit/score/src/objectallocateunlimited.c2
-rw-r--r--cpukit/score/src/objectextendinformation.c2
-rw-r--r--cpukit/score/src/objectfree.c12
-rw-r--r--cpukit/score/src/objectfreenothing.c2
-rw-r--r--cpukit/score/src/objectfreestatic.c2
-rw-r--r--cpukit/score/src/objectgetlocal.c2
-rw-r--r--cpukit/score/src/objectinitializeinformation.c1
-rw-r--r--cpukit/score/src/once.c2
-rw-r--r--cpukit/score/src/opt_compat.h2
-rw-r--r--cpukit/score/src/opt_ffclock.h2
-rw-r--r--cpukit/score/src/opt_ntp.h2
-rw-r--r--cpukit/score/src/percpuasm.c9
-rw-r--r--cpukit/score/src/percpudata.c11
-rw-r--r--cpukit/score/src/percpujobs.c2
-rw-r--r--cpukit/score/src/percpustatewait.c2
-rw-r--r--cpukit/score/src/pheapiterate.c52
-rw-r--r--cpukit/score/src/pheapresizeblock.c60
-rw-r--r--cpukit/score/src/processormaskcopy.c2
-rw-r--r--cpukit/score/src/profilingisrentryexit.c7
-rw-r--r--cpukit/score/src/profilingsmplock.c2
-rw-r--r--cpukit/score/src/rbtreeappend.c2
-rw-r--r--cpukit/score/src/rbtreeiterate.c2
-rw-r--r--cpukit/score/src/rbtreemax.c4
-rw-r--r--cpukit/score/src/rbtreemin.c4
-rw-r--r--cpukit/score/src/rbtreenext.c4
-rw-r--r--cpukit/score/src/rbtreepostorder.c2
-rw-r--r--cpukit/score/src/rbtreeprepend.c2
-rw-r--r--cpukit/score/src/rbtreeprev.c4
-rw-r--r--cpukit/score/src/rbtreereplace.c2
-rw-r--r--cpukit/score/src/sched.c2
-rw-r--r--cpukit/score/src/schedulerdefaultmakecleansticky.c2
-rw-r--r--cpukit/score/src/schedulerdefaultmappriority.c2
-rw-r--r--cpukit/score/src/schedulerdefaultpinunpin.c2
-rw-r--r--cpukit/score/src/schedulerdefaultpinunpindonothing.c2
-rw-r--r--cpukit/score/src/schedulerdefaultschedule.c2
-rw-r--r--cpukit/score/src/schedulerdefaultstartidle.c2
-rw-r--r--cpukit/score/src/scheduleredfblock.c4
-rw-r--r--cpukit/score/src/scheduleredfchangepriority.c5
-rw-r--r--cpukit/score/src/scheduleredfschedule.c5
-rw-r--r--cpukit/score/src/scheduleredfsmp.c2
-rw-r--r--cpukit/score/src/scheduleredfunblock.c20
-rw-r--r--cpukit/score/src/scheduleredfyield.c2
-rw-r--r--cpukit/score/src/schedulergetaffinity.c2
-rw-r--r--cpukit/score/src/schedulerpriorityblock.c4
-rw-r--r--cpukit/score/src/schedulerprioritychangepriority.c5
-rw-r--r--cpukit/score/src/schedulerpriorityschedule.c5
-rw-r--r--cpukit/score/src/schedulerprioritysmp.c2
-rw-r--r--cpukit/score/src/schedulerpriorityunblock.c16
-rw-r--r--cpukit/score/src/schedulerpriorityyield.c5
-rw-r--r--cpukit/score/src/schedulersetaffinity.c2
-rw-r--r--cpukit/score/src/schedulersimpleblock.c4
-rw-r--r--cpukit/score/src/schedulersimplechangepriority.c5
-rw-r--r--cpukit/score/src/schedulersimpleschedule.c5
-rw-r--r--cpukit/score/src/schedulersimplesmp.c2
-rw-r--r--cpukit/score/src/schedulersimpleunblock.c20
-rw-r--r--cpukit/score/src/schedulersimpleyield.c5
-rw-r--r--cpukit/score/src/schedulersmp.c2
-rw-r--r--cpukit/score/src/schedulersmpstartidle.c2
-rw-r--r--cpukit/score/src/schedulerstrongapa.c2
-rw-r--r--cpukit/score/src/semaphore.c2
-rw-r--r--cpukit/score/src/smp.c7
-rw-r--r--cpukit/score/src/smpbarrierwait.c2
-rw-r--r--cpukit/score/src/smpbroadcastaction.c2
-rw-r--r--cpukit/score/src/smplock.c2
-rw-r--r--cpukit/score/src/smpmulticastaction.c2
-rw-r--r--cpukit/score/src/smpothercastaction.c2
-rw-r--r--cpukit/score/src/smpsynchronize.c2
-rw-r--r--cpukit/score/src/smpunicastaction.c2
-rw-r--r--cpukit/score/src/stackallocator.c2
-rw-r--r--cpukit/score/src/stackallocatorforidle.c44
-rw-r--r--cpukit/score/src/stackallocatorforidlewkspace.c (renamed from cpukit/score/src/pheapgetblocksize.c)32
-rw-r--r--cpukit/score/src/stackallocatorfree.c2
-rw-r--r--cpukit/score/src/stackallocatorinit.c2
-rw-r--r--cpukit/score/src/threadallocateunlimited.c2
-rw-r--r--cpukit/score/src/threadchangepriority.c15
-rw-r--r--cpukit/score/src/threadcreateidle.c52
-rw-r--r--cpukit/score/src/threaddispatch.c19
-rw-r--r--cpukit/score/src/threadentryadaptoridle.c2
-rw-r--r--cpukit/score/src/threadentryadaptornumeric.c2
-rw-r--r--cpukit/score/src/threadentryadaptorpointer.c2
-rw-r--r--cpukit/score/src/threadexhausttimeslice.c2
-rw-r--r--cpukit/score/src/threadgetcputimeused.c2
-rw-r--r--cpukit/score/src/threadgetcputimeusedafterreset.c2
-rw-r--r--cpukit/score/src/threadidledefault.c2
-rw-r--r--cpukit/score/src/threadinitialize.c14
-rw-r--r--cpukit/score/src/threaditerate.c2
-rw-r--r--cpukit/score/src/threadname.c2
-rw-r--r--cpukit/score/src/threadplaindispatch.c2
-rw-r--r--cpukit/score/src/threadq.c2
-rw-r--r--cpukit/score/src/threadqenqueue.c3
-rw-r--r--cpukit/score/src/threadqextract.c2
-rw-r--r--cpukit/score/src/threadqgetnameandid.c2
-rw-r--r--cpukit/score/src/threadqops.c21
-rw-r--r--cpukit/score/src/threadqtimeout.c7
-rw-r--r--cpukit/score/src/threadresettimeslice.c2
-rw-r--r--cpukit/score/src/threadrestart.c131
-rw-r--r--cpukit/score/src/threadscheduler.c2
-rw-r--r--cpukit/score/src/threadselfid.c2
-rw-r--r--cpukit/score/src/threadunpin.c2
-rw-r--r--cpukit/score/src/threadwaitgetid.c2
-rw-r--r--cpukit/score/src/threadyield.c2
-rw-r--r--cpukit/score/src/tlsallocsize.c83
-rw-r--r--cpukit/score/src/userextiterate.c6
-rw-r--r--cpukit/score/src/watchdoginsert.c2
-rw-r--r--cpukit/score/src/watchdogremove.c2
-rw-r--r--cpukit/score/src/watchdogtick.c6
-rw-r--r--cpukit/score/src/watchdogtimeslicedefault.c2
-rw-r--r--cpukit/score/src/wkspace.c2
-rw-r--r--cpukit/score/src/wkspaceisunifieddefault.c2
-rw-r--r--cpukit/score/src/wkspacemallocinitdefault.c2
-rw-r--r--cpukit/score/src/wkspacemallocinitunified.c2
-rw-r--r--cpukit/score/src/wkstringduplicate.c2
320 files changed, 2390 insertions, 2529 deletions
diff --git a/cpukit/score/cpu/aarch64/aarch64-exception-default.c b/cpukit/score/cpu/aarch64/aarch64-exception-default.c
index 3494c88ea6..f1591cbd5d 100644
--- a/cpukit/score/cpu/aarch64/aarch64-exception-default.c
+++ b/cpukit/score/cpu/aarch64/aarch64-exception-default.c
@@ -48,6 +48,26 @@
void _AArch64_Exception_default( CPU_Exception_frame *frame )
{
+ uint64_t EC = AARCH64_ESR_EL1_EC_GET( frame->register_syndrome );
+
+ /* Emulate FPSR flags for FENV if a FPU exception occurred */
+ if ( EC == 0x2c ) {
+ /*
+ * This must be done because FENV depends on FPSR values, but trapped FPU
+ * exceptions don't set FPSR bits. In the case where a signal is mapped, the
+ * signal code executes after the exception frame is restored and FENV
+ * functions executed in that context will need this information to be
+ * accurate.
+ */
+ uint64_t ISS = AARCH64_ESR_EL1_EC_GET( frame->register_syndrome );
+
+ /* If the exception bits are valid, use them */
+ if ( ( ISS & ( 1 << 23 ) ) != 0 ) {
+ /* The bits of the lower byte match the FPSR exception bits */
+ frame->register_fpsr |= ( ISS & 0xff );
+ }
+ }
+
rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame );
}
diff --git a/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c b/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
index e207a5a81d..04a3dfdc0d 100644
--- a/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
+++ b/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
@@ -45,7 +45,7 @@
#include <inttypes.h>
#include <rtems/score/cpu.h>
-#include <rtems/score/io.h>
+#include <rtems/dev/io.h>
#include <rtems/bspIo.h>
typedef struct {
@@ -216,7 +216,7 @@ void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
for ( i = 0 ; i < 32 ; ++i ) {
uint64_t low = (uint64_t) qx[i];
- uint64_t high = (uint64_t) (qx[i] >> 32);
+ uint64_t high = (uint64_t) (qx[i] >> 64);
printk( "Q%02i = 0x%016" PRIx64 "%016" PRIx64 "\n", i, high, low );
}
diff --git a/cpukit/score/cpu/aarch64/cpu.c b/cpukit/score/cpu/aarch64/cpu.c
index 88e7ad8a8c..207508302b 100644
--- a/cpukit/score/cpu/aarch64/cpu.c
+++ b/cpukit/score/cpu/aarch64/cpu.c
@@ -142,7 +142,7 @@ void _CPU_Context_Initialize(
the_context->thread_id = (uintptr_t) tls_area;
if ( tls_area != NULL ) {
- _TLS_TCB_at_area_begin_initialize( tls_area );
+ the_context->thread_id = (uintptr_t) _TLS_Initialize_area( tls_area );
}
}
@@ -174,28 +174,6 @@ uint32_t _CPU_ISR_Get_level( void )
return ( level & AARCH64_PSTATE_I ) != 0;
}
-void _CPU_ISR_install_vector(
- uint32_t vector,
- CPU_ISR_handler new_handler,
- CPU_ISR_handler *old_handler
-)
-{
- /* Redirection table starts at the end of the vector table */
- CPU_ISR_handler *table = (CPU_ISR_handler *) (MAX_EXCEPTIONS * 4);
-
- CPU_ISR_handler current_handler = table [vector];
-
- /* The current handler is now the old one */
- if (old_handler != NULL) {
- *old_handler = current_handler;
- }
-
- /* Write only if necessary to avoid writes to a maybe read-only memory */
- if (current_handler != new_handler) {
- table [vector] = new_handler;
- }
-}
-
void _CPU_Initialize( void )
{
/* Do nothing */
diff --git a/cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h b/cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h
index 6b6296bb7a..ca9b60e6d1 100644
--- a/cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h
+++ b/cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h
@@ -60,7 +60,6 @@ extern "C" {
#define MMU_PAGE_BITS 12
#define MMU_PAGE_SIZE ( 1 << MMU_PAGE_BITS )
#define MMU_BITS_PER_LEVEL 9
-#define MMU_TOP_LEVEL_PAGE_BITS ( 2 * MMU_BITS_PER_LEVEL + MMU_PAGE_BITS )
#define AARCH64_MMU_FLAGS_BASE \
( MMU_DESC_VALID | MMU_DESC_SH_INNER | MMU_DESC_AF )
@@ -71,7 +70,7 @@ extern "C" {
#define AARCH64_MMU_CODE_RW_CACHED AARCH64_MMU_DATA_RW_CACHED
#define AARCH64_MMU_DATA_RO \
- ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 1 ) | MMU_DESC_WRITE_DISABLE )
+ ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 2 ) | MMU_DESC_WRITE_DISABLE )
#define AARCH64_MMU_CODE AARCH64_MMU_DATA_RO
#define AARCH64_MMU_CODE_RW AARCH64_MMU_DATA_RW
@@ -79,7 +78,7 @@ extern "C" {
#define AARCH64_MMU_DATA_RW_CACHED \
( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 3 ) )
#define AARCH64_MMU_DATA_RW \
- ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 1 ) )
+ ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 2 ) )
#define AARCH64_MMU_DEVICE ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 0 ) )
rtems_status_code aarch64_mmu_map(
diff --git a/cpukit/score/cpu/aarch64/include/machine/elf_machdep.h b/cpukit/score/cpu/aarch64/include/machine/elf_machdep.h
new file mode 100644
index 0000000000..c1d219d715
--- /dev/null
+++ b/cpukit/score/cpu/aarch64/include/machine/elf_machdep.h
@@ -0,0 +1,256 @@
+/* $NetBSD: elf_machdep.h,v 1.4 2018/10/12 01:28:58 ryo Exp $ */
+
+/*-
+ * Copyright (c) 2014 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _AARCH64_ELF_MACHDEP_H_
+#define _AARCH64_ELF_MACHDEP_H_
+
+#ifdef __aarch64__
+
+#if defined(__AARCH64EB__)
+#define ELF64_MACHDEP_ENDIANNESS ELFDATA2MSB
+#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB
+#else
+#define ELF64_MACHDEP_ENDIANNESS ELFDATA2LSB
+#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB
+#endif
+
+/* Processor specific flags for the ELF header e_flags field. */
+#define EF_ARM_RELEXEC 0x00000001
+#define EF_ARM_HASENTRY 0x00000002
+#define EF_ARM_INTERWORK 0x00000004 /* GNU binutils 000413 */
+#define EF_ARM_SYMSARESORTED 0x00000004 /* ARM ELF A08 */
+#define EF_ARM_APCS_26 0x00000008 /* GNU binutils 000413 */
+#define EF_ARM_DYNSYMSUSESEGIDX 0x00000008 /* ARM ELF B01 */
+#define EF_ARM_APCS_FLOAT 0x00000010 /* GNU binutils 000413 */
+#define EF_ARM_MAPSYMSFIRST 0x00000010 /* ARM ELF B01 */
+#define EF_ARM_PIC 0x00000020
+#define EF_ARM_ALIGN8 0x00000040 /* 8-bit structure alignment. */
+#define EF_ARM_NEW_ABI 0x00000080
+#define EF_ARM_OLD_ABI 0x00000100
+#define EF_ARM_SOFT_FLOAT 0x00000200
+#define EF_ARM_BE8 0x00800000
+#define EF_ARM_EABIMASK 0xff000000
+#define EF_ARM_EABI_VER1 0x01000000
+#define EF_ARM_EABI_VER2 0x02000000
+#define EF_ARM_EABI_VER3 0x03000000
+#define EF_ARM_EABI_VER4 0x04000000
+#define EF_ARM_EABI_VER5 0x05000000
+
+#define ELF32_MACHDEP_ID_CASES \
+ case EM_ARM: \
+ break;
+
+#define ELF64_MACHDEP_ID_CASES \
+ case EM_AARCH64: \
+ break;
+
+#define ELF64_MACHDEP_ID EM_AARCH64
+#define ELF32_MACHDEP_ID EM_ARM
+
+#define KERN_ELFSIZE 64
+#define ARCH_ELFSIZE 64 /* MD native binary size */
+
+/* Processor specific relocation types */
+
+#define R_AARCH64_NONE 0
+#define R_AARCH64_NONE2 256
+
+#define R_AARCH64_ABS64 257 /* S + A */
+#define R_AARCH64_ABS32 258 /* S + A */
+#define R_AARCH64_ABS16 259 /* S + A */
+#define R_AARCH64_PREL64 260 /* S + A - P */
+#define R_AARCH64_PREL32 261 /* S + A - P */
+#define R_AARCH64_PREL16 262 /* S + A - P */
+#define R_AARCH64_MOVW_UABS_G0 263 /* S + A [bits 0..15] */
+#define R_AARCH64_MOVW_UABS_G0_NC 264 /* S + A [bits 0..15] */
+#define R_AARCH64_MOVW_UABS_G1 265 /* S + A [bits 16..31] */
+#define R_AARCH64_MOVW_UABS_G1_NC 266 /* S + A [bits 16..31] */
+#define R_AARCH64_MOVW_UABS_G2 267 /* S + A [bits 32..47] */
+#define R_AARCH64_MOVW_UABS_G2_NC 268 /* S + A [bits 32..47] */
+#define R_AARCH64_MOVW_UABS_G3 269 /* S + A [bits 48..63] */
+#define R_AARCH64_MOVW_SABS_G0 270 /* S + A [bits 0..15] */
+#define R_AARCH64_MOVW_SABS_G1 271 /* S + A [bits 16..31] */
+#define R_AARCH64_MOVW_SABS_G2 272 /* S + A [bits 32..47] */
+#define R_AARCH64_LD_PREL_LO19 273 /* S + A - P */
+#define R_AARCH64_ADR_PREL_LO21 274 /* S + A - P */
+#define R_AARCH64_ADR_PREL_PG_HI21 275 /* Page(S + A) - Page(P) */
+#define R_AARCH64_ADR_PREL_PG_HI21_NC 276 /* Page(S + A) - Page(P) */
+#define R_AARCH64_ADD_ABS_LO12_NC 277 /* S + A */
+#define R_AARCH64_LDST8_ABS_LO12_NC 278 /* S + A */
+#define R_AARCH_TSTBR14 279 /* S + A - P */
+#define R_AARCH_CONDBR19 281 /* S + A - P */
+#define R_AARCH_JUMP26 282 /* S + A - P */
+#define R_AARCH_CALL26 283 /* S + A - P */
+#define R_AARCH_LDST16_ABS_LO12_NC 284 /* S + A */
+#define R_AARCH_LDST32_ABS_LO12_NC 285 /* S + A */
+#define R_AARCH_LDST64_ABS_LO12_NC 286 /* S + A */
+#define R_AARCH64_MOVW_PREL_G0 287 /* S + A - P */
+#define R_AARCH64_MOVW_PREL_G0_NC 288 /* S + A - P */
+#define R_AARCH64_MOVW_PREL_G1 289 /* S + A - P */
+#define R_AARCH64_MOVW_PREL_G1_NC 290 /* S + A - P */
+#define R_AARCH64_MOVW_PREL_G2 291 /* S + A - P */
+#define R_AARCH64_MOVW_PREL_G2_NC 292 /* S + A - P */
+#define R_AARCH64_MOVW_PREL_G3 293 /* S + A - P */
+
+#define R_AARCH64_LDST128_ABS_LO12_NC 299 /* S + A */
+#define R_AARCH64_MOVW_GOTOFF_G0 300 /* G(GDAT(S + A)) - GOT */
+#define R_AARCH64_MOVW_GOTOFF_G0_NC 301 /* G(GDAT(S + A)) - GOT */
+#define R_AARCH64_MOVW_GOTOFF_G1 302 /* G(GDAT(S + A)) - GOT */
+#define R_AARCH64_MOVW_GOTOFF_G1_NC 303 /* G(GDAT(S + A)) - GOT */
+#define R_AARCH64_MOVW_GOTOFF_G2 304 /* G(GDAT(S + A)) - GOT */
+#define R_AARCH64_MOVW_GOTOFF_G2_NC 305 /* G(GDAT(S + A)) - GOT */
+#define R_AARCH64_MOVW_GOTOFF_G3 306 /* G(GDAT(S + A)) - GOT */
+#define R_AARCH64_GOTREL64 307 /* S + A - GOT */
+#define R_AARCH64_GOTREL32 308 /* S + A - GOT */
+#define R_AARCH64_GOT_LD_PREL19 309 /* G(GDAT(S + A)) - P */
+#define R_AARCH64_LD64_GOTOFF_LO15 310 /* G(GDAT(S + A)) - GOT */
+#define R_AARCH64_ADR_GOT_PAGE 311 /* Page(G(GDAT(S + A))) - Page(GOT) */
+#define R_AARCH64_LD64_GOT_LO12_NC 312 /* G(GDAT(S + A)) */
+#define R_AARCH64_LD64_GOTPAGE_LO15 313 /* G(GDAT(S + A)) - Page(GOT) */
+
+#define R_AARCH64_TLSGD_ADR_PREL21 512 /* G(GTLSIDX(S,A)) - P */
+#define R_AARCH64_TLSGD_ADR_PAGE21 513 /* Page(G(GTLSIDX(S,A))) - Page(P) */
+#define R_AARCH64_TLSGD_ADD_LO12_NC 514 /* G(GTLSIDX(S,A)) */
+#define R_AARCH64_TLSGD_MOVW_G1 515 /* G(GTLSIDX(S,A)) - GOT */
+#define R_AARCH64_TLSGD_MOVW_G0_NV 516 /* G(GTLSIDX(S,A)) - GOT */
+#define R_AARCH64_TLSLD_ADR_PREL21 517 /* G(GLDM(S,A)) - P */
+#define R_AARCH64_TLSLD_ADR_PAGE21 518 /* Page(G(GLDM(S))) - Page(P) */
+#define R_AARCH64_TLSLD_ADD_LO12_NC 519 /* G(GLDM(S)) */
+#define R_AARCH64_TLSLD_MOVW_G1 520 /* G(GLDM(S)) - GOT */
+#define R_AARCH64_TLSLD_MOVW_G0_NC 521 /* G(GLDM(S)) - GOT */
+#define R_AARCH64_TLSLD_LD_PREL21 522 /* G(GLDM(S)) - P */
+#define R_AARCH64_TLSLD_MOVW_DTPREL_G2 523 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_MOVW_DTPREL_G1 524 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 525 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_MOVW_DTPREL_G0 526 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 528 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_ADD_DTPREL_HI12 528 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_ADD_DTPREL_HI12 528 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_ADD_DTPREL_LO12 529 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 530 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST8_DTPREL_LO12 531 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 532 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST16_DTPREL_LO12 533 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 534 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST32_DTPREL_LO12 535 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 536 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST64_DTPREL_LO12 537 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 538 /* DTPREL(S+A) */
+#define R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 539 /* G(GTPREL(S+A)) - GOT */
+#define R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 540 /* G(GTPREL(S+A)) - GOT */
+#define R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 541 /* Page(G(GTPREL(S+A))) - Page(P) */
+#define R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 542 /* G(GTPREL(S+A)) */
+#define R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 543 /* G(GTPREL(S+A)) - P */
+#define R_AARCH64_TLSLE_MOVW_TPREL_G2 544 /* TPREL(S+A) */
+#define R_AARCH64_MOVW_TPREL_G1 545 /* TPREL(S+A) */
+#define R_AARCH64_MOVW_TPREL_G1_NC 546 /* TPREL(S+A) */
+#define R_AARCH64_MOVW_TPREL_G0 547 /* TPREL(S+A) */
+#define R_AARCH64_MOVW_TPREL_G0_NC 548 /* TPREL(S+A) */
+#define R_AARCH64_ADD_TPREL_HI12 549 /* TPREL(S+A) */
+#define R_AARCH64_ADD_TPREL_LO12 550 /* TPREL(S+A) */
+#define R_AARCH64_ADD_TPREL_LO12_NC 551 /* TPREL(S+A) */
+#define R_AARCH64_LDST8_TPREL_LO12 552 /* TPREL(S+A) */
+#define R_AARCH64_LDST8_TPREL_LO12_NC 553 /* TPREL(S+A) */
+#define R_AARCH64_LDST16_TPREL_LO12 554 /* TPREL(S+A) */
+#define R_AARCH64_LDST16_TPREL_LO12_NC 555 /* TPREL(S+A) */
+#define R_AARCH64_LDST32_TPREL_LO12 556 /* TPREL(S+A) */
+#define R_AARCH64_LDST32_TPREL_LO12_NC 557 /* TPREL(S+A) */
+#define R_AARCH64_LDST64_TPREL_LO12 558 /* TPREL(S+A) */
+#define R_AARCH64_LDST64_TPREL_LO12_NC 559 /* TPREL(S+A) */
+#define R_AARCH64_TLSDESC_LD_PREL19 560 /* G(GTLSDESC(S+A)) - P */
+#define R_AARCH64_TLSDESC_LD_PREL21 561 /* G(GTLSDESC(S+A)) - P */
+#define R_AARCH64_TLSDESC_LD_PAGE21 562 /* Page(G(GTLSDESC(S+A))) - Page(P) */
+#define R_AARCH64_TLSDESC_LD64_LO12 563 /* G(GTLSDESC(S+A)) */
+#define R_AARCH64_TLSDESC_ADD_LO12 564 /* G(GTLSDESC(S+A)) */
+#define R_AARCH64_TLSDESC_OFF_G1 565 /* G(GTLSDESC(S+A)) - GOT */
+#define R_AARCH64_TLSDESC_OFF_G0_NC 566 /* G(GTLSDESC(S+A)) - GOT */
+#define R_AARCH64_TLSDESC_LDR 567 /* */
+#define R_AARCH64_TLSDESC_ADD 568 /* */
+#define R_AARCH64_TLSDESC_CALL 569 /* */
+#define R_AARCH64_TLSLE_LDST128_TPREL_LO12 570 /* TPREL(S+A) */
+#define R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC 571 /* TPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST128_DTPREL_LO12 572 /* DTPREL(S+A) */
+#define R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC 572 /* DTPREL(S+A) */
+
+/* Dynamic Relocations */
+#define R_AARCH64_P32_COPY 180
+#define R_AARCH64_P32_GLOB_DAT 181 /* S + A */
+#define R_AARCH64_P32_JUMP_SLOT 182 /* S + A */
+#define R_AARCH64_P32_RELATIVE 183 /* Delta(S) + A */
+#define R_AARCH64_P32_TLS_DTPREL 184 /* DTPREL(S+A) */
+#define R_AARCH64_P32_TLS_DTPMOD 185 /* LBM(S) */
+#define R_AARCH64_P32_TLS_TPREL 186 /* TPREL(S+A) */
+#define R_AARCH64_P32_TLSDESC 187 /* TLSDESC(S+A) */
+#define R_AARCH64_P32_IRELATIVE 188 /* Indirect(Delta(S) + A) */
+
+#define R_AARCH64_COPY 1024
+#define R_AARCH64_GLOB_DAT 1025 /* S + A */
+#define R_AARCH64_JUMP_SLOT 1026 /* S + A */
+#define R_AARCH64_RELATIVE 1027 /* Delta(S) + A */
+#define R_AARCH64_TLS_DTPREL64 1028 /* DTPREL(S+A) */
+#define R_AARCH64_TLS_DTPMOD64 1029 /* LBM(S) */
+#define R_AARCH64_TLS_TPREL64 1030 /* TPREL(S+A) */
+#define R_AARCH64_TLSDESC 1031 /* TLSDESC(S+A) */
+#define R_AARCH64_IRELATIVE 1032 /* Indirect(Delta(S) + A) */
+
+#define R_TYPE(name) R_AARCH64_ ## name
+#define R_TLS_TYPE(name) R_AARCH64_ ## name ## 64
+
+/* Processor specific program header types */
+#define PT_AARCH64_ARCHEXT (PT_LOPROC + 0)
+#define PT_AARCH64_UNWIND (PT_LOPROC + 1)
+
+/* Processor specific section header flags */
+#define SHF_ENTRYSECT 0x10000000
+#define SHF_COMDEF 0x80000000
+
+#define SHT_AARCH64_ATTRIBUTES (SHT_LOPROC + 3)
+
+#ifdef _KERNEL
+#ifdef ELFSIZE
+#define ELF_MD_PROBE_FUNC ELFNAME2(aarch64_netbsd,probe)
+#endif
+
+struct exec_package;
+
+int aarch64_netbsd_elf64_probe(struct lwp *, struct exec_package *, void *,
+ char *, vaddr_t *);
+int aarch64_netbsd_elf32_probe(struct lwp *, struct exec_package *, void *,
+ char *, vaddr_t *);
+#endif
+
+#elif defined(__arm__)
+
+#include <arm/elf_machdep.h>
+
+#endif
+
+#endif /* _AARCH64_ELF_MACHDEP_H_ */
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h b/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h
index 5bfddb6dad..8ddad5becf 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-system-registers.h
@@ -8,7 +8,7 @@
*/
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
index fdc0e3d929..aa4f90f1a8 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
@@ -43,6 +43,7 @@
#endif
#include <rtems/score/aarch64.h>
#include <libcpu/vectors.h>
+#include <limits.h>
/**
* @addtogroup RTEMSScoreCPUAArch64
@@ -101,7 +102,7 @@
#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
-#define CPU_STACK_MINIMUM_SIZE (1024 * 10)
+#define CPU_STACK_MINIMUM_SIZE (1024 * 8)
/* This could be either 4 or 8, depending on the ABI in use.
* Could also use __LP64__ or __ILP32__ */
@@ -156,7 +157,14 @@
extern "C" {
#endif
+/*
+ This is to fix the following warning
+ ISO C does not support 'uint128_t' types
+*/
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
typedef unsigned __int128 uint128_t;
+#pragma GCC diagnostic pop
typedef struct {
uint64_t register_x19;
@@ -252,7 +260,7 @@ static inline void AArch64_interrupt_flash( uint64_t isr_cookie )
#define _CPU_ISR_Flash( _isr_cookie ) \
AArch64_interrupt_flash( _isr_cookie )
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint64_t isr_cookie )
+static inline bool _CPU_ISR_Is_enabled( uint64_t isr_cookie )
{
return ( isr_cookie & AARCH64_PSTATE_I ) == 0;
}
@@ -306,12 +314,6 @@ void _CPU_Initialize( void );
typedef void ( *CPU_ISR_handler )( void );
-void _CPU_ISR_install_vector(
- uint32_t vector,
- CPU_ISR_handler new_handler,
- CPU_ISR_handler *old_handler
-);
-
/**
* @brief CPU switch context.
*/
@@ -382,14 +384,6 @@ uint32_t _CPU_Counter_frequency( void );
CPU_Counter_ticks _CPU_Counter_read( void );
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
void *_CPU_Thread_Idle_body( uintptr_t ignored );
typedef enum {
@@ -410,7 +404,7 @@ typedef enum {
AARCH64_EXCEPTION_LEL32_FIQ = 14,
AARCH64_EXCEPTION_LEL32_SERROR = 15,
MAX_EXCEPTIONS = 16,
- AARCH64_EXCEPTION_MAKE_ENUM_64_BIT = 0xffffffffffffffff
+ AARCH64_EXCEPTION_MAKE_ENUM_64_BIT = INT_MAX
} AArch64_symbolic_exception_name;
#define VECTOR_POINTER_OFFSET 0x78
@@ -438,7 +432,15 @@ static inline void* AArch64_set_exception_handler(
*vector_address = handler;
/* return now-previous vector pointer */
- return (void*)current_vector_pointer;
+
+/*
+ * This was put in to fix the following warning:
+ * warning: ISO C forbids conversion of function pointer to object pointer type.
+ */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+ return (void*)current_vector_pointer;
+#pragma GCC diagnostic pop
}
typedef struct {
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
index ffdef2f30a..8a0e476899 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
@@ -50,8 +50,11 @@
*/
#define CPU_PER_CPU_CONTROL_SIZE 0
+
#define CPU_INTERRUPT_FRAME_SIZE 0x2E0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 11
+
#ifndef ASM
#ifdef __cplusplus
@@ -152,16 +155,32 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( ".inst 0x0" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ __asm__ volatile (
+ "msr TPIDR_EL0, %0" : : "r" ( context->thread_id ) : "memory"
+ );
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ return (void *)(uintptr_t) context->thread_id;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/arm/__aeabi_read_tp.c b/cpukit/score/cpu/arm/__aeabi_read_tp.c
index 671065825d..0f4eba8d9a 100644
--- a/cpukit/score/cpu/arm/__aeabi_read_tp.c
+++ b/cpukit/score/cpu/arm/__aeabi_read_tp.c
@@ -1,7 +1,15 @@
/* SPDX-License-Identifier: BSD-2-Clause */
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of __aeabi_read_tp().
+ */
+
/*
- * Copyright (c) 2014 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2014 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -42,15 +50,15 @@ void __attribute__((naked)) __aeabi_read_tp(void)
"ldr r0, =_Per_CPU_Information\n"
"ldr r0, [r0, %[executingoff]]\n"
#if defined(__thumb__) && !defined(__thumb2__)
- "add r0, %[tlsareaoff]\n"
+ "add r0, %[threadidoff]\n"
"ldr r0, [r0]\n"
#else
- "ldr r0, [r0, %[tlsareaoff]]\n"
+ "ldr r0, [r0, %[threadidoff]]\n"
#endif
"bx lr\n"
:
: [executingoff] "I" (offsetof(Per_CPU_Control, executing)),
- [tlsareaoff] "I" (offsetof(Thread_Control, Start.tls_area))
+ [threadidoff] "I" (offsetof(Thread_Control, Registers.thread_id))
);
}
diff --git a/cpukit/score/cpu/arm/__tls_get_addr.c b/cpukit/score/cpu/arm/__tls_get_addr.c
index 5c8e60ae06..407bf3d639 100644
--- a/cpukit/score/cpu/arm/__tls_get_addr.c
+++ b/cpukit/score/cpu/arm/__tls_get_addr.c
@@ -1,7 +1,15 @@
/* SPDX-License-Identifier: BSD-2-Clause */
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of __tls_get_addr().
+ */
+
/*
- * Copyright (c) 2014-2015 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2014, 2015 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -39,10 +47,10 @@ void *__tls_get_addr(const TLS_Index *ti);
void *__tls_get_addr(const TLS_Index *ti)
{
const Thread_Control *executing = _Thread_Get_executing();
- void *tls_block = (char *) executing->Start.tls_area
- + _TLS_Get_thread_control_block_area_size( (uintptr_t) _TLS_Alignment );
+ void *tls_data = (char *) executing->Registers.thread_id
+ + _TLS_Get_thread_control_block_area_size( &_TLS_Configuration );
assert(ti->module == 1);
- return (char *) tls_block + ti->offset;
+ return (char *) tls_data + ti->offset;
}
diff --git a/cpukit/score/cpu/arm/aarch32-psma-init-default.c b/cpukit/score/cpu/arm/aarch32-psma-init-default.c
index da710d77fc..615e7a528a 100644
--- a/cpukit/score/cpu/arm/aarch32-psma-init-default.c
+++ b/cpukit/score/cpu/arm/aarch32-psma-init-default.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/arm/aarch32-psma-init.c b/cpukit/score/cpu/arm/aarch32-psma-init.c
index ee9338f050..93a3673a98 100644
--- a/cpukit/score/cpu/arm/aarch32-psma-init.c
+++ b/cpukit/score/cpu/arm/aarch32-psma-init.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,7 +45,7 @@
#include <rtems/score/aarch32-system-registers.h>
#include <rtems/score/cpu.h>
-#define AARCH32_PSMA_REGION_MAX \
+#define AARCH32_PMSA_REGION_MAX \
( ( AARCH32_MPUIR_REGION_MASK >> AARCH32_MPUIR_REGION_SHIFT ) + 1 )
static void _AArch32_PMSA_Configure(
@@ -133,16 +133,16 @@ size_t _AArch32_PMSA_Map_sections_to_regions(
if ( attr == region_attr ) {
uint32_t region_end;
- if ( end == region_base ) {
- /* Extend the region region */
+ if ( end - region_base <= AARCH32_PMSA_MIN_REGION_ALIGN ) {
+ /* Extend the region */
regions[ ri ].base = base;
break;
}
region_end = region_limit + AARCH32_PMSA_MIN_REGION_ALIGN;
- if ( base == region_end ) {
- /* Extend the region region */
+ if ( region_end - base <= AARCH32_PMSA_MIN_REGION_ALIGN ) {
+ /* Extend the region */
regions[ ri ].limit = limit;
break;
}
@@ -153,7 +153,7 @@ size_t _AArch32_PMSA_Map_sections_to_regions(
}
}
- if ( end <= region_base ) {
+ if ( base <= region_base ) {
size_t i;
if ( region_used >= region_max ) {
@@ -196,7 +196,7 @@ void _AArch32_PMSA_Initialize(
size_t section_count
)
{
- AArch32_PMSA_Region regions[ AARCH32_PSMA_REGION_MAX ];
+ AArch32_PMSA_Region regions[ AARCH32_PMSA_REGION_MAX ];
size_t region_max;
size_t region_used;
diff --git a/cpukit/score/cpu/arm/arm-context-validate.S b/cpukit/score/cpu/arm/arm-context-validate.S
index 424fa60daf..51157071dd 100644
--- a/cpukit/score/cpu/arm/arm-context-validate.S
+++ b/cpukit/score/cpu/arm/arm-context-validate.S
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2013, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S
index ac40755d4d..5cbbb27754 100644
--- a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S
+++ b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2013, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/arm/arm-exception-default.c b/cpukit/score/cpu/arm/arm-exception-default.c
index d2b2fc2767..02df769287 100644
--- a/cpukit/score/cpu/arm/arm-exception-default.c
+++ b/cpukit/score/cpu/arm/arm-exception-default.c
@@ -1,7 +1,16 @@
/* SPDX-License-Identifier: BSD-2-Clause */
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ * _ARM_Exception_default().
+ */
+
/*
- * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/arm/arm-exception-frame-print.c b/cpukit/score/cpu/arm/arm-exception-frame-print.c
index 4bb1efedec..b089648184 100644
--- a/cpukit/score/cpu/arm/arm-exception-frame-print.c
+++ b/cpukit/score/cpu/arm/arm-exception-frame-print.c
@@ -1,7 +1,16 @@
/* SPDX-License-Identifier: BSD-2-Clause */
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ * _CPU_Exception_frame_print().
+ */
+
/*
- * Copyright (c) 2012-2013 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2012, 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -32,11 +41,14 @@
#include <inttypes.h>
#include <rtems/score/cpu.h>
+#if defined(ARM_MULTILIB_ARCH_V7M)
+#include <rtems/score/armv7m.h>
+#endif
#include <rtems/bspIo.h>
static void _ARM_VFP_context_print( const ARM_VFP_context *vfp_context )
{
-#ifdef ARM_MULTILIB_VFP_D32
+#ifdef ARM_MULTILIB_VFP
if ( vfp_context != NULL ) {
const uint64_t *dx = &vfp_context->register_d0;
int i;
@@ -47,7 +59,14 @@ static void _ARM_VFP_context_print( const ARM_VFP_context *vfp_context )
vfp_context->register_fpscr
);
- for ( i = 0; i < 32; ++i ) {
+#if defined(ARM_MULTILIB_VFP_D32)
+ int regcount = 32;
+#elif defined(ARM_MULTILIB_VFP_D16)
+ int regcount = 16;
+#else
+ int regcount = 0;
+#endif
+ for ( i = 0; i < regcount; ++i ) {
uint32_t low = (uint32_t) dx[i];
uint32_t high = (uint32_t) (dx[i] >> 32);
@@ -57,6 +76,136 @@ static void _ARM_VFP_context_print( const ARM_VFP_context *vfp_context )
#endif
}
+static void _ARM_Cortex_M_fault_info_print( void )
+{
+#if defined(ARM_MULTILIB_ARCH_V7M)
+ /*
+ * prints content of additional debugging registers
+ * available on Cortex-Mx where x > 0 cores.
+ */
+ uint32_t cfsr = _ARMV7M_SCB->cfsr;
+ uint8_t mmfsr = ARMV7M_SCB_CFSR_MMFSR_GET( cfsr );
+ uint8_t bfsr = ( ARMV7M_SCB_CFSR_BFSR_GET( cfsr ) >> 8 );
+ uint16_t ufsr = ( ARMV7M_SCB_CFSR_UFSR_GET( cfsr ) >> 16 );
+ uint32_t hfsr = _ARMV7M_SCB->hfsr;
+ if ( mmfsr > 0 ) {
+ printk( "MMFSR= 0x%08" PRIx32 " (memory fault)\n", mmfsr );
+ if ( ( mmfsr & 0x1 ) != 0 ) {
+ printk( " IACCVIOL : 1 (instruction access violation)\n" );
+ }
+ if ( ( mmfsr & 0x2 ) != 0 ) {
+ printk( " DACCVIOL : 1 (data access violation)\n" );
+ }
+ if ( (mmfsr & 0x8 ) != 0 ) {
+ printk(
+ " MUNSTKERR : 1 (fault on unstacking on exception return)\n"
+ );
+ }
+ if ( ( mmfsr & 0x10 ) != 0 ) {
+ printk( " MSTKERR : 1 (fault on stacking on exception entry)\n" );
+ }
+ if ( (mmfsr & 0x20 ) != 0 ) {
+ printk( " MLSPERR : 1 (fault during lazy FP stack preservation)\n" );
+ }
+ if ( (mmfsr & 0x80 ) != 0 ) {
+ printk(
+ " MMFARVALID : 1 -> 0x%08" PRIx32 " (error address)\n",
+ _ARMV7M_SCB->mmfar
+ );
+ }
+ else {
+ printk( " MMFARVALID : 0 (undetermined error address)\n" );
+ }
+ }
+ if ( bfsr > 0 ) {
+ printk( "BFSR = 0x%08" PRIx32 " (bus fault)\n", bfsr );
+ if ( ( bfsr & 0x1 ) != 0 ) {
+ printk( " IBUSERR : 1 (instruction fetch error)\n" );
+ }
+ if ( (bfsr & 0x2 ) != 0 ) {
+ printk(
+ " PRECISERR : 1 (data bus error with known exact location)\n"
+ );
+ }
+ if ( ( bfsr & 0x4) != 0 ) {
+ printk(
+ " IMPRECISERR: 1 (data bus error without known exact location)\n"
+ );
+ }
+ if ( (bfsr & 0x8 ) != 0 ) {
+ printk(
+ " UNSTKERR : 1 (fault on unstacking on exception return)\n"
+ );
+ }
+ if ( ( bfsr & 0x10 ) != 0 ) {
+ printk( " STKERR : 1 (fault on stacking on exception entry)\n" );
+ }
+ if ( ( bfsr & 0x20 ) != 0 ) {
+ printk( " LSPERR : 1 (fault during lazy FP stack preservation)\n" );
+ }
+ if ( (bfsr & 0x80 ) != 0 ) {
+ printk(
+ " BFARVALID : 1 -> 0x%08" PRIx32 " (error address)\n",
+ _ARMV7M_SCB->bfar
+ );
+ }
+ else {
+ printk( " BFARVALID : 0 (undetermined error address)\n" );
+ }
+ }
+ if ( ufsr > 0 ) {
+ printk( "UFSR = 0x%08" PRIx32 " (usage fault)\n", ufsr);
+ if ( (ufsr & 0x1 ) != 0 ) {
+ printk( " UNDEFINSTR : 1 (undefined instruction issued)\n");
+ }
+ if ( (ufsr & 0x2 ) != 0 ) {
+ printk(
+ " INVSTATE : 1"
+ " (invalid instruction state"
+ " (Thumb not set in EPSR or invalid IT state in EPSR))\n"
+ );
+ }
+ if ( (ufsr & 0x4 ) != 0 ) {
+ printk( " INVPC : 1 (integrity check failure on EXC_RETURN)\n" );
+ }
+ if ( (ufsr & 0x8 ) != 0 ) {
+ printk(
+ " NOCP : 1"
+ " (coprocessor instruction issued"
+ " but coprocessor disabled or non existent)\n"
+ );
+ }
+ if ( ( ufsr & 0x100) != 0 ) {
+ printk( " UNALIGNED : 1 (unaligned access operation occurred)\n" );
+ }
+ if ( ( ufsr & 0x200) != 0 ) {
+ printk( " DIVBYZERO : 1 (division by zero)" );
+ }
+ }
+ if ( (hfsr & (
+ ARMV7M_SCB_HFSR_VECTTBL_MASK
+ | ARMV7M_SCB_HFSR_DEBUGEVT_MASK
+ | ARMV7M_SCB_HFSR_FORCED_MASK
+ ) ) != 0 ) {
+ printk( "HFSR = 0x%08" PRIx32 " (hard fault)\n", hfsr );
+ if ( (hfsr & ARMV7M_SCB_HFSR_VECTTBL_MASK ) != 0 ) {
+ printk(
+ " VECTTBL : 1 (error in address located in vector table)\n"
+ );
+ }
+ if ( (hfsr & ARMV7M_SCB_HFSR_FORCED_MASK ) != 0 ) {
+ printk(
+ " FORCED : 1 (configurable fault escalated to hard fault)\n"
+ );
+ }
+ if ( (hfsr & ARMV7M_SCB_HFSR_DEBUGEVT_MASK ) != 0 ) {
+ printk(
+ " DEBUGEVT : 1 (debug event occurred with debug system disabled)\n"
+ );
+ }
+ }
+#endif
+}
void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
{
printk(
@@ -100,4 +249,5 @@ void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
);
_ARM_VFP_context_print( frame->vfp_context );
+ _ARM_Cortex_M_fault_info_print();
}
diff --git a/cpukit/score/cpu/arm/arm_exc_abort.S b/cpukit/score/cpu/arm/arm_exc_abort.S
index b2fe0b726a..2721e3fed0 100644
--- a/cpukit/score/cpu/arm/arm_exc_abort.S
+++ b/cpukit/score/cpu/arm/arm_exc_abort.S
@@ -9,7 +9,7 @@
*/
/*
- * Copyright (c) 2009 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2009 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/arm/arm_exc_interrupt.S b/cpukit/score/cpu/arm/arm_exc_interrupt.S
index 696aeb786f..5a7109da26 100644
--- a/cpukit/score/cpu/arm/arm_exc_interrupt.S
+++ b/cpukit/score/cpu/arm/arm_exc_interrupt.S
@@ -9,7 +9,7 @@
*/
/*
- * Copyright (c) 2009, 2022 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2009, 2022 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/arm/armv4-exception-default.S b/cpukit/score/cpu/arm/armv4-exception-default.S
index 595951073d..a23aef76a4 100644
--- a/cpukit/score/cpu/arm/armv4-exception-default.S
+++ b/cpukit/score/cpu/arm/armv4-exception-default.S
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/coretodadjust.c b/cpukit/score/cpu/arm/armv4-isr-install-vector.c
index 907e5b06d7..739b02f8bf 100644
--- a/cpukit/score/src/coretodadjust.c
+++ b/cpukit/score/cpu/arm/armv4-isr-install-vector.c
@@ -3,15 +3,19 @@
/**
* @file
*
- * @ingroup RTEMSScoreTOD
+ * @ingroup RTEMSScoreCPUARM
*
- * @brief This source file contains the implementation of
- * _TOD_Adjust().
+ * @brief This source file contains the ARM-specific _CPU_ISR_install_vector().
*/
/*
- * COPYRIGHT (c) 1989-2014.
- * On-Line Applications Research Corporation (OAR).
+ * COPYRIGHT (c) 2000 Canon Research Centre France SA.
+ * Emmanuel Raguet, mailto:raguet@crf.canon.fr
+ *
+ * Copyright (c) 2002 Advent Networks, Inc
+ * Jay Monkman <jmonkman@adventnetworks.com>
+ *
+ * Copyright (C) 2009, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -39,35 +43,33 @@
#include "config.h"
#endif
-#include <rtems/score/todimpl.h>
+#include <rtems/score/cpu.h>
-Status_Control _TOD_Adjust(
- const struct timespec *delta
+#ifdef ARM_MULTILIB_ARCH_V4
+
+void _CPU_ISR_install_vector(
+ uint32_t vector,
+ CPU_ISR_handler new_handler,
+ CPU_ISR_handler *old_handler
)
{
- ISR_lock_Context lock_context;
- struct timespec tod;
- Status_Control status;
-
- /*
- * Currently, RTEMS does the adjustment in one movement.
- * Given interest, requirements, and sponsorship, a future
- * enhancement would be to adjust the time in smaller increments
- * at each clock tick. Until then, there is no outstanding
- * adjustment.
- */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Warray-bounds"
+ /* Redirection table starts at the end of the vector table */
+ CPU_ISR_handler volatile *table = (CPU_ISR_handler *) (MAX_EXCEPTIONS * 4);
- _TOD_Lock();
- _TOD_Acquire( &lock_context );
- _TOD_Get( &tod );
- _Timespec_Add_to( &tod, delta );
- status = _TOD_Is_valid_new_time_of_day( &tod );
+ CPU_ISR_handler current_handler = table [vector];
- if ( status == STATUS_SUCCESSFUL ) {
- status = _TOD_Set( &tod, &lock_context );
+ /* The current handler is now the old one */
+ if (old_handler != NULL) {
+ *old_handler = current_handler;
}
- _TOD_Unlock();
-
- return status;
+ /* Write only if necessary to avoid writes to a maybe read-only memory */
+ if (current_handler != new_handler) {
+ table [vector] = new_handler;
+ }
+#pragma GCC diagnostic pop
}
+
+#endif /* ARM_MULTILIB_ARCH_V4 */
diff --git a/cpukit/score/cpu/arm/armv4-sync-synchronize.c b/cpukit/score/cpu/arm/armv4-sync-synchronize.c
index 4445022fd6..2f454306d8 100644
--- a/cpukit/score/cpu/arm/armv4-sync-synchronize.c
+++ b/cpukit/score/cpu/arm/armv4-sync-synchronize.c
@@ -1,7 +1,15 @@
/* SPDX-License-Identifier: BSD-2-Clause */
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of __sync_synchronize().
+ */
+
/*
- * Copyright (c) 2015 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2015 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/arm/armv7-thread-idle.c b/cpukit/score/cpu/arm/armv7-thread-idle.c
index 399e41796e..720cb2be83 100644
--- a/cpukit/score/cpu/arm/armv7-thread-idle.c
+++ b/cpukit/score/cpu/arm/armv7-thread-idle.c
@@ -1,13 +1,16 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @brief CPU Thread Idle Body
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ * _CPU_Thread_Idle_body().
*/
/*
- * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/arm/armv7m-context-initialize.c b/cpukit/score/cpu/arm/armv7m-context-initialize.c
index 6bdedecb77..d67bcf93b5 100644
--- a/cpukit/score/cpu/arm/armv7m-context-initialize.c
+++ b/cpukit/score/cpu/arm/armv7m-context-initialize.c
@@ -1,9 +1,12 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @brief CPU Initialize Context
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ * _CPU_Context_Initialize().
*/
/*
@@ -61,7 +64,7 @@ void _CPU_Context_Initialize(
context->register_sp = stack_area_end;
if ( tls_area != NULL ) {
- _TLS_TCB_at_area_begin_initialize( tls_area );
+ context->thread_id = (uint32_t) _TLS_Initialize_area( tls_area );
}
}
diff --git a/cpukit/score/cpu/arm/armv7m-context-restore.c b/cpukit/score/cpu/arm/armv7m-context-restore.c
index bf402953a3..b888abe29f 100644
--- a/cpukit/score/cpu/arm/armv7m-context-restore.c
+++ b/cpukit/score/cpu/arm/armv7m-context-restore.c
@@ -1,9 +1,12 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @brief CPU Restore Context
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ * _CPU_Context_restore().
*/
/*
diff --git a/cpukit/score/cpu/arm/armv7m-context-switch.c b/cpukit/score/cpu/arm/armv7m-context-switch.c
index 091611aebf..74d6b953ef 100644
--- a/cpukit/score/cpu/arm/armv7m-context-switch.c
+++ b/cpukit/score/cpu/arm/armv7m-context-switch.c
@@ -3,7 +3,10 @@
/**
* @file
*
- * @brief ARM7M CPU Context Switch
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ * _CPU_Context_switch().
*/
/*
diff --git a/cpukit/score/cpu/arm/armv7m-exception-default.c b/cpukit/score/cpu/arm/armv7m-exception-default.c
index c9d1841afb..35dde50dc3 100644
--- a/cpukit/score/cpu/arm/armv7m-exception-default.c
+++ b/cpukit/score/cpu/arm/armv7m-exception-default.c
@@ -1,7 +1,16 @@
/* SPDX-License-Identifier: BSD-2-Clause */
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ * _ARMV7M_Exception_default().
+ */
+
/*
- * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/arm/armv7m-exception-handler-get.c b/cpukit/score/cpu/arm/armv7m-exception-handler-get.c
index 63fcfffcfa..41effd1e18 100644
--- a/cpukit/score/cpu/arm/armv7m-exception-handler-get.c
+++ b/cpukit/score/cpu/arm/armv7m-exception-handler-get.c
@@ -1,9 +1,12 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @brief ARMV7M Get Exception Handler
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ * _ARMV7M_Get_exception_handler().
*/
/*
diff --git a/cpukit/score/cpu/arm/armv7m-exception-handler-set.c b/cpukit/score/cpu/arm/armv7m-exception-handler-set.c
index a138cbeec1..94c9dc5360 100644
--- a/cpukit/score/cpu/arm/armv7m-exception-handler-set.c
+++ b/cpukit/score/cpu/arm/armv7m-exception-handler-set.c
@@ -1,9 +1,12 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @brief ARMV7M Set Exception Handler
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ * _ARMV7M_Set_exception_handler().
*/
/*
diff --git a/cpukit/score/cpu/arm/armv7m-exception-priority-get.c b/cpukit/score/cpu/arm/armv7m-exception-priority-get.c
index c22e874404..bb0892a32f 100644
--- a/cpukit/score/cpu/arm/armv7m-exception-priority-get.c
+++ b/cpukit/score/cpu/arm/armv7m-exception-priority-get.c
@@ -1,10 +1,14 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @brief ARMV7M Get Exception Priority
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ * _ARMV7M_Get_exception_priority().
*/
+
/*
* Copyright (c) 2011 Sebastian Huber. All rights reserved.
*
diff --git a/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c b/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c
index f77aa73522..b94366e07c 100644
--- a/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c
+++ b/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c
@@ -3,7 +3,10 @@
/**
* @file
*
- * @brief ARMV7M Set Exception Priority and Handler
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ * _ARMV7M_Set_exception_priority_and_handler().
*/
/*
diff --git a/cpukit/score/cpu/arm/armv7m-exception-priority-set.c b/cpukit/score/cpu/arm/armv7m-exception-priority-set.c
index da0a635497..05136a47db 100644
--- a/cpukit/score/cpu/arm/armv7m-exception-priority-set.c
+++ b/cpukit/score/cpu/arm/armv7m-exception-priority-set.c
@@ -1,9 +1,12 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @brief ARMV7M Set Exception Priority
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ * _ARMV7M_Set_exception_priority().
*/
/*
diff --git a/cpukit/score/cpu/arm/armv7m-initialize.c b/cpukit/score/cpu/arm/armv7m-initialize.c
index 6ec863fa30..0f47b49af7 100644
--- a/cpukit/score/cpu/arm/armv7m-initialize.c
+++ b/cpukit/score/cpu/arm/armv7m-initialize.c
@@ -3,11 +3,13 @@
/**
* @file
*
- * @brief ARM7M CPU Initialize
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of _CPU_Initialize().
*/
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
* Copyright (C) 2011 Sebastian Huber
*
* Redistribution and use in source and binary forms, with or without
diff --git a/cpukit/score/cpu/arm/armv7m-isr-dispatch.c b/cpukit/score/cpu/arm/armv7m-isr-dispatch.c
index 5ab9d1fae2..ea168969ba 100644
--- a/cpukit/score/cpu/arm/armv7m-isr-dispatch.c
+++ b/cpukit/score/cpu/arm/armv7m-isr-dispatch.c
@@ -3,7 +3,10 @@
/**
* @file
*
- * @brief ARMV7M ISR Dispatch
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ * _ARMV7M_Thread_dispatch().
*/
/*
diff --git a/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c b/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c
index e2f5b5b62f..1490f6e219 100644
--- a/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c
+++ b/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c
@@ -1,9 +1,12 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @brief ARMV7M Interrupt Service Enter and Leave
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ * _ARMV7M_Interrupt_service_enter() and _ARMV7M_Interrupt_service_leave().
*/
/*
diff --git a/cpukit/score/cpu/arm/armv7m-isr-level-get.c b/cpukit/score/cpu/arm/armv7m-isr-level-get.c
index d597e3bf3d..cc2b674e13 100644
--- a/cpukit/score/cpu/arm/armv7m-isr-level-get.c
+++ b/cpukit/score/cpu/arm/armv7m-isr-level-get.c
@@ -1,9 +1,11 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @brief CPU Get ISR Level
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of _CPU_ISR_Get_level().
*/
/*
diff --git a/cpukit/score/cpu/arm/armv7m-isr-level-set.c b/cpukit/score/cpu/arm/armv7m-isr-level-set.c
index 01835075fb..72c9684025 100644
--- a/cpukit/score/cpu/arm/armv7m-isr-level-set.c
+++ b/cpukit/score/cpu/arm/armv7m-isr-level-set.c
@@ -1,9 +1,11 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @brief CPU Set ISR Level
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of _CPU_ISR_Set_level().
*/
/*
diff --git a/cpukit/score/cpu/arm/armv7m-isr-vector-install.c b/cpukit/score/cpu/arm/armv7m-isr-vector-install.c
index 1616577895..c1e9eb70cb 100644
--- a/cpukit/score/cpu/arm/armv7m-isr-vector-install.c
+++ b/cpukit/score/cpu/arm/armv7m-isr-vector-install.c
@@ -1,9 +1,12 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @brief CPU ISR Vector Install
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ * _CPU_ISR_install_vector().
*/
/*
diff --git a/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c b/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c
index ffd21772a8..a9b59dec84 100644
--- a/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c
+++ b/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c
@@ -3,7 +3,10 @@
/**
* @file
*
- * @brief ARMV7M Start Multitasking
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This source file contains the implementation of
+ * _ARMV7M_Start_multitasking().
*/
/*
diff --git a/cpukit/score/cpu/arm/cpu.c b/cpukit/score/cpu/arm/cpu.c
index 5c5b253470..c27f4de9f9 100644
--- a/cpukit/score/cpu/arm/cpu.c
+++ b/cpukit/score/cpu/arm/cpu.c
@@ -5,7 +5,10 @@
*
* @ingroup RTEMSScoreCPUARM
*
- * @brief ARM architecture support implementation.
+ * @brief This source file contains static assertions to ensure the consistency
+ * of interfaces used in C and assembler and it contains the ARM-specific
+ * implementation of _CPU_Initialize(), _CPU_ISR_Get_level(),
+ * _CPU_ISR_Set_level(), _CPU_Context_Initialize(), and _CPU_Fatal_halt().
*/
/*
@@ -17,7 +20,7 @@
*
* Copyright (c) 2007 Ray xu <rayx.cn@gmail.com>
*
- * Copyright (c) 2009, 2017 embedded brains GmbH
+ * Copyright (C) 2009, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -56,13 +59,11 @@
);
#endif
-#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
- RTEMS_STATIC_ASSERT(
- offsetof( Context_Control, thread_id )
- == ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET,
- ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET
- );
-#endif
+RTEMS_STATIC_ASSERT(
+ offsetof( Context_Control, thread_id )
+ == ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET,
+ ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET
+);
#ifdef ARM_MULTILIB_ARCH_V4
RTEMS_STATIC_ASSERT(
@@ -118,13 +119,10 @@ void _CPU_Context_Initialize(
the_context->register_sp = (uint32_t) stack_area_begin + stack_area_size;
the_context->register_lr = (uint32_t) entry_point;
the_context->isr_dispatch_disable = 0;
-
-#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
the_context->thread_id = (uint32_t) tls_area;
-#endif
if ( tls_area != NULL ) {
- _TLS_TCB_at_area_begin_initialize( tls_area );
+ the_context->thread_id = (uint32_t) _TLS_Initialize_area( tls_area );
}
}
@@ -161,28 +159,6 @@ uint32_t _CPU_ISR_Get_level( void )
return ( level & ARM_PSR_I ) != 0;
}
-void _CPU_ISR_install_vector(
- uint32_t vector,
- CPU_ISR_handler new_handler,
- CPU_ISR_handler *old_handler
-)
-{
- /* Redirection table starts at the end of the vector table */
- CPU_ISR_handler *table = (CPU_ISR_handler *) (MAX_EXCEPTIONS * 4);
-
- CPU_ISR_handler current_handler = table [vector];
-
- /* The current handler is now the old one */
- if (old_handler != NULL) {
- *old_handler = current_handler;
- }
-
- /* Write only if necessary to avoid writes to a maybe read-only memory */
- if (current_handler != new_handler) {
- table [vector] = new_handler;
- }
-}
-
void _CPU_Initialize( void )
{
/* Do nothing */
diff --git a/cpukit/score/cpu/arm/cpu_asm.S b/cpukit/score/cpu/arm/cpu_asm.S
index d52a43f70d..87bbfc4f01 100644
--- a/cpukit/score/cpu/arm/cpu_asm.S
+++ b/cpukit/score/cpu/arm/cpu_asm.S
@@ -21,7 +21,7 @@
* COPYRIGHT (c) 2000 Canon Research Centre France SA.
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
*
- * Copyright (c) 2013, 2017 embedded brains GmbH
+ * Copyright (C) 2013, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
index 1e707191cf..c239eaccc8 100644
--- a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
+++ b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
@@ -10,7 +10,7 @@
/*
* Copyright (c) 2013 Hesham AL-Matary
- * Copyright (c) 2009-2017 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2009, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -1309,15 +1309,17 @@ arm_cp15_data_cache_test_and_clean(void)
);
}
-/* In DDI0301H_arm1176jzfs_r0p7_trm
- * 'MCR p15, 0, <Rd>, c7, c14, 0' means
- * Clean and Invalidate Entire Data Cache
- */
ARM_CP15_TEXT_SECTION static inline void
arm_cp15_data_cache_clean_and_invalidate(void)
{
ARM_SWITCH_REGISTERS;
+#if __ARM_ARCH >= 6
+ /*
+ * In DDI0301H_arm1176jzfs_r0p7_trm
+ * 'MCR p15, 0, <Rd>, c7, c14, 0' means
+ * Clean and Invalidate Entire Data Cache
+ */
uint32_t sbz = 0;
__asm__ volatile (
@@ -1328,6 +1330,22 @@ arm_cp15_data_cache_clean_and_invalidate(void)
: [sbz] "r" (sbz)
: "memory"
);
+#else
+ /*
+ * Assume this is an ARM926EJ-S. Use the test, clean, and invalidate DCache
+ * operation.
+ */
+ __asm__ volatile (
+ ARM_SWITCH_TO_ARM
+ "1:\n"
+ "mrc p15, 0, r15, c7, c14, 3\n"
+ "bne 1b\n"
+ ARM_SWITCH_BACK
+ : ARM_SWITCH_OUTPUT
+ :
+ : "memory"
+ );
+#endif
}
ARM_CP15_TEXT_SECTION static inline void
diff --git a/cpukit/score/cpu/arm/include/rtems/asm.h b/cpukit/score/cpu/arm/include/rtems/asm.h
index 0bbe43c837..9f676e40ab 100644
--- a/cpukit/score/cpu/arm/include/rtems/asm.h
+++ b/cpukit/score/cpu/arm/include/rtems/asm.h
@@ -3,7 +3,10 @@
/**
* @file
*
- * @brief ARM Assembler Support API
+ * @ingroup RTEMSScoreCPUARMASM
+ *
+ * @brief This header file provides interfaces to address problems caused by
+ * incompatible flavor of assemblers and toolsets.
*
* This include file attempts to address the problems
* caused by incompatible flavors of assemblers and
@@ -86,15 +89,13 @@
#define __REGISTER_PREFIX__
#endif
-#include <rtems/concat.h>
-
/* Use the right prefix for global labels. */
-#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
+#define SYM(x) RTEMS_XCONCAT(__USER_LABEL_PREFIX__, x)
/* Use the right prefix for registers. */
-#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
+#define REG(x) RTEMS_XCONCAT(__REGISTER_PREFIX__, x)
/*
* define macros for all of the registers on this CPU
diff --git a/cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h b/cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h
index d7244138ca..36541a97aa 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/arm/include/rtems/score/aarch32-system-registers.h b/cpukit/score/cpu/arm/include/rtems/score/aarch32-system-registers.h
index 2c532ca669..5af0921547 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/aarch32-system-registers.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/aarch32-system-registers.h
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/arm/include/rtems/score/arm.h b/cpukit/score/cpu/arm/include/rtems/score/arm.h
index 67fa579e67..650c48d55f 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/arm.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/arm.h
@@ -72,7 +72,8 @@ extern "C" {
#ifndef ARM_DISABLE_THREAD_ID_REGISTER_USE
#if defined(__ARM_ARCH_7A__) \
|| defined(__ARM_ARCH_7R__) \
- || __ARM_ARCH >= 8
+ || __ARM_ARCH >= 8 \
+ || __ARM_ARCH == 6
#define ARM_MULTILIB_HAS_THREAD_ID_REGISTER
#endif
#endif
diff --git a/cpukit/score/cpu/arm/include/rtems/score/armv4.h b/cpukit/score/cpu/arm/include/rtems/score/armv4.h
index 7f40fb66ce..1d3a6de5ff 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/armv4.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/armv4.h
@@ -1,7 +1,16 @@
/* SPDX-License-Identifier: BSD-2-Clause */
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This header file provides interfaces of the ARMv4 architecture
+ * support.
+ */
+
/*
- * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -34,6 +43,12 @@
extern "C" {
#endif /* __cplusplus */
+/**
+ * @addtogroup RTEMSScoreCPUARM
+ *
+ * @{
+ */
+
#ifdef ARM_MULTILIB_ARCH_V4
void bsp_interrupt_dispatch( void );
@@ -104,6 +119,8 @@ static inline void _ARMV4_Status_restore( uint32_t psr )
#endif /* ARM_MULTILIB_ARCH_V4 */
+/** @} */
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/cpukit/score/cpu/arm/include/rtems/score/armv7m.h b/cpukit/score/cpu/arm/include/rtems/score/armv7m.h
index 10b3955671..7fa48b3aa5 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/armv7m.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/armv7m.h
@@ -3,7 +3,10 @@
/**
* @file
*
- * @brief ARMV7M Architecture Support
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This header file provides interfaces of the ARMv7-M architecture
+ * support.
*/
/*
@@ -156,8 +159,19 @@ typedef struct {
#define ARMV7M_SCB_SHCSR_MEMFAULTENA (1U << 16)
uint32_t shcsr;
+#define ARMV7M_SCB_CFSR_MMFSR_MASK 0xff
+#define ARMV7M_SCB_CFSR_MMFSR_GET(n) (n & ARMV7M_SCB_CFSR_MMFSR_MASK)
+#define ARMV7M_SCB_CFSR_BFSR_MASK 0xff00
+#define ARMV7M_SCB_CFSR_BFSR_GET(n) (n & ARMV7M_SCB_CFSR_BFSR_MASK)
+#define ARMV7M_SCB_CFSR_UFSR_MASK 0xffff0000
+#define ARMV7M_SCB_CFSR_UFSR_GET(n) (n & ARMV7M_SCB_CFSR_UFSR_MASK)
uint32_t cfsr;
+
+#define ARMV7M_SCB_HFSR_VECTTBL_MASK 0x2
+#define ARMV7M_SCB_HFSR_FORCED_MASK (1U << 30)
+#define ARMV7M_SCB_HFSR_DEBUGEVT_MASK (1U << 31)
uint32_t hfsr;
+
uint32_t dfsr;
uint32_t mmfar;
uint32_t bfar;
@@ -691,6 +705,7 @@ static inline void _ARMV7M_MPU_Disable_region(
}
static inline void _ARMV7M_MPU_Setup(
+ uint32_t ctrl,
const ARMV7M_MPU_Region_config *cfg,
size_t cfg_count
)
@@ -726,7 +741,7 @@ static inline void _ARMV7M_MPU_Setup(
_ARMV7M_MPU_Disable_region(mpu, region);
}
- mpu->ctrl = ARMV7M_MPU_CTRL_ENABLE | ARMV7M_MPU_CTRL_PRIVDEFENA;
+ mpu->ctrl = ctrl;
scb->shcsr |= ARMV7M_SCB_SHCSR_MEMFAULTENA;
_ARM_Data_synchronization_barrier();
diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu.h b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
index 7ac180ac26..a462b48cf1 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
@@ -3,14 +3,17 @@
/**
* @file
*
- * @brief ARM Architecture Support API
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This header file defines implementation interfaces pertaining to the
+ * port of the executive to the ARM architecture.
*/
/*
* This include file contains information pertaining to the ARM
* processor.
*
- * Copyright (c) 2009, 2017 embedded brains GmbH
+ * Copyright (C) 2009, 2017 embedded brains GmbH & Co. KG
*
* Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com>
*
@@ -176,9 +179,7 @@
#define CPU_MAXIMUM_PROCESSORS 32
-#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
- #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44
-#endif
+#define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44
#ifdef ARM_MULTILIB_VFP
#define ARM_CONTEXT_CONTROL_D8_OFFSET 48
@@ -191,10 +192,8 @@
#ifdef RTEMS_SMP
#if defined(ARM_MULTILIB_VFP)
#define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112
- #elif defined(ARM_MULTILIB_HAS_THREAD_ID_REGISTER)
- #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48
#else
- #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 44
+ #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48
#endif
#endif
@@ -240,9 +239,7 @@ typedef struct {
#else
void *register_sp;
#endif
-#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
uint32_t thread_id;
-#endif
#ifdef ARM_MULTILIB_VFP
uint64_t register_d8;
uint64_t register_d9;
@@ -402,7 +399,7 @@ static inline void arm_interrupt_flash( uint32_t level )
#define _CPU_ISR_Flash( _isr_cookie ) \
arm_interrupt_flash( _isr_cookie )
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
#if defined(ARM_MULTILIB_ARCH_V4)
return ( level & 0x80 ) == 0;
@@ -574,14 +571,6 @@ uint32_t _CPU_Counter_frequency( void );
CPU_Counter_ticks _CPU_Counter_read( void );
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
void *_CPU_Thread_Idle_body( uintptr_t ignored );
#if defined(ARM_MULTILIB_ARCH_V4)
@@ -596,7 +585,7 @@ typedef enum {
ARM_EXCEPTION_IRQ = 6,
ARM_EXCEPTION_FIQ = 7,
MAX_EXCEPTIONS = 8,
- ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff
+ ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0x7fffffff
} Arm_symbolic_exception_name;
#endif /* defined(ARM_MULTILIB_ARCH_V4) */
diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/arm/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 01bb99cda3..0000000000
--- a/cpukit/score/cpu/arm/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
index 0ce347c86f..04d23f0ea7 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
@@ -3,11 +3,14 @@
/**
* @file
*
- * @brief CPU Port Implementation API
+ * @ingroup RTEMSScoreCPUARM
+ *
+ * @brief This header file defines implementation interfaces pertaining to the
+ * port of the executive to the ARM architecture.
*/
/*
- * Copyright (c) 2013, 2016 embedded brains GmbH
+ * Copyright (C) 2013, 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -60,6 +63,8 @@
#endif /* ARM_MULTILIB_ARCH_V4 */
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 11
+
#ifndef ASM
#ifdef __cplusplus
@@ -150,16 +155,36 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( "udf" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
+ __asm__ volatile (
+ "mcr p15, 0, %0, c13, c0, 3" : : "r" ( context->thread_id ) : "memory"
+ );
+#else
+ (void) context;
+#endif
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ return (void *) context->thread_id;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/arm/include/rtems/score/paravirt.h b/cpukit/score/cpu/arm/include/rtems/score/paravirt.h
index e3fb9009ad..4aa98499ad 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/paravirt.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/paravirt.h
@@ -3,10 +3,10 @@
/**
* @file
*
- * @brief ARM Paravirtualization Definitions
+ * @ingroup RTEMSScoreCPUARMParavirt
*
- * This include file contains definitions pertaining to paravirtualization
- * of the ARM port.
+ * @brief This header file provides definitions pertaining to
+ * paravirtualization of the ARM port.
*/
/*
diff --git a/cpukit/score/cpu/bfin/bfin-exception-frame-print.c b/cpukit/score/cpu/bfin/bfin-exception-frame-print.c
index 4828493309..d6c49f5569 100644
--- a/cpukit/score/cpu/bfin/bfin-exception-frame-print.c
+++ b/cpukit/score/cpu/bfin/bfin-exception-frame-print.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012 embedded brains GmbH & Co. KG
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpu.h b/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
index 91b1a91b07..72e6d14433 100644
--- a/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
@@ -355,7 +355,7 @@ typedef struct {
: : "d"(_level) : "R0" ); \
}
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
return level != 0;
}
@@ -605,14 +605,6 @@ uint32_t _CPU_Counter_frequency( void );
CPU_Counter_ticks _CPU_Counter_read( void );
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
/** Type that can store a 32-bit integer or a pointer. */
typedef uintptr_t CPU_Uint32ptr;
diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/bfin/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 598ee76b20..0000000000
--- a/cpukit/score/cpu/bfin/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
index 1485abd365..5a445d9420 100644
--- a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
@@ -5,7 +5,7 @@
*/
/*
- * Copyright (c) 2013 embedded brains GmbH
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -29,6 +29,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
@@ -37,28 +39,47 @@ extern "C" {
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
-RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern )
+static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
+ (void) pattern;
+
/* TODO */
}
-RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern )
+static inline void _CPU_Context_validate( uintptr_t pattern )
{
+ (void) pattern;
+
while (1) {
/* TODO */
}
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( ".word 0" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ (void) context;
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ (void) context;
+ return NULL;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/i386/cpu.c b/cpukit/score/cpu/i386/cpu.c
index e89cdebdbe..9a3b188d10 100644
--- a/cpukit/score/cpu/i386/cpu.c
+++ b/cpukit/score/cpu/i386/cpu.c
@@ -193,7 +193,7 @@ void _CPU_Context_Initialize(
the_context->esp = (void *) _stack;
if ( tls_area != NULL ) {
- tcb = (uint32_t) _TLS_TCB_after_TLS_block_initialize( tls_area );
+ tcb = (uint32_t) _TLS_Initialize_area( tls_area );
} else {
tcb = 0;
}
diff --git a/cpukit/score/cpu/i386/cpu_asm.S b/cpukit/score/cpu/i386/cpu_asm.S
index 6b114e94e1..bb5c096e72 100644
--- a/cpukit/score/cpu/i386/cpu_asm.S
+++ b/cpukit/score/cpu/i386/cpu_asm.S
@@ -67,11 +67,13 @@
.p2align 1
PUBLIC (_CPU_Context_switch)
+ PUBLIC (_CPU_Context_switch_no_return)
.set RUNCONTEXT_ARG, 4 /* save context argument */
.set HEIRCONTEXT_ARG, 8 /* restore context argument */
SYM (_CPU_Context_switch):
+SYM (_CPU_Context_switch_no_return):
movl RUNCONTEXT_ARG(esp),eax /* eax = running threads context */
GET_SELF_CPU_CONTROL edx /* edx has address for per_CPU information */
movl PER_CPU_ISR_DISPATCH_DISABLE(edx),ecx
diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpu.h b/cpukit/score/cpu/i386/include/rtems/score/cpu.h
index 1de9b7544c..a12b0f2b92 100644
--- a/cpukit/score/cpu/i386/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/i386/include/rtems/score/cpu.h
@@ -2,9 +2,9 @@
/**
* @file
- *
+ *
* @brief Intel I386 CPU Dependent Source
- *
+ *
* This include file contains information pertaining to the Intel
* i386 processor.
*/
@@ -51,7 +51,7 @@ extern "C" {
#include <rtems/score/paravirt.h>
#endif
#include <rtems/score/i386.h>
-
+
/**
* @defgroup RTEMSScoreCPUi386 i386 Specific Support
*
@@ -163,7 +163,7 @@ typedef struct {
} Context_Control;
#define _CPU_Context_Get_SP( _context ) \
- (_context)->esp
+ (uintptr_t) (_context)->esp
#ifdef RTEMS_SMP
static inline bool _CPU_Context_Get_is_executing(
@@ -428,7 +428,7 @@ extern Context_Control_fp _CPU_Null_fp_context;
#define _CPU_ISR_Set_level( _new_level ) i386_set_interrupt_level(_new_level)
#endif
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
return ( level & EFLAGS_INTR_ENABLE ) != 0;
}
@@ -572,6 +572,11 @@ void _CPU_Context_switch(
Context_Control *heir
);
+RTEMS_NO_RETURN void _CPU_Context_switch_no_return(
+ Context_Control *executing,
+ Context_Control *heir
+);
+
/*
* _CPU_Context_restore
*
@@ -651,14 +656,6 @@ uint32_t _CPU_Counter_frequency( void );
CPU_Counter_ticks _CPU_Counter_read( void );
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
/**@}**/
/** Type that can store a 32-bit integer or a pointer. */
diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/i386/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 01bb99cda3..0000000000
--- a/cpukit/score/cpu/i386/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
index 31ec0ac8bb..da38ecacf7 100644
--- a/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2013 embedded brains GmbH
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -50,6 +50,8 @@
#define CPU_INTERRUPT_FRAME_SIZE 52
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 20
+
#ifndef ASM
#ifdef __cplusplus
@@ -58,28 +60,65 @@ extern "C" {
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
-RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern )
+static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
+ (void) pattern;
+
/* TODO */
}
-RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern )
+static inline void _CPU_Context_validate( uintptr_t pattern )
{
+ (void) pattern;
+
while (1) {
/* TODO */
}
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( ".word 0" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ uint32_t tmp;
+ uint32_t cpu_index;
+
+#ifdef RTEMS_SMP
+ cpu_index = _CPU_SMP_Get_current_processor();
+#else
+ cpu_index = 0;
+#endif
+
+ __asm__ volatile (
+ "movl " RTEMS_XSTRING( I386_CONTEXT_CONTROL_GS_0_OFFSET ) "(%2), %0\n"
+ "movl %0, _Global_descriptor_table+24(,%1,8)\n"
+ "movl " RTEMS_XSTRING( I386_CONTEXT_CONTROL_GS_1_OFFSET ) "(%2), %0\n"
+ "movl %0, _Global_descriptor_table+28(,%1,8)\n"
+ "leal 24(,%1,8), %0\n"
+ "movl %0, %%gs\n"
+ : "=&r" ( tmp )
+ : "r" ( cpu_index ), "r" ( context )
+ : "memory"
+ );
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ return (void *) &context->gs;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/i386/include/rtems/score/i386.h b/cpukit/score/cpu/i386/include/rtems/score/i386.h
index 6b0ae5d6c2..7598204a64 100644
--- a/cpukit/score/cpu/i386/include/rtems/score/i386.h
+++ b/cpukit/score/cpu/i386/include/rtems/score/i386.h
@@ -223,7 +223,7 @@ void *i386_Physical_to_logical(
* @param[in] offset used with \p segment to compute physical address
* @retval physical address
*/
-RTEMS_INLINE_ROUTINE void *i386_Real_to_physical(
+static inline void *i386_Real_to_physical(
uint16_t segment,
uint16_t offset)
{
@@ -577,7 +577,7 @@ extern segment_descriptors* i386_get_gdt_entry (uint16_t sgmnt_selector);
* @param[in] gdt_entry pointer to entry from which base should be retrieved
* @retval base address from GDT entry
*/
-RTEMS_INLINE_ROUTINE void* i386_base_gdt_entry (segment_descriptors* gdt_entry)
+static inline void* i386_base_gdt_entry (segment_descriptors* gdt_entry)
{
return (void*)(gdt_entry->base_address_15_0 |
(gdt_entry->base_address_23_16<<16) |
diff --git a/cpukit/score/cpu/lm32/include/rtems/score/cpu.h b/cpukit/score/cpu/lm32/include/rtems/score/cpu.h
index 9bceb3b892..335d3407fe 100644
--- a/cpukit/score/cpu/lm32/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/lm32/include/rtems/score/cpu.h
@@ -456,7 +456,7 @@ extern Context_Control_fp _CPU_Null_fp_context;
#define _CPU_ISR_Flash( _isr_cookie ) \
lm32_flash_interrupts( _isr_cookie );
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
return ( level & 0x0001 ) != 0;
}
@@ -612,7 +612,7 @@ void _CPU_Initialize(void);
typedef void ( *CPU_ISR_raw_handler )( void );
-RTEMS_INLINE_ROUTINE void _CPU_ISR_install_raw_handler(
+static inline void _CPU_ISR_install_raw_handler(
uint32_t vector,
CPU_ISR_raw_handler new_handler,
CPU_ISR_raw_handler *old_handler
@@ -745,14 +745,6 @@ uint32_t _CPU_Counter_frequency( void );
CPU_Counter_ticks _CPU_Counter_read( void );
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
/** Type that can store a 32-bit integer or a pointer. */
typedef uintptr_t CPU_Uint32ptr;
diff --git a/cpukit/score/cpu/lm32/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/lm32/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 598ee76b20..0000000000
--- a/cpukit/score/cpu/lm32/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
index eb0c058723..70a1db1d4d 100644
--- a/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
@@ -5,7 +5,7 @@
*/
/*
- * Copyright (c) 2013 embedded brains GmbH
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -28,6 +28,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
@@ -36,28 +38,47 @@ extern "C" {
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
-RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern )
+static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
+ (void) pattern;
+
/* TODO */
}
-RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern )
+static inline void _CPU_Context_validate( uintptr_t pattern )
{
+ (void) pattern;
+
while (1) {
/* TODO */
}
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( ".word 0" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ (void) context;
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ (void) context;
+ return NULL;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/lm32/lm32-exception-frame-print.c b/cpukit/score/cpu/lm32/lm32-exception-frame-print.c
index 4828493309..d6c49f5569 100644
--- a/cpukit/score/cpu/lm32/lm32-exception-frame-print.c
+++ b/cpukit/score/cpu/lm32/lm32-exception-frame-print.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012 embedded brains GmbH & Co. KG
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
diff --git a/cpukit/score/cpu/m68k/__m68k_read_tp.c b/cpukit/score/cpu/m68k/__m68k_read_tp.c
index e15ac3fed3..8c73c96339 100644
--- a/cpukit/score/cpu/m68k/__m68k_read_tp.c
+++ b/cpukit/score/cpu/m68k/__m68k_read_tp.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2014-2015 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2014, 2015 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -37,9 +37,7 @@ void __m68k_read_tp(void);
void __m68k_read_tp(void)
{
const Thread_Control *executing = _Thread_Get_executing();
- void *tp = (char *) executing->Start.tls_area +
- _TLS_Get_thread_control_block_area_size((uintptr_t) _TLS_Alignment)
- + 0x7000;
+ void *tp = executing->Registers.thread_pointer;
__asm__ volatile (
"move.l %0, %%a0"
diff --git a/cpukit/score/cpu/m68k/cpu.c b/cpukit/score/cpu/m68k/cpu.c
index 9f6fb9223e..44dc06cc91 100644
--- a/cpukit/score/cpu/m68k/cpu.c
+++ b/cpukit/score/cpu/m68k/cpu.c
@@ -279,6 +279,9 @@ void _CPU_Context_Initialize(
#endif
if ( tls_area != NULL ) {
- _TLS_TCB_before_TLS_block_initialize( tls_area );
+ the_context->thread_pointer =
+ (char *) _TLS_Initialize_area( tls_area ) + 0x7000;
+ } else {
+ the_context->thread_pointer = NULL;
}
}
diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpu.h b/cpukit/score/cpu/m68k/include/rtems/score/cpu.h
index e72b735501..ae3194b9bb 100644
--- a/cpukit/score/cpu/m68k/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m68k/include/rtems/score/cpu.h
@@ -145,6 +145,7 @@ typedef struct {
#if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
uint8_t fpu_dis;
#endif
+ void *thread_pointer;
} Context_Control;
#define _CPU_Context_Get_SP( _context ) \
@@ -384,7 +385,7 @@ extern void* _VBR;
#define _CPU_ISR_Flash( _level ) \
m68k_flash_interrupts( _level )
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
return ( level & 0x0700 ) == 0;
}
@@ -621,14 +622,6 @@ uint32_t _CPU_Counter_frequency( void );
CPU_Counter_ticks _CPU_Counter_read( void );
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
#if (M68K_HAS_FPSP_PACKAGE == 1)
/*
* Hooks for the Floating Point Support Package (FPSP) provided by Motorola
diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/m68k/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 01bb99cda3..0000000000
--- a/cpukit/score/cpu/m68k/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
index e3b61efd9f..521e9fc4c2 100644
--- a/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2013 embedded brains GmbH
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -48,6 +48,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
@@ -56,28 +58,50 @@ extern "C" {
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
-RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern )
+static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
+ (void) pattern;
+
/* TODO */
}
-RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern )
+static inline void _CPU_Context_validate( uintptr_t pattern )
{
+ (void) pattern;
+
while (1) {
/* TODO */
}
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( "illegal" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ /*
+ * There is nothing to do since the thread-local storage area is obtained by
+ * calling __m68k_read_tp().
+ */
+ (void) context;
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ return (void *) context->thread_pointer;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/m68k/m68k-exception-frame-print.c b/cpukit/score/cpu/m68k/m68k-exception-frame-print.c
index cd87c9ef34..ba629fd073 100644
--- a/cpukit/score/cpu/m68k/m68k-exception-frame-print.c
+++ b/cpukit/score/cpu/m68k/m68k-exception-frame-print.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/microblaze/__tls_get_addr.c b/cpukit/score/cpu/microblaze/__tls_get_addr.c
index e779a63488..b7e7890013 100644
--- a/cpukit/score/cpu/microblaze/__tls_get_addr.c
+++ b/cpukit/score/cpu/microblaze/__tls_get_addr.c
@@ -46,9 +46,11 @@ void *__tls_get_addr( const TLS_Index *ti );
void *__tls_get_addr( const TLS_Index *ti )
{
- const Thread_Control *executing = _Thread_Get_executing();
- void *tls_block = (char *) executing->Start.tls_area
- + _TLS_Get_thread_control_block_area_size( (uintptr_t) _TLS_Alignment );
+ const Thread_Control *executing;
- return (char *) tls_block + ti->offset;
+ (void) ti;
+
+ executing = _Thread_Get_executing();
+
+ return executing->Registers.thread_pointer;
}
diff --git a/cpukit/score/cpu/microblaze/cpu.c b/cpukit/score/cpu/microblaze/cpu.c
index 1e829a4714..823825d2b1 100644
--- a/cpukit/score/cpu/microblaze/cpu.c
+++ b/cpukit/score/cpu/microblaze/cpu.c
@@ -73,7 +73,7 @@ void _CPU_Context_Initialize(
context->rmsr = msr;
if ( tls_area != NULL ) {
- _TLS_TCB_at_area_begin_initialize( tls_area );
+ context->thread_pointer = _TLS_Initialize_area( tls_area );
}
}
diff --git a/cpukit/score/cpu/microblaze/include/machine/elf_machdep.h b/cpukit/score/cpu/microblaze/include/machine/elf_machdep.h
new file mode 100644
index 0000000000..e6d661c596
--- /dev/null
+++ b/cpukit/score/cpu/microblaze/include/machine/elf_machdep.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2023 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MICROBLAZE_ELF_MACHDEP_H_
+#define _MICROBLAZE_ELF_MACHDEP_H_
+
+#define ELF64_MACHDEP_ID EM_MICROBLAZE
+#define ELF32_MACHDEP_ID EM_MICROBLAZE
+
+#define ELF64_MACHDEP_ENDIANNESS ELFDATA2LSB
+#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB
+
+#define ELF32_MACHDEP_ID_CASES \
+ case EM_MICROBLAZE: \
+ break;
+
+#define ELF64_MACHDEP_ID_CASES \
+ case EM_MICROBLAZE: \
+ break;
+
+#define KERN_ELFSIZE 32
+#define ARCH_ELFSIZE 32 /* MD native binary size */
+
+/* Processor specific relocation types */
+
+#define R_MICROBLAZE_NONE 0
+#define R_MICROBLAZE_32 1
+#define R_MICROBLAZE_32_PCREL 2
+#define R_MICROBLAZE_64_PCREL 3
+#define R_MICROBLAZE_32_PCREL_LO 4
+#define R_MICROBLAZE_64 5
+#define R_MICROBLAZE_32_LO 6
+#define R_MICROBLAZE_SRO32 7
+#define R_MICROBLAZE_SRW32 8
+#define R_MICROBLAZE_64_NONE 9
+#define R_MICROBLAZE_32_SYM_OP_SYM 10
+#define R_MICROBLAZE_GNU_VTINHERIT 11
+#define R_MICROBLAZE_GNU_VTENTRY 12
+#define R_MICROBLAZE_GOTPC_64 13
+#define R_MICROBLAZE_GOT_64 14
+#define R_MICROBLAZE_PLT_64 15
+#define R_MICROBLAZE_REL 16
+#define R_MICROBLAZE_JUMP_SLOT 17
+#define R_MICROBLAZE_GLOB_DAT 18
+#define R_MICROBLAZE_GOTOFF_64 19
+#define R_MICROBLAZE_GOTOFF_32 20
+#define R_MICROBLAZE_COPY 21
+#define R_MICROBLAZE_TLS 22
+#define R_MICROBLAZE_TLSGD 23
+#define R_MICROBLAZE_TLSLD 24
+#define R_MICROBLAZE_TLSDTPMOD32 25
+#define R_MICROBLAZE_TLSDTPREL32 26
+#define R_MICROBLAZE_TLSDTPREL64 27
+#define R_MICROBLAZE_TLSGOTTPREL32 28
+#define R_MICROBLAZE_TLSTPREL32 29
+
+#define R_TYPE( name ) R_MICROBLAZE_##name
+
+#endif /* _MICROBLAZE_ELF_MACHDEP_H_ */
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
index a486c3d2b3..3d865732d6 100644
--- a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
@@ -137,6 +137,7 @@ typedef struct {
uint32_t r30;
uint32_t r31;
uint32_t rmsr;
+ void *thread_pointer;
} Context_Control;
/**
@@ -264,7 +265,7 @@ void _CPU_ISR_Set_level( uint32_t level );
uint32_t _CPU_ISR_Get_level( void );
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
return ( level & MICROBLAZE_MSR_IE ) != 0;
}
@@ -450,14 +451,6 @@ uint32_t _CPU_Counter_frequency( void );
CPU_Counter_ticks _CPU_Counter_read( void );
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
void *_CPU_Thread_Idle_body( uintptr_t ignored );
void bsp_interrupt_dispatch( uint32_t source );
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 6dc769b95a..0000000000
--- a/cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/**
- * @file
- *
- * @ingroup RTEMSScoreCPU
- *
- * @brief MicroBlaze atomic support
- */
-
-/*
- * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
index 0573759d52..760ebbfbbb 100644
--- a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
@@ -49,8 +49,11 @@
*/
#define CPU_PER_CPU_CONTROL_SIZE 0
+
#define CPU_INTERRUPT_FRAME_SIZE 56
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#define MICROBLAZE_INTERRUPT_FRAME_R3 0
#define MICROBLAZE_INTERRUPT_FRAME_R4 4
#define MICROBLAZE_INTERRUPT_FRAME_R5 8
@@ -76,16 +79,34 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( ".word 0x0" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ /*
+ * There is nothing to do since the thread-local storage area is obtained by
+ * calling __tls_get_addr().
+ */
+ (void) context;
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ return (void *) context->thread_pointer;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/mips/include/rtems/score/cpu.h b/cpukit/score/cpu/mips/include/rtems/score/cpu.h
index fdb7ee4d73..447a384c88 100644
--- a/cpukit/score/cpu/mips/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/mips/include/rtems/score/cpu.h
@@ -602,7 +602,7 @@ uint32_t mips_interrupt_mask( void );
_xlevel = _scratch2; \
} while(0)
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
return ( level & SR_INTERRUPT_ENABLE_BITS ) != 0;
}
@@ -835,14 +835,6 @@ uint32_t _CPU_Counter_frequency( void );
CPU_Counter_ticks _CPU_Counter_read( void );
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
/** Type that can store a 32-bit integer or a pointer. */
typedef uintptr_t CPU_Uint32ptr;
diff --git a/cpukit/score/cpu/mips/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/mips/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 01bb99cda3..0000000000
--- a/cpukit/score/cpu/mips/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h
index 0568134351..98ed1c492f 100644
--- a/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2013 embedded brains GmbH
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -48,6 +48,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
@@ -56,28 +58,47 @@ extern "C" {
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
-RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern )
+static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
+ (void) pattern;
+
/* TODO */
}
-RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern )
+static inline void _CPU_Context_validate( uintptr_t pattern )
{
+ (void) pattern;
+
while (1) {
/* TODO */
}
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( ".word -1" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ (void) context;
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ (void) context;
+ return NULL;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/moxie/include/rtems/score/cpu.h b/cpukit/score/cpu/moxie/include/rtems/score/cpu.h
index 18329a5b3d..cc1900a852 100644
--- a/cpukit/score/cpu/moxie/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/moxie/include/rtems/score/cpu.h
@@ -228,7 +228,7 @@ typedef struct {
*
* XXX
*/
-#define CPU_STACK_MINIMUM_SIZE (1536)
+#define CPU_STACK_MINIMUM_SIZE (2048)
/**
* Size of a pointer.
@@ -317,7 +317,7 @@ typedef struct {
_CPU_ISR_Disable( _isr_cookie ); \
} while (0)
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
return true;
}
@@ -532,14 +532,6 @@ uint32_t _CPU_Counter_frequency( void );
CPU_Counter_ticks _CPU_Counter_read( void );
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
/** Type that can store a 32-bit integer or a pointer. */
typedef uintptr_t CPU_Uint32ptr;
diff --git a/cpukit/score/cpu/moxie/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/moxie/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 01bb99cda3..0000000000
--- a/cpukit/score/cpu/moxie/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h
index 038a1326cc..44c70cc56d 100644
--- a/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2013 embedded brains GmbH
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -48,6 +48,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
@@ -56,28 +58,47 @@ extern "C" {
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
-RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern )
+static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
+ (void) pattern;
+
/* TODO */
}
-RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern )
+static inline void _CPU_Context_validate( uintptr_t pattern )
{
+ (void) pattern;
+
while (1) {
/* TODO */
}
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( ".word 0" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ (void) context;
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ (void) context;
+ return NULL;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/nios2/include/rtems/score/cpu.h b/cpukit/score/cpu/nios2/include/rtems/score/cpu.h
index d7c484f9bc..a58e7bca06 100644
--- a/cpukit/score/cpu/nios2/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/nios2/include/rtems/score/cpu.h
@@ -9,7 +9,7 @@
*/
/*
- * Copyright (c) 2011 embedded brains GmbH
+ * Copyright (c) 2011 embedded brains GmbH & Co. KG
*
* Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
*
@@ -353,14 +353,6 @@ uint32_t _CPU_Counter_frequency( void );
CPU_Counter_ticks _CPU_Counter_read( void );
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
/** Type that can store a 32-bit integer or a pointer. */
typedef uintptr_t CPU_Uint32ptr;
diff --git a/cpukit/score/cpu/nios2/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/nios2/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 01bb99cda3..0000000000
--- a/cpukit/score/cpu/nios2/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h
index 215df68f67..3c9c6734ec 100644
--- a/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2013 embedded brains GmbH
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -48,6 +48,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
@@ -60,16 +62,35 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( ".word 0" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ register uint32_t r23 __asm__( "r23" );
+
+ r23 = context->r23;
+
+ /* Make sure that the register assignment is not optimized away */
+ __asm__ volatile ( "" : : "r" ( r23 ) );
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ return (void *) context->r23;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/nios2/include/rtems/score/nios2-utility.h b/cpukit/score/cpu/nios2/include/rtems/score/nios2-utility.h
index 1f230937eb..811c1affe0 100644
--- a/cpukit/score/cpu/nios2/include/rtems/score/nios2-utility.h
+++ b/cpukit/score/cpu/nios2/include/rtems/score/nios2-utility.h
@@ -6,7 +6,7 @@
* @brief NIOS II Utility
*/
/*
- * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2011 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/nios2/nios2-context-initialize.c b/cpukit/score/cpu/nios2/nios2-context-initialize.c
index fe458cc2ca..dc96855fbf 100644
--- a/cpukit/score/cpu/nios2/nios2-context-initialize.c
+++ b/cpukit/score/cpu/nios2/nios2-context-initialize.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2011, 2021 embedded brains GmbH
+ * Copyright (C) 2011, 2021 embedded brains GmbH & Co. KG
*
* Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
*
@@ -90,9 +90,6 @@ void _CPU_Context_Initialize(
}
if ( tls_area != NULL ) {
- context->r23 = (uintptr_t) tls_area +
- _TLS_Get_thread_control_block_area_size( (uintptr_t) _TLS_Alignment ) +
- 0x7000;
- _TLS_TCB_before_TLS_block_initialize( tls_area );
+ context->r23 = (uintptr_t) _TLS_Initialize_area( tls_area ) + 0x7000;
}
}
diff --git a/cpukit/score/cpu/nios2/nios2-context-switch.S b/cpukit/score/cpu/nios2/nios2-context-switch.S
index 87f6539076..687d8301c6 100644
--- a/cpukit/score/cpu/nios2/nios2-context-switch.S
+++ b/cpukit/score/cpu/nios2/nios2-context-switch.S
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2011 embedded brains GmbH
+ * Copyright (c) 2011 embedded brains GmbH & Co. KG
*
* Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
*
diff --git a/cpukit/score/cpu/nios2/nios2-context-validate.S b/cpukit/score/cpu/nios2/nios2-context-validate.S
index a9d6ead9ba..a7fb6e646d 100644
--- a/cpukit/score/cpu/nios2/nios2-context-validate.S
+++ b/cpukit/score/cpu/nios2/nios2-context-validate.S
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/nios2/nios2-context-volatile-clobber.S b/cpukit/score/cpu/nios2/nios2-context-volatile-clobber.S
index 28a38d5392..a5e181c3df 100644
--- a/cpukit/score/cpu/nios2/nios2-context-volatile-clobber.S
+++ b/cpukit/score/cpu/nios2/nios2-context-volatile-clobber.S
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/nios2/nios2-eic-il-low-level.S b/cpukit/score/cpu/nios2/nios2-eic-il-low-level.S
index 1b2ecb0c98..660c0add39 100644
--- a/cpukit/score/cpu/nios2/nios2-eic-il-low-level.S
+++ b/cpukit/score/cpu/nios2/nios2-eic-il-low-level.S
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2011-2015 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2011, 2015 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/nios2/nios2-exception-frame-print.c b/cpukit/score/cpu/nios2/nios2-exception-frame-print.c
index cd87c9ef34..ba629fd073 100644
--- a/cpukit/score/cpu/nios2/nios2-exception-frame-print.c
+++ b/cpukit/score/cpu/nios2/nios2-exception-frame-print.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/nios2/nios2-fatal-halt.c b/cpukit/score/cpu/nios2/nios2-fatal-halt.c
index ab27de4b34..3fa43d630d 100644
--- a/cpukit/score/cpu/nios2/nios2-fatal-halt.c
+++ b/cpukit/score/cpu/nios2/nios2-fatal-halt.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2011 embedded brains GmbH
+ * Copyright (c) 2011 embedded brains GmbH & Co. KG
*
* Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
*
diff --git a/cpukit/score/cpu/nios2/nios2-iic-irq.c b/cpukit/score/cpu/nios2/nios2-iic-irq.c
index 561ba3865e..8215e16a4c 100644
--- a/cpukit/score/cpu/nios2/nios2-iic-irq.c
+++ b/cpukit/score/cpu/nios2/nios2-iic-irq.c
@@ -60,7 +60,7 @@ void __Exception_Handler(CPU_Exception_frame *efr);
register unsigned long *stack_ptr __asm__ ("sp");
-RTEMS_INLINE_ROUTINE void __IIC_Handler(void)
+static inline void __IIC_Handler(void)
{
uint32_t active;
uint32_t mask;
diff --git a/cpukit/score/cpu/nios2/nios2-isr-get-level.c b/cpukit/score/cpu/nios2/nios2-isr-get-level.c
index 4879f60fff..7b15ac93f5 100644
--- a/cpukit/score/cpu/nios2/nios2-isr-get-level.c
+++ b/cpukit/score/cpu/nios2/nios2-isr-get-level.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2011, 2016 embedded brains GmbH
+ * Copyright (C) 2011, 2016 embedded brains GmbH & Co. KG
*
* Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
*
diff --git a/cpukit/score/cpu/nios2/nios2-isr-is-in-progress.c b/cpukit/score/cpu/nios2/nios2-isr-is-in-progress.c
index d6610e8485..5822ebf1f8 100644
--- a/cpukit/score/cpu/nios2/nios2-isr-is-in-progress.c
+++ b/cpukit/score/cpu/nios2/nios2-isr-is-in-progress.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2011 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/nios2/nios2-isr-set-level.c b/cpukit/score/cpu/nios2/nios2-isr-set-level.c
index c18def01e4..6211546585 100644
--- a/cpukit/score/cpu/nios2/nios2-isr-set-level.c
+++ b/cpukit/score/cpu/nios2/nios2-isr-set-level.c
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2011 embedded brains GmbH
+ * Copyright (c) 2011 embedded brains GmbH & Co. KG
*
* Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
*
diff --git a/cpukit/score/cpu/nios2/nios2-mpu-add-region.c b/cpukit/score/cpu/nios2/nios2-mpu-add-region.c
index 9b4e46ee83..dd04aa0a97 100644
--- a/cpukit/score/cpu/nios2/nios2-mpu-add-region.c
+++ b/cpukit/score/cpu/nios2/nios2-mpu-add-region.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2011 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/nios2/nios2-mpu-configuration.c b/cpukit/score/cpu/nios2/nios2-mpu-configuration.c
index ea5e25b437..640bbb1223 100644
--- a/cpukit/score/cpu/nios2/nios2-mpu-configuration.c
+++ b/cpukit/score/cpu/nios2/nios2-mpu-configuration.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2011 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/nios2/nios2-mpu-descriptor.c b/cpukit/score/cpu/nios2/nios2-mpu-descriptor.c
index 284e609ac5..9076a065d9 100644
--- a/cpukit/score/cpu/nios2/nios2-mpu-descriptor.c
+++ b/cpukit/score/cpu/nios2/nios2-mpu-descriptor.c
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2011 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c b/cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c
index 7c46ddf2fa..f1ed73b495 100644
--- a/cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c
+++ b/cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2011 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/nios2/nios2-mpu-reset.c b/cpukit/score/cpu/nios2/nios2-mpu-reset.c
index 7e2a8ed3da..85dbfb338b 100644
--- a/cpukit/score/cpu/nios2/nios2-mpu-reset.c
+++ b/cpukit/score/cpu/nios2/nios2-mpu-reset.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2011 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/nios2/nios2-thread-dispatch-disabled.c b/cpukit/score/cpu/nios2/nios2-thread-dispatch-disabled.c
index a9ce6cdbba..56efc0e10d 100644
--- a/cpukit/score/cpu/nios2/nios2-thread-dispatch-disabled.c
+++ b/cpukit/score/cpu/nios2/nios2-thread-dispatch-disabled.c
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2011 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/no_cpu/cpucounterfrequency.c b/cpukit/score/cpu/no_cpu/cpucounterfrequency.c
index fcc4cdbc33..96a4078889 100644
--- a/cpukit/score/cpu/no_cpu/cpucounterfrequency.c
+++ b/cpukit/score/cpu/no_cpu/cpucounterfrequency.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2018 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2018 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/no_cpu/cpucounterread.c b/cpukit/score/cpu/no_cpu/cpucounterread.c
index f27784f9a7..f4e6e77fc1 100644
--- a/cpukit/score/cpu/no_cpu/cpucounterread.c
+++ b/cpukit/score/cpu/no_cpu/cpucounterread.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2014 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2014 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/no_cpu/cpuidle.c b/cpukit/score/cpu/no_cpu/cpuidle.c
index 85ca01b7ca..dbaf109905 100644
--- a/cpukit/score/cpu/no_cpu/cpuidle.c
+++ b/cpukit/score/cpu/no_cpu/cpuidle.c
@@ -1,7 +1,16 @@
/* SPDX-License-Identifier: BSD-2-Clause */
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPU
+ *
+ * @brief This source file contains the implementation of the
+ * _CPU_Thread_Idle_body().
+ */
+
/*
- * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -33,6 +42,13 @@
void *_CPU_Thread_Idle_body( uintptr_t ignored )
{
+ /*
+ * This is a workaround for:
+ *
+ * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108658
+ */
+ __asm__ volatile ("");
+
while ( true ) {
/* Do nothing */
}
diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
index 5403cc8a10..9ef6f43eb9 100644
--- a/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
@@ -554,7 +554,8 @@ extern Context_Control_fp _CPU_Null_fp_context;
* @addtogroup RTEMSScoreCPUExampleContext
*
* Should be large enough to run all RTEMS tests. This ensures
- * that a "reasonable" small application should not have any problems.
+ * that a "reasonable" small application should not have any problems. The
+ * size shall be a power of two.
*
* Port Specific Information:
*
@@ -695,7 +696,7 @@ extern Context_Control_fp _CPU_Null_fp_context;
* @retval true Interrupts are enabled in the ISR level.
* @retval false Otherwise.
*/
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
return false;
}
@@ -1293,44 +1294,27 @@ static inline uint32_t CPU_swap_u32(
typedef uint32_t CPU_Counter_ticks;
/**
- * @brief Returns the current CPU counter frequency in Hz.
+ * @brief Gets the current CPU counter frequency in Hz.
*
- * @return The current CPU counter frequency in Hz.
+ * @return Returns the current CPU counter frequency in Hz.
*/
uint32_t _CPU_Counter_frequency( void );
/**
- * @brief Returns the current CPU counter value.
+ * @brief Gets the current CPU counter value.
*
- * A CPU counter is some free-running counter. It ticks usually with a
- * frequency close to the CPU or system bus clock. The board support package
- * must ensure that this function works before the RTEMS initialization.
- * Otherwise invalid profiling statistics will be gathered.
+ * A CPU counter should be some monotonically increasing free-running counter.
+ * It ticks usually with a frequency close to the CPU or system bus clock. The
+ * counter should not be affected by power saving states so that it can be used
+ * for timestamps. The CPU counter should be initialized at the
+ * RTEMS_SYSINIT_CPU_COUNTER initialization step if necessary. If
+ * RTEMS_PROFILING is enabled, the CPU counter may have to work very early in
+ * the system initialization to avoid invalid profiling statistics.
*
- * @return The current CPU counter value.
+ * @return Returns the current CPU counter value.
*/
CPU_Counter_ticks _CPU_Counter_read( void );
-/**
- * @brief Returns the difference between the second and first CPU counter
- * value.
- *
- * This operation may be carried out as a modulo operation depending on the
- * range of the CPU counter device.
- *
- * @param[in] second The second CPU counter value.
- * @param[in] first The first CPU counter value.
- *
- * @return Returns second minus first modulo counter period.
- */
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
#ifdef RTEMS_SMP
/**
* @brief Performs CPU specific SMP initialization in the context of the boot
diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
index 6f4abfcfc3..61f1ab7ba5 100644
--- a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2013, 2016 embedded brains GmbH
+ * Copyright (C) 2013, 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -54,6 +54,24 @@
*/
#define CPU_PER_CPU_CONTROL_SIZE 0
+/**
+ * @brief Defines the thread-local storage (TLS) variant.
+ *
+ * Use one of the following values:
+ *
+ * 10: The architecture uses Variant I and the TLS offsets emitted by the
+ * linker neglect the TCB (examples: nios2, m68k, microblaze, powerpc,
+ * riscv). The thread pointer directly references the thread-local data
+ * area.
+ *
+ * 11: The architecture uses Variant I and the TLS offsets emitted by the
+ * linker take the TCB into account (examples: arm, aarch64).
+ * The thread pointer references the TCB.
+ *
+ * 20: The architecture uses Variant II (examples: i386, sparc).
+ */
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
@@ -151,7 +169,7 @@ void _CPU_Context_validate( uintptr_t pattern );
*
* This function is used only in test sptests/spfatal26.
*/
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( ".word 0" );
}
@@ -161,11 +179,44 @@ RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
*
* This function is used only in test sptests/spcache01.
*/
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+/**
+ * @brief Uses the thread-local storage area of the context.
+ *
+ * Some architectures may use dedicated registers to reference the thread-local
+ * storage area of the associated thread. This function should set these
+ * registers to the values defined by the specified processor context.
+ *
+ * @param context is the processor context defining the thread-local storage
+ * area to use.
+ */
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ (void) context;
+}
+
+/**
+ * @brief Gets the thread pointer of the context.
+ *
+ * The thread pointer is used to get the address of thread-local storage
+ * objects associated with a thread.
+ *
+ * @param context is the processor context containing the thread pointer.
+ */
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ (void) context;
+ return NULL;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h
index 83d46010ba..ce1aa301b3 100644
--- a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h
@@ -316,7 +316,7 @@ static inline void or1k_interrupt_enable(uint32_t level)
_OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \
} while(0)
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
return ( level & CPU_OR1K_SPR_SR ) != 0;
}
@@ -468,7 +468,7 @@ void _CPU_ISR_install_raw_handler(
typedef void ( *CPU_ISR_handler )( uint32_t );
-RTEMS_INLINE_ROUTINE void _CPU_ISR_install_vector(
+static inline void _CPU_ISR_install_vector(
uint32_t vector,
CPU_ISR_handler new_handler,
CPU_ISR_handler *old_handler
@@ -578,14 +578,6 @@ uint32_t _CPU_Counter_frequency( void );
CPU_Counter_ticks _CPU_Counter_read( void );
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
/** Type that can store a 32-bit integer or a pointer. */
typedef uintptr_t CPU_Uint32ptr;
diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/or1k/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 01bb99cda3..0000000000
--- a/cpukit/score/cpu/or1k/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h
index 37cd1db436..9b58b1b77a 100644
--- a/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2013 embedded brains GmbH
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -48,6 +48,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
@@ -60,16 +62,31 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( ".word 0" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "l.nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ (void) context;
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ (void) context;
+ return NULL;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h b/cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h
index c7618c9355..58db24fbbd 100644
--- a/cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h
+++ b/cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h
@@ -345,7 +345,7 @@ static inline uint32_t _OR1K_mfspr(uint32_t reg)
{
uint32_t spr_value;
- asm volatile (
+ __asm__ volatile (
"l.mfspr %0, %1, 0;\n\t"
: "=r" (spr_value) : "r" (reg));
@@ -354,7 +354,7 @@ static inline uint32_t _OR1K_mfspr(uint32_t reg)
static inline void _OR1K_mtspr(uint32_t reg, uint32_t value)
{
- asm volatile (
+ __asm__ volatile (
"l.mtspr %1, %0, 0;\n\t"
:: "r" (value), "r" (reg)
);
@@ -386,12 +386,12 @@ static inline void _OR1K_mtspr(uint32_t reg, uint32_t value)
static inline void _OR1K_Sync_mem( void )
{
- asm volatile("l.msync");
+ __asm__ volatile("l.msync");
}
static inline void _OR1K_Sync_pipeline( void )
{
- asm volatile("l.psync");
+ __asm__ volatile("l.psync");
}
/**
@@ -402,7 +402,7 @@ static inline void _OR1K_Sync_pipeline( void )
*
*/
#define _OR1KSIM_CPU_Halt() \
- asm volatile ("l.nop 0xc")
+ __asm__ volatile ("l.nop 0xc")
#ifdef __cplusplus
}
diff --git a/cpukit/score/cpu/powerpc/cpu.c b/cpukit/score/cpu/powerpc/cpu.c
index 6147d7be74..7c90ac28dc 100644
--- a/cpukit/score/cpu/powerpc/cpu.c
+++ b/cpukit/score/cpu/powerpc/cpu.c
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (C) 2009, 2017 embedded brains GmbH.
+ * Copyright (C) 2009, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -79,8 +79,10 @@ PPC_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE);
#endif
#ifdef PPC_MULTILIB_ALTIVEC
+ PPC_ASSERT_OFFSET(vrsave, VRSAVE);
+ PPC_ASSERT_OFFSET(vscr, VSCR);
RTEMS_STATIC_ASSERT(
- PPC_CONTEXT_OFFSET_V20 % 16 == 0,
+ PPC_CONTEXT_OFFSET_V20 % PPC_DEFAULT_CACHE_LINE_SIZE == 0,
ppc_context_altivec
);
PPC_ASSERT_OFFSET(v20, V20);
@@ -95,7 +97,6 @@ PPC_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE);
PPC_ASSERT_OFFSET(v29, V29);
PPC_ASSERT_OFFSET(v30, V30);
PPC_ASSERT_OFFSET(v31, V31);
- PPC_ASSERT_OFFSET(vrsave, VRSAVE);
#endif
#ifdef PPC_MULTILIB_FPU
@@ -357,4 +358,5 @@ void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
: "r" (source), "r" (error)
: "memory"
);
+ RTEMS_UNREACHABLE();
}
diff --git a/cpukit/score/cpu/powerpc/include/rtems/asm.h b/cpukit/score/cpu/powerpc/include/rtems/asm.h
index 27af64e724..94f54245b4 100644
--- a/cpukit/score/cpu/powerpc/include/rtems/asm.h
+++ b/cpukit/score/cpu/powerpc/include/rtems/asm.h
@@ -75,23 +75,21 @@
#define __PROC_LABEL_PREFIX__ __USER_LABEL_PREFIX__
#endif
-#include <rtems/concat.h>
-
/* Use the right prefix for global labels. */
-#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
+#define SYM(x) RTEMS_XCONCAT (__USER_LABEL_PREFIX__, x)
/* Use the right prefix for procedure labels. */
-#define PROC(x) CONCAT1 (__PROC_LABEL_PREFIX__, x)
+#define PROC(x) RTEMS_XCONCAT (__PROC_LABEL_PREFIX__, x)
/* Use the right prefix for registers. */
-#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
+#define REG(x) RTEMS_XCONCAT (__REGISTER_PREFIX__, x)
/* Use the right prefix for floating point registers. */
-#define FREG(x) CONCAT1 (__FLOAT_REGISTER_PREFIX__, x)
+#define FREG(x) RTEMS_XCONCAT (__FLOAT_REGISTER_PREFIX__, x)
/*
* define macros for all of the registers on this CPU
diff --git a/cpukit/score/cpu/powerpc/include/rtems/powerpc/registers.h b/cpukit/score/cpu/powerpc/include/rtems/powerpc/registers.h
index b651261493..271dcc36af 100644
--- a/cpukit/score/cpu/powerpc/include/rtems/powerpc/registers.h
+++ b/cpukit/score/cpu/powerpc/include/rtems/powerpc/registers.h
@@ -541,8 +541,8 @@ lidate */
#define FSL_EIS_MAS0 624
#define FSL_EIS_MAS0_TLBSEL (1 << (63 - 35))
-#define FSL_EIS_MAS0_ESEL(n) ((0xf & (n)) << (63 - 47))
-#define FSL_EIS_MAS0_ESEL_GET(m) (((m) >> (63 - 47)) & 0xf)
+#define FSL_EIS_MAS0_ESEL(n) ((0xfff & (n)) << (63 - 47))
+#define FSL_EIS_MAS0_ESEL_GET(m) (((m) >> (63 - 47)) & 0xfff)
#define FSL_EIS_MAS0_NV (1 << (63 - 63))
#define FSL_EIS_MAS1 625
diff --git a/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h
index 42900aeb1d..6f2fe491e9 100644
--- a/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h
@@ -29,7 +29,7 @@
*
* Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL).
*
- * Copyright (c) 2010, 2017 embedded brains GmbH.
+ * Copyright (C) 2010, 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -246,6 +246,13 @@ typedef struct {
uint32_t isr_dispatch_disable;
uint32_t reserved_for_alignment;
#if defined(PPC_MULTILIB_ALTIVEC)
+ #if !defined(__powerpc64__)
+ uint32_t reserved_for_alignment_2[4];
+ #endif
+ uint32_t vrsave;
+ uint32_t reserved_for_alignment_3[2];
+ /* This field must take stvewx/lvewx requirements into account */
+ uint32_t vscr;
uint8_t v20[16];
uint8_t v21[16];
uint8_t v22[16];
@@ -258,7 +265,6 @@ typedef struct {
uint8_t v29[16];
uint8_t v30[16];
uint8_t v31[16];
- uint32_t vrsave;
#elif defined(__ALTIVEC__)
/*
* 12 non-volatile vector registers, cache-aligned area for vscr/vrsave
@@ -373,8 +379,16 @@ static inline ppc_context *ppc_get_context( const Context_Control *context )
#define PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE PPC_CONTEXT_GPR_OFFSET( 32 )
#ifdef PPC_MULTILIB_ALTIVEC
+ #ifdef __powerpc64__
+ #define PPC_CONTEXT_OFFSET_VRSAVE \
+ ( PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8 )
+ #else
+ #define PPC_CONTEXT_OFFSET_VRSAVE \
+ ( PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 24 )
+ #endif
+ #define PPC_CONTEXT_OFFSET_VSCR ( PPC_CONTEXT_OFFSET_VRSAVE + 12 )
#define PPC_CONTEXT_OFFSET_V( v ) \
- ( ( ( v ) - 20 ) * 16 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8)
+ ( ( ( v ) - 20 ) * 16 + PPC_CONTEXT_OFFSET_VRSAVE + 16)
#define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 )
#define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 )
#define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 )
@@ -387,9 +401,8 @@ static inline ppc_context *ppc_get_context( const Context_Control *context )
#define PPC_CONTEXT_OFFSET_V29 PPC_CONTEXT_OFFSET_V( 29 )
#define PPC_CONTEXT_OFFSET_V30 PPC_CONTEXT_OFFSET_V( 30 )
#define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 )
- #define PPC_CONTEXT_OFFSET_VRSAVE PPC_CONTEXT_OFFSET_V( 32 )
#define PPC_CONTEXT_OFFSET_F( f ) \
- ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_VRSAVE + 8 )
+ ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_V( 32 ) )
#else
#define PPC_CONTEXT_OFFSET_F( f ) \
( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8 )
@@ -419,7 +432,7 @@ static inline ppc_context *ppc_get_context( const Context_Control *context )
#if defined(PPC_MULTILIB_FPU)
#define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_F( 32 )
#elif defined(PPC_MULTILIB_ALTIVEC)
- #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_OFFSET_VRSAVE + 4)
+ #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_V( 33 )
#elif defined(__ALTIVEC__)
#define PPC_CONTEXT_VOLATILE_SIZE \
(PPC_CONTEXT_GPR_OFFSET( 32 ) + 8 \
@@ -436,8 +449,8 @@ static inline ppc_context *ppc_get_context( const Context_Control *context )
#endif
#ifndef ASM
-typedef struct {
#if (PPC_HAS_FPU == 1)
+typedef struct {
/* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
* procedure calls. However, this would mean that the interrupt
* frame had to hold f0-f13, and the fpscr. And as the majority
@@ -451,9 +464,8 @@ typedef struct {
float f[32];
uint32_t fpscr;
#endif
-#endif /* (PPC_HAS_FPU == 1) */
} Context_Control_fp;
-
+#endif /* (PPC_HAS_FPU == 1) */
#endif /* ASM */
/*
@@ -549,7 +561,9 @@ typedef struct {
* CPUs with a "floating point save context" instruction.
*/
+#if (PPC_HAS_FPU == 1)
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
+#endif
/*
* (Optional) # of bytes for libmisc/stackchk to check
@@ -595,7 +609,7 @@ typedef struct {
#ifndef ASM
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
return ( level & MSR_EE ) != 0;
}
@@ -729,14 +743,6 @@ static inline CPU_Counter_ticks _CPU_Counter_read( void )
return value;
}
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
#endif /* ASM */
@@ -935,6 +941,7 @@ RTEMS_NO_RETURN void _CPU_Context_switch_no_return(
RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
+#if (PPC_HAS_FPU == 1)
/*
* _CPU_Context_save_fp
*
@@ -954,6 +961,7 @@ void _CPU_Context_save_fp(
void _CPU_Context_restore_fp(
Context_Control_fp **fp_context_ptr
);
+#endif
#ifdef RTEMS_SMP
uint32_t _CPU_SMP_Initialize( void );
diff --git a/cpukit/score/cpu/powerpc/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/powerpc/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 01bb99cda3..0000000000
--- a/cpukit/score/cpu/powerpc/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h
index cfed43ced4..68b7165546 100644
--- a/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h
@@ -12,7 +12,7 @@
*
* Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu>
*
- * Copyright (c) 2009, 2017 embedded brains GmbH
+ * Copyright (C) 2009, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -151,6 +151,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifdef RTEMS_SMP
/* Use SPRG0 for the per-CPU control of the current processor */
@@ -273,16 +275,39 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( ".long 0" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+#ifdef __powerpc64__
+ register uintptr_t tp __asm__( "13" );
+#else
+ register uintptr_t tp __asm__( "2" );
+#endif
+
+ tp = ppc_get_context( context )->tp;
+
+ /* Make sure that the register assignment is not optimized away */
+ __asm__ volatile ( "" : : "r" ( tp ) );
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ return (void *) ppc_get_context( context )->tp;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/powerpc/ppc-context-validate.S b/cpukit/score/cpu/powerpc/ppc-context-validate.S
index e4331b2661..721633c642 100644
--- a/cpukit/score/cpu/powerpc/ppc-context-validate.S
+++ b/cpukit/score/cpu/powerpc/ppc-context-validate.S
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2013, 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -99,6 +99,7 @@
#define VTMP_OFFSET VOFFSET(12)
#define VTMP2_OFFSET VOFFSET(13)
#define VRSAVE_OFFSET VOFFSET(14)
+ #define VRSAVE2_OFFSET (VOFFSET(14) + 4)
#define VSCR_OFFSET (VOFFSET(14) + 12)
#define ALTIVECEND VOFFSET(15)
#else
@@ -161,6 +162,13 @@ _CPU_Context_validate:
#endif
#ifdef PPC_MULTILIB_ALTIVEC
+ mfvrsave r0
+ stw r0, VRSAVE_OFFSET(r1)
+ li r0, 0xffffffff
+ mtvrsave r0
+ mfvscr v0
+ li r0, VSCR_OFFSET
+ stvewx v0, r1, r0
li r0, V20_OFFSET
stvx v20, r1, r0
li r0, V21_OFFSET
@@ -185,11 +193,6 @@ _CPU_Context_validate:
stvx v30, r1, r0
li r0, V31_OFFSET
stvx v31, r1, r0
- mfvscr v0
- li r0, VSCR_OFFSET
- stvewx v0, r1, r0
- mfvrsave r0
- stw r0, VRSAVE_OFFSET(r1)
#endif
/* Fill */
@@ -337,9 +340,11 @@ _CPU_Context_validate:
FILL_V 29
FILL_V 30
FILL_V 31
+#ifndef __PPC_VRSAVE__
addi r4, r3, 0x700
mtvrsave r4
#endif
+#endif
/* Check */
check:
@@ -516,6 +521,15 @@ check:
#ifdef PPC_MULTILIB_ALTIVEC
.macro CHECK_V i
+#ifdef __PPC_VRSAVE__
+ mfvrsave r4
+.if (31 - \i) > 15
+ andis. r5, r4, 1 << (31 - \i - 16)
+.else
+ andi. r5, r4, 1 << (31 - \i)
+.endif
+ beq 1f
+#endif
li r4, VTMP_OFFSET
stvx \i, r1, r4
lwz r5, VTMP_OFFSET(r1)
@@ -534,9 +548,43 @@ check:
addi r4, r3, 0x600 + \i
cmpw r5, r4
bne restore
+#ifdef __PPC_VRSAVE__
+ mfvrsave r4
+.if (31 - \i) > 15
+ xoris r4, r4, 1 << (31 - \i - 16)
+.else
+ xori r4, r4, 1 << (31 - \i)
+.endif
+ mtvrsave r4
+ b 2f
+1:
+.if (31 - \i) > 15
+ oris r4, r4, 1 << (31 - \i - 16)
+.else
+ ori r4, r4, 1 << (31 - \i)
+.endif
+ mtvrsave r4
+ addi r4, r3, 0x300 + \i
+ stw r4, VTMP_OFFSET(r1)
+ addi r4, r3, 0x400 + \i
+ stw r4, VTMP_OFFSET + 4(r1)
+ addi r4, r3, 0x500 + \i
+ stw r4, VTMP_OFFSET + 8(r1)
+ addi r4, r3, 0x600 + \i
+ stw r4, VTMP_OFFSET + 12(r1)
+ li r4, VTMP_OFFSET
+ lvx \i, r1, r4
+2:
+#endif
.endm
/* Check VSCR */
+#ifdef __PPC_VRSAVE__
+ mfvrsave r4
+ stw r4, VRSAVE2_OFFSET(r1)
+ oris r4, r4, 0x8000
+ mtvrsave r4
+#endif
li r4, VTMP_OFFSET
stvx v0, r1, r4
mfvscr v0
@@ -548,6 +596,10 @@ check:
bne restore
li r4, VTMP_OFFSET
lvx v0, r1, r4
+#ifdef __PPC_VRSAVE__
+ lwz r4, VRSAVE2_OFFSET(r1)
+ mtvrsave r4
+#endif
CHECK_V 0
CHECK_V 1
@@ -582,10 +634,16 @@ check:
CHECK_V 30
CHECK_V 31
mfvrsave r5
+#ifdef __PPC_VRSAVE__
+ addi r5, r5, 1
+ cmplwi r0, r5, 1
+ bgt restore
+#else
addi r4, r3, 0x700
cmpw r5, r4
bne restore
#endif
+#endif
mtcr r29
addi r5, r3, 1
@@ -595,7 +653,7 @@ check:
restore:
#ifdef PPC_MULTILIB_ALTIVEC
- lwz r0, VRSAVE_OFFSET(r1)
+ li r0, 0xffffffff
mtvrsave r0
li r0, V31_OFFSET
lvx v31, r1, r0
@@ -621,6 +679,11 @@ restore:
lvx v21, r1, r0
li r0, V20_OFFSET
lvx v20, r1, r0
+ li r0, VSCR_OFFSET
+ lvewx v0, r1, r0
+ mtvscr v0
+ lwz r0, VRSAVE_OFFSET(r1)
+ mtvrsave r0
#endif
#ifdef PPC_MULTILIB_FPU
diff --git a/cpukit/score/cpu/powerpc/ppc-context-volatile-clobber.S b/cpukit/score/cpu/powerpc/ppc-context-volatile-clobber.S
index 021ec6941b..d235929f7d 100644
--- a/cpukit/score/cpu/powerpc/ppc-context-volatile-clobber.S
+++ b/cpukit/score/cpu/powerpc/ppc-context-volatile-clobber.S
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2013, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/powerpc/ppc-isr-disable-mask.S b/cpukit/score/cpu/powerpc/ppc-isr-disable-mask.S
index 4fc765195d..529b88bf3f 100644
--- a/cpukit/score/cpu/powerpc/ppc-isr-disable-mask.S
+++ b/cpukit/score/cpu/powerpc/ppc-isr-disable-mask.S
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2014 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2014 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/riscv/cpu.c b/cpukit/score/cpu/riscv/cpu.c
index 62150d4ea5..74a716a3b2 100644
--- a/cpukit/score/cpu/riscv/cpu.c
+++ b/cpukit/score/cpu/riscv/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 embedded brains GmbH
+ * Copyright (c) 2018 embedded brains GmbH & Co. KG
*
* Copyright (c) 2015 University of York.
* Hesham ALmatary <hesham@alumni.york.ac.uk>
@@ -173,18 +173,6 @@ RTEMS_STATIC_ASSERT(
riscv_interrupt_frame_size
);
-void _init(void);
-
-void _fini(void);
-
-void _init(void)
-{
-}
-
-void _fini(void)
-{
-}
-
/**
* @brief Performs processor dependent initialization.
*/
diff --git a/cpukit/score/cpu/riscv/include/libcpu/access.h b/cpukit/score/cpu/riscv/include/libcpu/access.h
index 4f2a780895..f414d6f22f 100644
--- a/cpukit/score/cpu/riscv/include/libcpu/access.h
+++ b/cpukit/score/cpu/riscv/include/libcpu/access.h
@@ -1,12 +1,31 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
/*
* access.h - access routines for SPARC. SPARC is big endian only.
*
* COPYRIGHT (c) 2011
* Aeroflex Gaisler.
*
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LIBCPU_ACCESS_H
diff --git a/cpukit/score/cpu/riscv/include/libcpu/byteorder.h b/cpukit/score/cpu/riscv/include/libcpu/byteorder.h
index 939e51fe84..1b4f6f3b1e 100644
--- a/cpukit/score/cpu/riscv/include/libcpu/byteorder.h
+++ b/cpukit/score/cpu/riscv/include/libcpu/byteorder.h
@@ -7,6 +7,8 @@
#ifndef _LIBCPU_BYTEORDER_H
#define _LIBCPU_BYTEORDER_H
+#include <stdint.h>
+
static inline void st_le32(volatile uint32_t *addr, uint32_t value)
{
*(addr)=value ;
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index 471c6c6c3e..e342e7d4af 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -4,7 +4,7 @@
*/
/*
- * Copyright (c) 2018 embedded brains GmbH
+ * Copyright (c) 2018 embedded brains GmbH & Co. KG
*
* Copyright (c) 2015 University of York.
* Hesham Almatary <hesham@alumni.york.ac.uk>
@@ -186,28 +186,26 @@ static inline void riscv_interrupt_enable( uint32_t level )
riscv_interrupt_disable(); \
} while(0)
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level )
+static inline bool _CPU_ISR_Is_enabled( unsigned long level )
{
return ( level & RISCV_MSTATUS_MIE ) != 0;
}
-RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level( uint32_t level )
+static inline void _CPU_ISR_Set_level( uint32_t level )
{
- if ( ( level & CPU_MODES_INTERRUPT_MASK) == 0 ) {
- __asm__ volatile (
- ".option push\n"
- ".option arch, +zicsr\n"
- "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
- ".option pop"
- );
- } else {
- __asm__ volatile (
- ".option push\n"
- ".option arch, +zicsr\n"
- "csrrc zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
- ".option pop"
- );
- }
+ /*
+ * Where CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE, the only supported
+ * interrupt level allowed to set is 0 (interrupts enabled). This constraint
+ * is enforced by the API level functions which return an error status for
+ * other interrupt levels.
+ */
+ (void) level;
+ __asm__ volatile (
+ ".option push\n"
+ ".option arch, +zicsr\n"
+ "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
+ ".option pop"
+ );
}
uint32_t _CPU_ISR_Get_level( void );
@@ -459,14 +457,6 @@ extern volatile uint32_t * const _RISCV_Counter;
CPU_Counter_ticks _CPU_Counter_read( void );
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
#ifdef RTEMS_SMP
uint32_t _CPU_SMP_Initialize( void );
@@ -489,7 +479,7 @@ static inline uint32_t _CPU_SMP_Get_current_processor( void )
"=&r" ( mhartid )
);
- return (uint32_t) mhartid;
+ return (uint32_t) mhartid - RISCV_BOOT_HARTID;
}
void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 8ee9606b44..0000000000
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
index 5162cbbd51..13fd60ed8c 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
@@ -5,7 +5,7 @@
*/
/*
- * Copyright (c) 2013, 2018 embedded brains GmbH
+ * Copyright (C) 2013, 2018 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -54,6 +54,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 16
#endif
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifdef RTEMS_SMP
#define RISCV_CONTEXT_IS_EXECUTING 0
#endif
@@ -296,6 +298,16 @@
extern "C" {
#endif
+static inline uint32_t _RISCV_Map_hardid_to_cpu_index( uint32_t hardid )
+{
+ return hardid - RISCV_BOOT_HARTID;
+}
+
+static inline uint32_t _RISCV_Map_cpu_index_to_hardid( uint32_t cpu_index )
+{
+ return cpu_index + RISCV_BOOT_HARTID;
+}
+
/* Core Local Interruptor (CLINT) */
typedef union {
@@ -325,7 +337,7 @@ typedef struct {
uint32_t priority[RISCV_PLIC_MAX_INTERRUPTS];
uint32_t pending[1024];
uint32_t enable[16320][32];
- RISCV_PLIC_hart_regs harts[CPU_MAXIMUM_PROCESSORS];
+ RISCV_PLIC_hart_regs harts[CPU_MAXIMUM_PROCESSORS + RISCV_BOOT_HARTID];
} RISCV_PLIC_regs;
typedef struct {
@@ -420,16 +432,35 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( "unimp" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ register uintptr_t tp __asm__( "tp" );
+
+ tp = context->tp;
+
+ /* Make sure that the register assignment is not optimized away */
+ __asm__ volatile ( "" : : "r" ( tp ) );
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ return (void *) context->tp;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/riscv/riscv-context-initialize.c b/cpukit/score/cpu/riscv/riscv-context-initialize.c
index c6bd99ebbd..67998b426e 100644
--- a/cpukit/score/cpu/riscv/riscv-context-initialize.c
+++ b/cpukit/score/cpu/riscv/riscv-context-initialize.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 embedded brains GmbH
+ * Copyright (c) 2018 embedded brains GmbH & Co. KG
*
* Copyright (c) 2015 University of York.
* Hesham Almatary <hesham@alumni.york.ac.uk>
@@ -68,7 +68,7 @@ void _CPU_Context_Initialize(
if ( tls_area != NULL ) {
void *tls_block;
- tls_block = _TLS_TCB_before_TLS_block_initialize( tls_area );
+ tls_block = _TLS_Initialize_area( tls_area );
context->tp = (uintptr_t) tls_block;
}
}
diff --git a/cpukit/score/cpu/riscv/riscv-context-switch.S b/cpukit/score/cpu/riscv/riscv-context-switch.S
index cfaff444b0..a00c842de2 100644
--- a/cpukit/score/cpu/riscv/riscv-context-switch.S
+++ b/cpukit/score/cpu/riscv/riscv-context-switch.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 embedded brains GmbH
+ * Copyright (c) 2018 embedded brains GmbH & Co. KG
*
* Copyright (c) 2015 University of York.
* Hesham ALmatary <hesham@alumni.york.ac.uk>
diff --git a/cpukit/score/cpu/riscv/riscv-context-validate.S b/cpukit/score/cpu/riscv/riscv-context-validate.S
index 6bdb06a15b..838803e809 100644
--- a/cpukit/score/cpu/riscv/riscv-context-validate.S
+++ b/cpukit/score/cpu/riscv/riscv-context-validate.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 embedded brains GmbH
+ * Copyright (c) 2018 embedded brains GmbH & Co. KG
* Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>
*
* Redistribution and use in source and binary forms, with or without
diff --git a/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S b/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S
index 628bd1a467..efea2afc72 100644
--- a/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S
+++ b/cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 embedded brains GmbH
+ * Copyright (c) 2018 embedded brains GmbH & Co. KG
* Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>
*
* Redistribution and use in source and binary forms, with or without
diff --git a/cpukit/score/cpu/riscv/riscv-counter.S b/cpukit/score/cpu/riscv/riscv-counter.S
index e779325b4b..96c68e6b13 100644
--- a/cpukit/score/cpu/riscv/riscv-counter.S
+++ b/cpukit/score/cpu/riscv/riscv-counter.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 embedded brains GmbH
+ * Copyright (c) 2018 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/riscv/riscv-exception-frame-print.c b/cpukit/score/cpu/riscv/riscv-exception-frame-print.c
index 897ceaf9a8..61986a8ba2 100644
--- a/cpukit/score/cpu/riscv/riscv-exception-frame-print.c
+++ b/cpukit/score/cpu/riscv/riscv-exception-frame-print.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 embedded brains GmbH
+ * Copyright (c) 2018 embedded brains GmbH & Co. KG
* Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>
*
* Redistribution and use in source and binary forms, with or without
diff --git a/cpukit/score/cpu/riscv/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S
index 87a69652a4..34e7cbb0b3 100644
--- a/cpukit/score/cpu/riscv/riscv-exception-handler.S
+++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2018 embedded brains GmbH
+ * Copyright (c) 2018 embedded brains GmbH & Co. KG
* Copyright (c) 2015 University of York.
* Hesham Almatary <hesham@alumni.york.ac.uk>
diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpu.h b/cpukit/score/cpu/sh/include/rtems/score/cpu.h
index 2805e4244c..f2b59a8713 100644
--- a/cpukit/score/cpu/sh/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sh/include/rtems/score/cpu.h
@@ -393,7 +393,7 @@ void CPU_delay( uint32_t microseconds );
#define _CPU_ISR_Flash( _level) \
sh_flash_interrupts( _level)
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
sh_get_interrupt_level( level );
return level == 0;
@@ -576,14 +576,6 @@ uint32_t _CPU_Counter_frequency( void );
CPU_Counter_ticks _CPU_Counter_read( void );
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
/** Type that can store a 32-bit integer or a pointer. */
typedef uintptr_t CPU_Uint32ptr;
diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/sh/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 598ee76b20..0000000000
--- a/cpukit/score/cpu/sh/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h
index 745a185d1a..e5f45eb363 100644
--- a/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h
@@ -5,7 +5,7 @@
*/
/*
- * Copyright (c) 2013 embedded brains GmbH
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -29,6 +29,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
@@ -37,28 +39,47 @@ extern "C" {
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
-RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern )
+static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
+ (void) pattern;
+
/* TODO */
}
-RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern )
+static inline void _CPU_Context_validate( uintptr_t pattern )
{
+ (void) pattern;
+
while (1) {
/* TODO */
}
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( ".word 0" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ (void) context;
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ (void) context;
+ return NULL;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/sh/sh-exception-frame-print.c b/cpukit/score/cpu/sh/sh-exception-frame-print.c
index 4828493309..d6c49f5569 100644
--- a/cpukit/score/cpu/sh/sh-exception-frame-print.c
+++ b/cpukit/score/cpu/sh/sh-exception-frame-print.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012 embedded brains GmbH & Co. KG
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c
index b910d96d8d..c82fa935fe 100644
--- a/cpukit/score/cpu/sparc/cpu.c
+++ b/cpukit/score/cpu/sparc/cpu.c
@@ -15,7 +15,7 @@
* COPYRIGHT (c) 1989-2007.
* On-Line Applications Research Corporation (OAR).
*
- * Copyright (c) 2017 embedded brains GmbH
+ * Copyright (c) 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -319,7 +319,7 @@ void _CPU_Context_Initialize(
the_context->isr_dispatch_disable = 0;
if ( tls_area != NULL ) {
- void *tcb = _TLS_TCB_after_TLS_block_initialize( tls_area );
+ void *tcb = _TLS_Initialize_area( tls_area );
the_context->g7 = (uintptr_t) tcb;
}
diff --git a/cpukit/score/cpu/sparc/cpu_asm.S b/cpukit/score/cpu/sparc/cpu_asm.S
index af54e273b2..fd7186b499 100644
--- a/cpukit/score/cpu/sparc/cpu_asm.S
+++ b/cpukit/score/cpu/sparc/cpu_asm.S
@@ -9,7 +9,7 @@
* COPYRIGHT (c) 1989-2011.
* On-Line Applications Research Corporation (OAR).
*
- * Copyright (c) 2014, 2017 embedded brains GmbH
+ * Copyright (C) 2014, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -246,6 +246,14 @@ done_flushing:
mov %g1, %psr ! restore status register and
! **** ENABLE TRAPS ****
+ /*
+ * WARNING: This code does not run with the restored stack pointer. In
+ * SMP configurations, it uses a processor-specific stack. In
+ * uniprocessor configurations, it uses the stack of the caller. In
+ * this case, the caller shall ensure that it is not the interrupt
+ * stack (which is also the system initialization stack).
+ */
+
ld [%o1 + G5_OFFSET], %g5 ! restore the global registers
ld [%o1 + G7_OFFSET], %g7
@@ -266,7 +274,9 @@ done_flushing:
ldd [%o1 + I4_OFFSET], %i4
ldd [%o1 + I6_FP_OFFSET], %i6
- ldd [%o1 + O6_SP_OFFSET], %o6 ! restore the output registers
+ ldd [%o1 + O6_SP_OFFSET], %o6 ! restore the non-volatile output
+ ! registers (stack pointer,
+ ! link register)
jmp %o7 + 8 ! return
nop ! delay slot
@@ -325,6 +335,23 @@ SYM(_CPU_Context_restore):
ba SYM(_CPU_Context_restore_heir)
mov %i0, %o1 ! in the delay slot
+#if !defined(RTEMS_SMP)
+ .align 4
+ PUBLIC(_SPARC_Start_multitasking)
+SYM(_SPARC_Start_multitasking):
+ /*
+ * Restore the stack pointer right now, so that the window flushing and
+ * interrupts during _CPU_Context_restore_heir() use the stack of the
+ * heir thread. This is crucial for the interrupt handling to prevent
+ * a concurrent use of the interrupt stack (which is also the system
+ * initialization stack).
+ */
+ ld [%o0 + O6_SP_OFFSET], %o6
+
+ ba SYM(_CPU_Context_restore)
+ nop
+#endif
+
/*
* void _SPARC_Interrupt_trap()
*
@@ -496,9 +523,7 @@ dont_do_the_window:
bnz dont_switch_stacks ! No, then do not switch stacks
#if defined(RTEMS_PROFILING)
- sethi %hi(_SPARC_Counter), %o5
- ld [%o5 + %lo(_SPARC_Counter)], %l4
- call %l4
+ call SYM(_SPARC_Counter_read_ISR_disabled)
nop
mov %o0, %o5
#else
@@ -577,7 +602,7 @@ dont_switch_stacks:
cmp %l7, 0
bne profiling_not_outer_most_exit
nop
- call %l4 ! Call _SPARC_Counter.counter_read
+ call SYM(_SPARC_Counter_read_ISR_disabled)
mov %g1, %l4 ! Save previous interrupt status
mov %o0, %o2 ! o2 = 3rd arg = interrupt exit instant
mov %l3, %o1 ! o1 = 2nd arg = interrupt entry instant
diff --git a/cpukit/score/cpu/sparc/include/libcpu/byteorder.h b/cpukit/score/cpu/sparc/include/libcpu/byteorder.h
index 38b1f18f63..0c469ba36b 100644
--- a/cpukit/score/cpu/sparc/include/libcpu/byteorder.h
+++ b/cpukit/score/cpu/sparc/include/libcpu/byteorder.h
@@ -37,42 +37,42 @@
extern "C" {
#endif
-RTEMS_INLINE_ROUTINE uint16_t ld_le16(volatile uint16_t *addr)
+static inline uint16_t ld_le16(volatile uint16_t *addr)
{
return CPU_swap_u16(*addr);
}
-RTEMS_INLINE_ROUTINE void st_le16(volatile uint16_t *addr, uint16_t val)
+static inline void st_le16(volatile uint16_t *addr, uint16_t val)
{
*addr = CPU_swap_u16(val);
}
-RTEMS_INLINE_ROUTINE uint32_t ld_le32(volatile uint32_t *addr)
+static inline uint32_t ld_le32(volatile uint32_t *addr)
{
return CPU_swap_u32(*addr);
}
-RTEMS_INLINE_ROUTINE void st_le32(volatile uint32_t *addr, uint32_t val)
+static inline void st_le32(volatile uint32_t *addr, uint32_t val)
{
*addr = CPU_swap_u32(val);
}
-RTEMS_INLINE_ROUTINE uint16_t ld_be16(volatile uint16_t *addr)
+static inline uint16_t ld_be16(volatile uint16_t *addr)
{
return *addr;
}
-RTEMS_INLINE_ROUTINE void st_be16(volatile uint16_t *addr, uint16_t val)
+static inline void st_be16(volatile uint16_t *addr, uint16_t val)
{
*addr = val;
}
-RTEMS_INLINE_ROUTINE uint32_t ld_be32(volatile uint32_t *addr)
+static inline uint32_t ld_be32(volatile uint32_t *addr)
{
return *addr;
}
-RTEMS_INLINE_ROUTINE void st_be32(volatile uint32_t *addr, uint32_t val)
+static inline void st_be32(volatile uint32_t *addr, uint32_t val)
{
*addr = val;
}
diff --git a/cpukit/score/cpu/sparc/include/libcpu/grlib-tn-0018.h b/cpukit/score/cpu/sparc/include/libcpu/grlib-tn-0018.h
index 62f33da6e8..10f34c6123 100644
--- a/cpukit/score/cpu/sparc/include/libcpu/grlib-tn-0018.h
+++ b/cpukit/score/cpu/sparc/include/libcpu/grlib-tn-0018.h
@@ -1,7 +1,16 @@
/* SPDX-License-Identifier: BSD-2-Clause */
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUSPARC
+ *
+ * @brief This header file provides interfaces of the GRLIB-TN-0018 LEON3FT
+ * RETT Restart Errata fixes.
+ */
+
/*
- * Copyright (C) 2020 Cobham Gailer AB
+ * Copyright (C) 2020 Cobham Gaisler AB
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/sparc/include/rtems/asm.h b/cpukit/score/cpu/sparc/include/rtems/asm.h
index de65f35d2c..ca89f8e417 100644
--- a/cpukit/score/cpu/sparc/include/rtems/asm.h
+++ b/cpukit/score/cpu/sparc/include/rtems/asm.h
@@ -1,8 +1,10 @@
/**
* @file
*
- * @brief Address the Problems Caused by Incompatible Flavor of
- * Assemblers and Toolsets
+ * @ingroup RTEMSScoreCPUSPARCASM
+ *
+ * @brief This header file provides interfaces to address problems caused by
+ * incompatible flavor of assemblers and toolsets.
*
* This include file attempts to address the problems
* caused by incompatible flavors of assemblers and
diff --git a/cpukit/score/cpu/sparc/include/rtems/score/cpu.h b/cpukit/score/cpu/sparc/include/rtems/score/cpu.h
index 225eaf96c6..a21cef371f 100644
--- a/cpukit/score/cpu/sparc/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc/include/rtems/score/cpu.h
@@ -3,10 +3,10 @@
/**
* @file
*
- * @brief SPARC CPU Department Source
+ * @ingroup RTEMSScoreCPUSPARC
*
- * This include file contains information pertaining to the port of
- * the executive to the SPARC processor.
+ * @brief This header file defines interfaces pertaining to the port of the
+ * executive to the SPARC processor.
*/
/*
@@ -797,7 +797,7 @@ void _SPARC_Interrupt_dispatch( uint32_t irq );
#define _CPU_ISR_Is_enabled( _isr_cookie ) \
sparc_interrupt_is_enabled( _isr_cookie )
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
return ( level & SPARC_PSR_PIL_MASK ) == 0;
}
@@ -993,6 +993,25 @@ RTEMS_NO_RETURN void _CPU_Context_switch_no_return(
*/
RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
+#if !defined(RTEMS_SMP)
+/**
+ * @brief Starts multitasking in uniprocessor configurations.
+ *
+ * This function just sets the stack of the heir thread and then calls
+ * _CPU_Context_restore().
+ *
+ * This is causes that the window flushing and interrupts during
+ * _CPU_Context_restore() use the stack of the heir thread. This is crucial
+ * for the interrupt handling to prevent a concurrent use of the interrupt
+ * stack (which is also the system initialization stack).
+ *
+ * @param[in] heir is the context of the heir thread.
+ */
+RTEMS_NO_RETURN void _SPARC_Start_multitasking( Context_Control *heir );
+
+#define _CPU_Start_multitasking( _heir ) _SPARC_Start_multitasking( _heir )
+#endif
+
#if defined(RTEMS_SMP)
uint32_t _CPU_SMP_Initialize( void );
@@ -1132,39 +1151,7 @@ typedef uint32_t CPU_Counter_ticks;
uint32_t _CPU_Counter_frequency( void );
-typedef CPU_Counter_ticks ( *SPARC_Counter_read )( void );
-
-/*
- * The SPARC processors supported by RTEMS have no built-in CPU counter
- * support. We have to use some hardware counter module for this purpose, for
- * example the GPTIMER instance used by the clock driver. The BSP must provide
- * an implementation of the CPU counter read function. This allows the use of
- * dynamic hardware enumeration.
- */
-typedef struct {
- SPARC_Counter_read read_isr_disabled;
- SPARC_Counter_read read;
- volatile const CPU_Counter_ticks *counter_register;
- volatile const uint32_t *pending_register;
- uint32_t pending_mask;
- CPU_Counter_ticks accumulated;
- CPU_Counter_ticks interval;
-} SPARC_Counter;
-
-extern const SPARC_Counter _SPARC_Counter;
-
-static inline CPU_Counter_ticks _CPU_Counter_read( void )
-{
- return ( *_SPARC_Counter.read )();
-}
-
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
+CPU_Counter_ticks _CPU_Counter_read( void );
/** Type that can store a 32-bit integer or a pointer. */
typedef uintptr_t CPU_Uint32ptr;
diff --git a/cpukit/score/cpu/sparc/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/sparc/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 01bb99cda3..0000000000
--- a/cpukit/score/cpu/sparc/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h
index 7197eb960e..9697209a97 100644
--- a/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h
@@ -3,12 +3,15 @@
/**
* @file
*
- * @brief CPU Port Implementation API
+ * @ingroup RTEMSScoreCPUSPARC
+ *
+ * @brief This header file defines implementation interfaces pertaining to the
+ * port of the executive to the SPARC processor.
*/
/*
* Copyright (c) 1989, 2007 On-Line Applications Research Corporation (OAR)
- * Copyright (c) 2013, 2016 embedded brains GmbH
+ * Copyright (C) 2013, 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -120,6 +123,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
#endif
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 20
+
#if ( SPARC_HAS_FPU == 1 )
/**
* @brief Offset of the CPU_Per_CPU_control::fsr field relative to the
@@ -224,16 +229,42 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( "unimp 0" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ register uint32_t g7 __asm__( "g7" );
+
+ g7 = context->g7;
+
+ /* Make sure that the register assignment is not optimized away */
+ __asm__ volatile ( "" : : "r" ( g7 ) );
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ return (void *) context->g7;
+}
+
+#if defined(RTEMS_PROFILING)
+/**
+ * @brief Reads the CPU counter while interrupts are disabled.
+ */
+CPU_Counter_ticks _SPARC_Counter_read_ISR_disabled( void );
+#endif
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/sparc/include/rtems/score/sparc.h b/cpukit/score/cpu/sparc/include/rtems/score/sparc.h
index 4ac3cc48c9..9b1a09d5e6 100644
--- a/cpukit/score/cpu/sparc/include/rtems/score/sparc.h
+++ b/cpukit/score/cpu/sparc/include/rtems/score/sparc.h
@@ -3,8 +3,10 @@
/**
* @file
*
- * @brief Information Required to Build RTEMS for a Particular Member
- * of the SPARC Family
+ * @ingroup RTEMSScoreCPUSPARC
+ *
+ * @brief This header file provides information required to build RTEMS for a
+ * particular member of the SPARC family.
*
* This file contains the information required to build
* RTEMS for a particular member of the SPARC family. It does
diff --git a/cpukit/score/cpu/sparc/include/rtems/score/sparcimpl.h b/cpukit/score/cpu/sparc/include/rtems/score/sparcimpl.h
deleted file mode 100644
index a62f0a488f..0000000000
--- a/cpukit/score/cpu/sparc/include/rtems/score/sparcimpl.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * Copyright (c) 2016, 2018 embedded brains GmbH. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _RTEMS_SCORE_SPARCIMPL_H
-#define _RTEMS_SCORE_SPARCIMPL_H
-
-#include <rtems/score/cpu.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-struct timecounter;
-
-/*
- * Provides a mutable alias to _SPARC_Counter for use in
- * _SPARC_Counter_initialize(). The _SPARC_Counter and _SPARC_Counter_mutable
- * are defined via the SPARC_COUNTER_DEFINITION define.
- */
-extern SPARC_Counter _SPARC_Counter_mutable;
-
-void _SPARC_Counter_at_tick_clock( void );
-
-CPU_Counter_ticks _SPARC_Counter_read_default( void );
-
-CPU_Counter_ticks _SPARC_Counter_read_up( void );
-
-CPU_Counter_ticks _SPARC_Counter_read_down( void );
-
-CPU_Counter_ticks _SPARC_Counter_read_clock_isr_disabled( void );
-
-CPU_Counter_ticks _SPARC_Counter_read_clock( void );
-
-CPU_Counter_ticks _SPARC_Counter_read_asr23( void );
-
-uint32_t _SPARC_Get_timecount_up( struct timecounter * );
-
-uint32_t _SPARC_Get_timecount_down( struct timecounter * );
-
-uint32_t _SPARC_Get_timecount_clock( struct timecounter * );
-
-uint32_t _SPARC_Get_timecount_asr23( struct timecounter * );
-
-/*
- * Defines the _SPARC_Counter and _SPARC_Counter_mutable global variables.
- * Place this define in the global file scope of the CPU counter support file
- * of the BSP.
- */
-#define SPARC_COUNTER_DEFINITION \
- __asm__ ( \
- "\t.global\t_SPARC_Counter\n" \
- "\t.global\t_SPARC_Counter_mutable\n" \
- "\t.section\t.data._SPARC_Counter,\"aw\",@progbits\n" \
- "\t.align\t4\n" \
- "\t.type\t_SPARC_Counter, #object\n" \
- "\t.size\t_SPARC_Counter, 28\n" \
- "_SPARC_Counter:\n" \
- "_SPARC_Counter_mutable:\n" \
- "\t.long\t_SPARC_Counter_read_default\n" \
- "\t.long\t_SPARC_Counter_read_default\n" \
- "\t.long\t0\n" \
- "\t.long\t0\n" \
- "\t.long\t0\n" \
- "\t.long\t0\n" \
- "\t.long\t0\n" \
- "\t.previous\n" \
- )
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* _RTEMS_SCORE_SPARCIMPL_H */
diff --git a/cpukit/score/cpu/sparc/sparc-bad-trap.S b/cpukit/score/cpu/sparc/sparc-bad-trap.S
index c20a97889f..f769b64125 100644
--- a/cpukit/score/cpu/sparc/sparc-bad-trap.S
+++ b/cpukit/score/cpu/sparc/sparc-bad-trap.S
@@ -9,7 +9,7 @@
*/
/*
- * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/sparc/sparc-context-validate.S b/cpukit/score/cpu/sparc/sparc-context-validate.S
index 3c239172c1..ce1c738d7b 100644
--- a/cpukit/score/cpu/sparc/sparc-context-validate.S
+++ b/cpukit/score/cpu/sparc/sparc-context-validate.S
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2015, 2017 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2015, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/sparc/sparc-context-volatile-clobber.S b/cpukit/score/cpu/sparc/sparc-context-volatile-clobber.S
index 9fe62e2a66..ebbaec59a6 100644
--- a/cpukit/score/cpu/sparc/sparc-context-volatile-clobber.S
+++ b/cpukit/score/cpu/sparc/sparc-context-volatile-clobber.S
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2015 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2015 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/sparc/sparc-counter-asm.S b/cpukit/score/cpu/sparc/sparc-counter-asm.S
deleted file mode 100644
index a073879869..0000000000
--- a/cpukit/score/cpu/sparc/sparc-counter-asm.S
+++ /dev/null
@@ -1,151 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * Copyright (c) 2016, 2018 embedded brains GmbH. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <rtems/asm.h>
-
- /*
- * All functions except _SPARC_Counter_read_clock() in this module are
- * sometimes called with traps disabled.
- */
-
- .section ".text"
- .align 4
-
- PUBLIC(_SPARC_Counter_read_default)
-SYM(_SPARC_Counter_read_default):
- sethi %hi(_SPARC_Counter + 12), %o1
- ld [%o1 + %lo(_SPARC_Counter + 12)], %o0
- add %o0, 1, %o0
- st %o0, [%o1 + %lo(_SPARC_Counter + 12)]
- jmp %o7 + 8
- nop
-
- PUBLIC(_SPARC_Counter_read_up)
- PUBLIC(_SPARC_Get_timecount_up)
-SYM(_SPARC_Counter_read_up):
-SYM(_SPARC_Get_timecount_up):
- sethi %hi(_SPARC_Counter + 8), %o0
- ld [%o0 + %lo(_SPARC_Counter + 8)], %o0
- jmp %o7 + 8
- ld [%o0], %o0
-
- PUBLIC(_SPARC_Counter_read_down)
- PUBLIC(_SPARC_Get_timecount_down)
-SYM(_SPARC_Counter_read_down):
-SYM(_SPARC_Get_timecount_down):
- sethi %hi(_SPARC_Counter + 8), %o0
- ld [%o0 + %lo(_SPARC_Counter + 8)], %o0
- ld [%o0], %o0
- jmp %o7 + 8
- xnor %g0, %o0, %o0
-
- /*
- * For the corresponding C code is something like this:
- *
- * CPU_Counter_ticks _SPARC_Counter_read_clock_isr_disabled( void )
- * {
- * const SPARC_Counter *ctr;
- * CPU_Counter_ticks ticks;
- * CPU_Counter_ticks accumulated;
- *
- * ctr = &_SPARC_Counter;
- * ticks = *ctr->counter_register;
- * accumulated = ctr->accumulated;
- *
- * if ( ( *ctr->pending_register & ctr->pending_mask ) != 0 ) {
- * ticks = *ctr->counter_register;
- * accumulated += ctr->interval;
- * }
- *
- * return accumulated - ticks;
- * }
- */
- PUBLIC(_SPARC_Counter_read_clock_isr_disabled)
-SYM(_SPARC_Counter_read_clock_isr_disabled):
- sethi %hi(_SPARC_Counter), %o5
- or %o5, %lo(_SPARC_Counter), %o5
- ld [%o5 + 8], %o3
- ld [%o5 + 12], %o4
- ld [%o5 + 16], %o2
- ld [%o3], %o0
- ld [%o4], %o1
- btst %o1, %o2
- bne .Lpending_isr_disabled
- ld [%o5 + 20], %o4
- jmp %o7 + 8
- sub %o4, %o0, %o0
-.Lpending_isr_disabled:
- ld [%o5 + 24], %o5
- ld [%o3], %o0
- add %o4, %o5, %o4
- jmp %o7 + 8
- sub %o4, %o0, %o0
-
- /*
- * For the corresponding C code see
- * _SPARC_Counter_read_clock_isr_disabled() above.
- */
- PUBLIC(_SPARC_Counter_read_clock)
- PUBLIC(_SPARC_Get_timecount_clock)
-SYM(_SPARC_Counter_read_clock):
-SYM(_SPARC_Get_timecount_clock):
- sethi %hi(_SPARC_Counter), %o5
- or %o5, %lo(_SPARC_Counter), %o5
- ta SPARC_SWTRAP_IRQDIS
- ld [%o5 + 8], %o3
- ld [%o5 + 12], %o4
- ld [%o5 + 16], %o2
- ld [%o3], %o0
- ld [%o4], %o1
- btst %o1, %o2
- bne .Lpending
- ld [%o5 + 20], %o4
- ta SPARC_SWTRAP_IRQEN
-#ifdef __FIX_LEON3FT_TN0018
- /* A nop is added to work around the GRLIB-TN-0018 errata */
- nop
-#endif
- jmp %o7 + 8
- sub %o4, %o0, %o0
-.Lpending:
- ld [%o5 + 24], %o5
- ld [%o3], %o0
- ta SPARC_SWTRAP_IRQEN
- add %o4, %o5, %o4
- jmp %o7 + 8
- sub %o4, %o0, %o0
-
- PUBLIC(_SPARC_Counter_read_asr23)
- PUBLIC(_SPARC_Get_timecount_asr23)
-SYM(_SPARC_Counter_read_asr23):
-SYM(_SPARC_Get_timecount_asr23):
- jmp %o7 + 8
- mov %asr23, %o0
diff --git a/cpukit/score/cpu/sparc/sparc-exception-frame-print.c b/cpukit/score/cpu/sparc/sparc-exception-frame-print.c
index f216c1dc63..71f7f89c7c 100644
--- a/cpukit/score/cpu/sparc/sparc-exception-frame-print.c
+++ b/cpukit/score/cpu/sparc/sparc-exception-frame-print.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/sparc/sparc-isr-handler.S b/cpukit/score/cpu/sparc/sparc-isr-handler.S
index 264f839f2d..9ecb44e870 100644
--- a/cpukit/score/cpu/sparc/sparc-isr-handler.S
+++ b/cpukit/score/cpu/sparc/sparc-isr-handler.S
@@ -8,7 +8,7 @@
* COPYRIGHT (c) 1989-2011.
* On-Line Applications Research Corporation (OAR).
*
- * Copyright (c) 2014, 2017 embedded brains GmbH
+ * Copyright (C) 2014, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -231,9 +231,7 @@ dont_do_the_window:
bnz dont_switch_stacks ! No, then do not switch stacks
#if defined(RTEMS_PROFILING)
- sethi %hi(_SPARC_Counter), %o5
- ld [%o5 + %lo(_SPARC_Counter)], %l4
- call %l4
+ call SYM(_SPARC_Counter_read_ISR_disabled)
nop
mov %o0, %o5
#else
@@ -335,7 +333,7 @@ pil_fixed:
cmp %l7, 0
bne profiling_not_outer_most_exit
nop
- call %l4 ! Call _SPARC_Counter.counter_read
+ call SYM(_SPARC_Counter_read_ISR_disabled)
mov %g1, %l4 ! Save previous interrupt status
mov %o0, %o2 ! o2 = 3rd arg = interrupt exit instant
mov %l3, %o1 ! o1 = 2nd arg = interrupt entry instant
diff --git a/cpukit/score/cpu/sparc/syscall.S b/cpukit/score/cpu/sparc/syscall.S
index 737a501098..ee21c1b005 100644
--- a/cpukit/score/cpu/sparc/syscall.S
+++ b/cpukit/score/cpu/sparc/syscall.S
@@ -11,7 +11,7 @@
* COPYRIGHT:
*
* COPYRIGHT (c) 1995. European Space Agency.
- * Copyright (c) 2016, 2017 embedded brains GmbH
+ * Copyright (C) 2016, 2017 embedded brains GmbH & Co. KG
*
* This terms of the RTEMS license apply to this file.
*
@@ -44,8 +44,10 @@ SYM(syscall):
ta 0 ! syscall 1, halt with %g1,%g2,%g3 info
PUBLIC(sparc_syscall_exit)
+ PUBLIC(_CPU_Fatal_halt)
SYM(sparc_syscall_exit):
+SYM(_CPU_Fatal_halt):
mov SYS_exit, %g1
mov %o0, %g2 ! Additional exit code 1
diff --git a/cpukit/score/cpu/sparc/syscall.h b/cpukit/score/cpu/sparc/syscall.h
index 2f20886840..6fc8fa3a6f 100644
--- a/cpukit/score/cpu/sparc/syscall.h
+++ b/cpukit/score/cpu/sparc/syscall.h
@@ -1 +1,9 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUSPARC
+ *
+ * @brief This header file provides system call interfaces.
+ */
+
#define SYS_exit 1
diff --git a/cpukit/score/cpu/sparc64/cpu.c b/cpukit/score/cpu/sparc64/cpu.c
index c93b68a2cc..ae3b359876 100644
--- a/cpukit/score/cpu/sparc64/cpu.c
+++ b/cpukit/score/cpu/sparc64/cpu.c
@@ -132,7 +132,7 @@ void _CPU_Context_Initialize(
the_context->isr_dispatch_disable = 0;
if ( tls_area != NULL ) {
- void *tcb = _TLS_TCB_after_TLS_block_initialize( tls_area );
+ void *tcb = _TLS_Initialize_area( tls_area );
the_context->g7 = (uintptr_t) tcb;
}
diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h b/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h
index 03f6e2aa63..90ffe96341 100644
--- a/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h
@@ -697,7 +697,7 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
#define _CPU_ISR_Flash( _level ) \
sparc_flash_interrupts( _level )
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
return ( level & SPARC_PSTATE_IE_MASK ) != 0;
}
@@ -934,14 +934,6 @@ uint32_t _CPU_Counter_frequency( void );
CPU_Counter_ticks _CPU_Counter_read( void );
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
/** Type that can store a 32-bit integer or a pointer. */
typedef uintptr_t CPU_Uint32ptr;
diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/sparc64/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 01bb99cda3..0000000000
--- a/cpukit/score/cpu/sparc64/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h
index c026687d01..25a362c350 100644
--- a/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2013 embedded brains GmbH
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -48,6 +48,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 20
+
#ifndef ASM
#ifdef __cplusplus
@@ -56,28 +58,47 @@ extern "C" {
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
-RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern )
+static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
+ (void) pattern;
+
/* TODO */
}
-RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern )
+static inline void _CPU_Context_validate( uintptr_t pattern )
{
+ (void) pattern;
+
while (1) {
/* TODO */
}
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( "unimp" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ (void) context;
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ (void) context;
+ return NULL;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/sparc64/sparc64-exception-frame-print.c b/cpukit/score/cpu/sparc64/sparc64-exception-frame-print.c
index cd87c9ef34..ba629fd073 100644
--- a/cpukit/score/cpu/sparc64/sparc64-exception-frame-print.c
+++ b/cpukit/score/cpu/sparc64/sparc64-exception-frame-print.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/v850/include/rtems/score/cpu.h b/cpukit/score/cpu/v850/include/rtems/score/cpu.h
index 958bed5dc3..00addf0bc6 100644
--- a/cpukit/score/cpu/v850/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/v850/include/rtems/score/cpu.h
@@ -346,7 +346,7 @@ typedef struct {
__asm__ __volatile__( "di" ); \
} while (0)
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
return ( level & V850_PSW_INTERRUPT_DISABLE_MASK )
!= V850_PSW_INTERRUPT_DISABLE;
@@ -674,14 +674,6 @@ uint32_t _CPU_Counter_frequency( void );
CPU_Counter_ticks _CPU_Counter_read( void );
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
/** Type that can store a 32-bit integer or a pointer. */
typedef uintptr_t CPU_Uint32ptr;
diff --git a/cpukit/score/cpu/v850/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/v850/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 01bb99cda3..0000000000
--- a/cpukit/score/cpu/v850/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h
index 23c1437ba0..5bc1c42459 100644
--- a/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2013 embedded brains GmbH
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -48,6 +48,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
@@ -56,28 +58,47 @@ extern "C" {
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
-RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern )
+static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
+ (void) pattern;
+
/* TODO */
}
-RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern )
+static inline void _CPU_Context_validate( uintptr_t pattern )
{
+ (void) pattern;
+
while (1) {
/* TODO */
}
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( ".word 0" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ (void) context;
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ (void) context;
+ return NULL;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/cpu/v850/v850-exception-frame-print.c b/cpukit/score/cpu/v850/v850-exception-frame-print.c
index cd87c9ef34..ba629fd073 100644
--- a/cpukit/score/cpu/v850/v850-exception-frame-print.c
+++ b/cpukit/score/cpu/v850/v850-exception-frame-print.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h
index bea8e05e39..b26fb4c8ad 100644
--- a/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h
@@ -144,7 +144,7 @@ typedef struct {
#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
#define CPU_STACK_MINIMUM_SIZE (1024*4)
#define CPU_SIZEOF_POINTER 8
-#define CPU_ALIGNMENT 8
+#define CPU_ALIGNMENT 16
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
#define CPU_STACK_ALIGNMENT 16
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
@@ -177,12 +177,12 @@ typedef struct {
(void) _level; /* Prevent -Wunused-but-set-variable */ \
}
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled(uint32_t level)
+static inline bool _CPU_ISR_Is_enabled(uint32_t level)
{
return (level & EFLAGS_INTR_ENABLE) != 0;
}
-RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level(uint32_t new_level)
+static inline void _CPU_ISR_Set_level(uint32_t new_level)
{
if ( new_level ) {
amd64_disable_interrupts();
@@ -192,7 +192,7 @@ RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level(uint32_t new_level)
}
}
-RTEMS_INLINE_ROUTINE uint32_t _CPU_ISR_Get_level(void)
+static inline uint32_t _CPU_ISR_Get_level(void)
{
uint64_t rflags;
@@ -304,15 +304,6 @@ uint32_t _CPU_Counter_frequency( void );
CPU_Counter_ticks _CPU_Counter_read( void );
-
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
#ifdef RTEMS_SMP
*
uint32_t _CPU_SMP_Initialize( void );
diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h
index 4ad50b9f42..10e0887cb9 100644
--- a/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h
+++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h
@@ -31,7 +31,7 @@
#include <rtems/score/basedefs.h>
-RTEMS_INLINE_ROUTINE uint8_t inport_byte(uint16_t port)
+static inline uint8_t inport_byte(uint16_t port)
{
uint8_t ret;
__asm__ volatile ( "inb %1, %0"
@@ -40,12 +40,12 @@ RTEMS_INLINE_ROUTINE uint8_t inport_byte(uint16_t port)
return ret;
}
-RTEMS_INLINE_ROUTINE void outport_byte(uint16_t port, uint8_t val)
+static inline void outport_byte(uint16_t port, uint8_t val)
{
__asm__ volatile ( "outb %0, %1" : : "a" (val), "Nd" (port) );
}
-RTEMS_INLINE_ROUTINE uint16_t amd64_get_cs(void)
+static inline uint16_t amd64_get_cs(void)
{
uint16_t segment = 0;
@@ -54,12 +54,12 @@ RTEMS_INLINE_ROUTINE uint16_t amd64_get_cs(void)
return segment;
}
-RTEMS_INLINE_ROUTINE void amd64_set_cr3(uint64_t segment)
+static inline void amd64_set_cr3(uint64_t segment)
{
__asm__ volatile ( "movq %0, %%cr3" : "=r" (segment) : "0" (segment) );
}
-RTEMS_INLINE_ROUTINE void cpuid(
+static inline void cpuid(
uint32_t code, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx
) {
__asm__ volatile ( "cpuid"
@@ -67,7 +67,7 @@ RTEMS_INLINE_ROUTINE void cpuid(
: "a" (code) );
}
-RTEMS_INLINE_ROUTINE uint64_t rdmsr(uint32_t msr)
+static inline uint64_t rdmsr(uint32_t msr)
{
uint32_t low, high;
__asm__ volatile ( "rdmsr" :
@@ -76,23 +76,23 @@ RTEMS_INLINE_ROUTINE uint64_t rdmsr(uint32_t msr)
return low | (uint64_t) high << 32;
}
-RTEMS_INLINE_ROUTINE void wrmsr(uint32_t msr, uint32_t low, uint32_t high)
+static inline void wrmsr(uint32_t msr, uint32_t low, uint32_t high)
{
__asm__ volatile ( "wrmsr" : :
"a" (low), "d" (high), "c" (msr) );
}
-RTEMS_INLINE_ROUTINE void amd64_enable_interrupts(void)
+static inline void amd64_enable_interrupts(void)
{
__asm__ volatile ( "sti" );
}
-RTEMS_INLINE_ROUTINE void amd64_disable_interrupts(void)
+static inline void amd64_disable_interrupts(void)
{
__asm__ volatile ( "cli" );
}
-RTEMS_INLINE_ROUTINE void stub_io_wait(void)
+static inline void stub_io_wait(void)
{
/* XXX: This likely won't be required on any modern boards, but this function
* exists so it's easier to find all the places it may be used.
diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 598ee76b20..0000000000
--- a/cpukit/score/cpu/x86_64/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h
index d3a4b848e6..d4b7a71009 100644
--- a/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h
@@ -8,7 +8,7 @@
* Copyright (c) 2018.
* Amaan Cheval <amaan.cheval@gmail.com>
*
- * Copyright (c) 2013, 2016 embedded brains GmbH
+ * Copyright (C) 2013, 2016 embedded brains GmbH & Co. KG
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -32,6 +32,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 20
+
#ifndef ASM
#ifdef __cplusplus
@@ -40,28 +42,47 @@ extern "C" {
RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
-RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern )
+static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
+ (void) pattern;
+
/* TODO */
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Context_validate( uintptr_t pattern )
{
- __asm__ volatile ( ".word 0" );
-}
+ (void) pattern;
-RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern )
-{
while (1) {
/* TODO */
}
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_illegal( void )
+{
+ __asm__ volatile ( ".word 0" );
+}
+
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ (void) context;
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ (void) context;
+ return NULL;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpukit/score/src/allocatormutex.c b/cpukit/score/src/allocatormutex.c
index aec965bb85..8a4a9bdd2c 100644
--- a/cpukit/score/src/allocatormutex.c
+++ b/cpukit/score/src/allocatormutex.c
@@ -11,7 +11,7 @@
*/
/*
- * Copyright (c) 2017 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/chainnodecount.c b/cpukit/score/src/chainnodecount.c
index 61ddaa0dbb..b70108a567 100644
--- a/cpukit/score/src/chainnodecount.c
+++ b/cpukit/score/src/chainnodecount.c
@@ -9,7 +9,7 @@
* _Chain_Node_count_unprotected().
*/
/*
- * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/condition.c b/cpukit/score/src/condition.c
index 976af5d47b..fffe48ee30 100644
--- a/cpukit/score/src/condition.c
+++ b/cpukit/score/src/condition.c
@@ -13,7 +13,7 @@
*/
/*
- * Copyright (c) 2015, 2016 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2015, 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/configstackspacesize.c b/cpukit/score/src/configstackspacesize.c
index ce3d7d4836..21c69a0304 100644
--- a/cpukit/score/src/configstackspacesize.c
+++ b/cpukit/score/src/configstackspacesize.c
@@ -9,7 +9,7 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
- * Copyright (C) 2014, 2019 embedded brains GmbH
+ * Copyright (C) 2014, 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/coremsgwkspace.c b/cpukit/score/src/coremsgwkspace.c
index 8441701813..7296ffb4ea 100644
--- a/cpukit/score/src/coremsgwkspace.c
+++ b/cpukit/score/src/coremsgwkspace.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/coretodcheck.c b/cpukit/score/src/coretodcheck.c
index 8c012c5070..1d13d950be 100644
--- a/cpukit/score/src/coretodcheck.c
+++ b/cpukit/score/src/coretodcheck.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/debugisthreaddispatchingallowed.c b/cpukit/score/src/debugisthreaddispatchingallowed.c
index d7880ef331..5c5cc2b34b 100644
--- a/cpukit/score/src/debugisthreaddispatchingallowed.c
+++ b/cpukit/score/src/debugisthreaddispatchingallowed.c
@@ -9,7 +9,7 @@
* _Debug_Is_thread_dispatching_allowed().
*/
/*
- * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/ioprintf.c b/cpukit/score/src/debugunreachable.c
index eb694736ae..f6c2bf67ca 100644
--- a/cpukit/score/src/ioprintf.c
+++ b/cpukit/score/src/debugunreachable.c
@@ -3,14 +3,13 @@
/**
* @file
*
- * @ingroup RTEMSScoreIO
+ * @ingroup RTEMSScore
*
- * @brief This source file contains the implementation of
- * _IO_Printf().
+ * @brief This source file contains the implementation of _Debug_Unreachable().
*/
/*
- * Copyright (c) 2017 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2023 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -38,16 +37,13 @@
#include "config.h"
#endif
-#include <rtems/score/io.h>
+#include <rtems/score/basedefs.h>
-int _IO_Printf( IO_Put_char put_char, void *arg, char const *fmt, ... )
-{
- va_list ap;
- int len;
-
- va_start( ap, fmt );
- len = _IO_Vprintf( put_char, arg, fmt, ap );
- va_end( ap );
+#include <assert.h>
- return len;
+#if defined(RTEMS_DEBUG)
+void _Debug_Unreachable( const char *file, int line, const char *func )
+{
+ __assert_func( file, line, func, "reached unreachable code" );
}
+#endif
diff --git a/cpukit/score/src/futex.c b/cpukit/score/src/futex.c
index ff2bcd853e..e158b61238 100644
--- a/cpukit/score/src/futex.c
+++ b/cpukit/score/src/futex.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2015, 2016 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2015, 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/hash.c b/cpukit/score/src/hash.c
index 42ea7f0582..0b9f127e54 100644
--- a/cpukit/score/src/hash.c
+++ b/cpukit/score/src/hash.c
@@ -9,7 +9,7 @@
*/
/*
- * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -39,7 +39,7 @@
#include <rtems/score/hash.h>
#include <rtems/score/assert.h>
-#include <rtems/score/io.h>
+#include <rtems/base64.h>
#include <limits.h>
@@ -64,7 +64,7 @@ void _Hash_Finalize( Hash_Context *context, Hash_Control *hash )
context->hash = hash;
context->index = 0;
hash->chars[ sizeof( *hash ) - 1 ] = '\0';
- n = _IO_Base64url(
+ n = _Base64url_Encode(
_Hash_Put_char,
context,
digest,
diff --git a/cpukit/score/src/heap.c b/cpukit/score/src/heap.c
index c5596adaa7..948e48e5d5 100644
--- a/cpukit/score/src/heap.c
+++ b/cpukit/score/src/heap.c
@@ -13,7 +13,7 @@
* COPYRIGHT (c) 1989-2009.
* On-Line Applications Research Corporation (OAR).
*
- * Copyright (c) 2009, 2010 embedded brains GmbH.
+ * Copyright (C) 2009, 2010 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/heapallocate.c b/cpukit/score/src/heapallocate.c
index 049a1279b1..8a93ad17b8 100644
--- a/cpukit/score/src/heapallocate.c
+++ b/cpukit/score/src/heapallocate.c
@@ -13,7 +13,7 @@
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
- * Copyright (c) 2009 embedded brains GmbH.
+ * Copyright (c) 2009 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/heapextend.c b/cpukit/score/src/heapextend.c
index 02a36aa442..da506d6a39 100644
--- a/cpukit/score/src/heapextend.c
+++ b/cpukit/score/src/heapextend.c
@@ -13,7 +13,7 @@
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
- * Copyright (c) 2010 embedded brains GmbH.
+ * Copyright (c) 2010 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/heapgreedy.c b/cpukit/score/src/heapgreedy.c
index 47a65dab1b..c8c79cb3ba 100644
--- a/cpukit/score/src/heapgreedy.c
+++ b/cpukit/score/src/heapgreedy.c
@@ -11,7 +11,7 @@
*/
/*
- * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/heapiterate.c b/cpukit/score/src/heapiterate.c
index 4b1cb734a5..77874923da 100644
--- a/cpukit/score/src/heapiterate.c
+++ b/cpukit/score/src/heapiterate.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2011 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/heapnoextend.c b/cpukit/score/src/heapnoextend.c
index 11fe0f3ebb..828448b8db 100644
--- a/cpukit/score/src/heapnoextend.c
+++ b/cpukit/score/src/heapnoextend.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/heapresizeblock.c b/cpukit/score/src/heapresizeblock.c
index 7f7dc29d51..a94461d0a5 100644
--- a/cpukit/score/src/heapresizeblock.c
+++ b/cpukit/score/src/heapresizeblock.c
@@ -13,7 +13,7 @@
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
- * Copyright (c) 2009 embedded brains GmbH.
+ * Copyright (c) 2009 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/iobase64.c b/cpukit/score/src/iobase64.c
deleted file mode 100644
index 38bc2cd22c..0000000000
--- a/cpukit/score/src/iobase64.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* SPDX-License-Identifier: ISC */
-
-/**
- * @file
- *
- * @ingroup RTEMSScoreIO
- *
- * @brief This source file contains the implementation of
- * _IO_Base64() and _IO_Base64url().
- */
-
-/*
- * Copyright (C) 2020, 2021 embedded brains GmbH (http://www.embedded-brains.de)
- * Copyright (C) 2004, 2005, 2007, 2009 Internet Systems Consortium, Inc. ("ISC")
- * Copyright (C) 1998-2001, 2003 Internet Software Consortium.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND ISC DISCLAIMS ALL WARRANTIES WITH
- * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS. IN NO EVENT SHALL ISC BE LIABLE FOR ANY SPECIAL, DIRECT,
- * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
- * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
- * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <rtems/score/io.h>
-
-static void
-_IO_Put(int c, void *arg, IO_Put_char put_char)
-{
- (*put_char)(c, arg);
-}
-
-static int
-_IO_Base64_with_encoding(IO_Put_char put_char, void *arg, const void *src,
- size_t srclen, const char *wordbreak, int wordlen, const char *encoding)
-{
- unsigned int loops = 0;
- const unsigned char *in = src;
- int out = 0;
-
- if (wordlen < 4) {
- wordlen = 4;
- }
-
- while (srclen > 2) {
- _IO_Put(encoding[(in[0]>>2)&0x3f], arg, put_char);
- _IO_Put(encoding[((in[0]<<4)&0x30)|
- ((in[1]>>4)&0x0f)], arg, put_char);
- _IO_Put(encoding[((in[1]<<2)&0x3c)|
- ((in[2]>>6)&0x03)], arg, put_char);
- _IO_Put(encoding[in[2]&0x3f], arg, put_char);
- in += 3;
- srclen -= 3;
- out += 4;
-
- loops++;
- if (srclen != 0 &&
- (int)((loops + 1) * 4) >= wordlen)
- {
- const char *w = wordbreak;
- loops = 0;
- while (*w != '\0') {
- _IO_Put(*w, arg, put_char);
- ++w;
- ++out;
- }
- }
- }
- if (srclen == 2) {
- _IO_Put(encoding[(in[0]>>2)&0x3f], arg, put_char);
- _IO_Put(encoding[((in[0]<<4)&0x30)|
- ((in[1]>>4)&0x0f)], arg, put_char);
- _IO_Put(encoding[((in[1]<<2)&0x3c)], arg, put_char);
- _IO_Put('=', arg, put_char);
- out += 4;
- } else if (srclen == 1) {
- _IO_Put(encoding[(in[0]>>2)&0x3f], arg, put_char);
- _IO_Put(encoding[((in[0]<<4)&0x30)], arg, put_char);
- _IO_Put('=', arg, put_char);
- _IO_Put('=', arg, put_char);
- out += 4;
- }
- return out;
-}
-
-static const char base64[] =
- "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/=";
-
-int
-_IO_Base64(IO_Put_char put_char, void *arg, const void *src, size_t srclen,
- const char *wordbreak, int wordlen)
-{
- return _IO_Base64_with_encoding(put_char, arg, src, srclen, wordbreak,
- wordlen, base64);
-}
-
-static const char base64url[] =
- "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789-_=";
-
-int
-_IO_Base64url(IO_Put_char put_char, void *arg, const void *src, size_t srclen,
- const char *wordbreak, int wordlen)
-{
- return _IO_Base64_with_encoding(put_char, arg, src, srclen, wordbreak,
- wordlen, base64url);
-}
diff --git a/cpukit/score/src/iorelax.c b/cpukit/score/src/iorelax.c
deleted file mode 100644
index f37d848605..0000000000
--- a/cpukit/score/src/iorelax.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/**
- * @file
- *
- * @ingroup RTEMSScoreIO
- *
- * @brief This source file contains the implementation of _IO_Relax().
- */
-
-/*
- * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <rtems/score/io.h>
-#include <rtems/score/cpuimpl.h>
-
-void _IO_Relax( void )
-{
- _CPU_Instruction_no_operation();
- _CPU_Instruction_no_operation();
- _CPU_Instruction_no_operation();
- _CPU_Instruction_no_operation();
- _CPU_Instruction_no_operation();
- _CPU_Instruction_no_operation();
- _CPU_Instruction_no_operation();
- _CPU_Instruction_no_operation();
-}
diff --git a/cpukit/score/src/iovprintf.c b/cpukit/score/src/iovprintf.c
deleted file mode 100644
index 0e8eb0b47b..0000000000
--- a/cpukit/score/src/iovprintf.c
+++ /dev/null
@@ -1,377 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSScoreIO
- *
- * @brief This source file contains the implementation of
- * _IO_Vprintf().
- */
-
-/*-
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright (c) 1986, 1988, 1991, 1993
- * The Regents of the University of California. All rights reserved.
- * (c) UNIX System Laboratories, Inc.
- * All or some portions of this file are derived from material licensed
- * to the University of California by American Telephone and Telegraph
- * Co. or Unix System Laboratories, Inc. and are reproduced herein with
- * the permission of UNIX System Laboratories, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @(#)subr_prf.c 8.3 (Berkeley) 1/21/94
- */
-
-#include <rtems/score/io.h>
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: head/sys/kern/subr_prf.c 336417 2018-07-17 14:56:54Z markj $");
-
-#include <sys/param.h>
-#include <string.h>
-
-/* Max number conversion buffer length: a intmax_t in base 8, plus NUL byte. */
-#define MAXNBUF (howmany(sizeof(intmax_t) * NBBY, 3) + 1)
-
-static inline int imax(int a, int b) { return (a > b ? a : b); }
-
-static char const hex2ascii_data[2][16] = {
- { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
- 'a', 'b', 'c', 'd', 'e', 'f' },
- { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
- 'A', 'B', 'C', 'D', 'E', 'F' }
-};
-
-static inline char
-hex2ascii(int hex)
-{
-
- return (hex2ascii_data[0][hex]);
-}
-
-/*
- * Put a NUL-terminated ASCII number (base <= 16) in a buffer in reverse
- * order; return an optional length and a pointer to the last character
- * written in the buffer (i.e., the first character of the string).
- * The buffer pointed to by `nbuf' must have length >= MAXNBUF.
- */
-static char *
-ksprintn(char *nbuf, uintmax_t num, int base, int *lenp, int upper)
-{
- char *p;
-
- p = nbuf;
- *p = '\0';
- do {
- *++p = hex2ascii_data[upper][num % base];
- } while (num /= base);
- if (lenp)
- *lenp = p - nbuf;
- return (p);
-}
-
-int
-_IO_Vprintf(IO_Put_char put_char, void *arg, char const *fmt, va_list ap)
-{
-#define PCHAR(c) {int cc=(c); (*put_char)(cc, arg); retval++; }
- char nbuf[MAXNBUF];
- const char *p, *percent, *q;
- u_char *up;
- int ch, n;
- uintmax_t num;
- int base, lflag, tmp, width, ladjust, sharpflag, neg, sign, dot;
- int cflag, hflag, jflag;
- RTEMS_STATIC_ASSERT(sizeof(intmax_t) == sizeof(long long), _IO_Vprintf_j);
-#if __SIZEOF_PTRDIFF_T__ == __SIZEOF_LONG__
-#define tflag lflag
-#else
- int tflag;
-#endif
-#if __SIZEOF_SIZE_T__ == __SIZEOF_LONG__
-#define zflag lflag
-#else
- int zflag;
-#endif
- int dwidth, upper;
- char padc;
- int stop = 0, retval = 0;
-
- num = 0;
-
- if (fmt == NULL)
- fmt = "(fmt null)\n";
-
- for (;;) {
- padc = ' ';
- width = 0;
- while ((ch = (u_char)*fmt++) != '%' || stop) {
- if (ch == '\0')
- return (retval);
- PCHAR(ch);
- }
- percent = fmt - 1;
- lflag = 0; ladjust = 0; sharpflag = 0; neg = 0;
- sign = 0; dot = 0; dwidth = 0; upper = 0;
- cflag = 0; hflag = 0; jflag = 0; tflag = 0; zflag = 0;
-reswitch: switch (ch = (u_char)*fmt++) {
- case '.':
- dot = 1;
- goto reswitch;
- case '#':
- sharpflag = 1;
- goto reswitch;
- case '+':
- sign = 1;
- goto reswitch;
- case '-':
- ladjust = 1;
- goto reswitch;
- case '%':
- PCHAR(ch);
- break;
- case '*':
- if (!dot) {
- width = va_arg(ap, int);
- if (width < 0) {
- ladjust = !ladjust;
- width = -width;
- }
- } else {
- dwidth = va_arg(ap, int);
- }
- goto reswitch;
- case '0':
- if (!dot) {
- padc = '0';
- goto reswitch;
- }
- /* FALLTHROUGH */
- case '1': case '2': case '3': case '4':
- case '5': case '6': case '7': case '8': case '9':
- for (n = 0;; ++fmt) {
- n = n * 10 + ch - '0';
- ch = *fmt;
- if (ch < '0' || ch > '9')
- break;
- }
- if (dot)
- dwidth = n;
- else
- width = n;
- goto reswitch;
- case 'c':
- width -= 1;
-
- if (!ladjust && width > 0)
- while (width--)
- PCHAR(padc);
- PCHAR(va_arg(ap, int));
- if (ladjust && width > 0)
- while (width--)
- PCHAR(padc);
- break;
- case 'D':
- up = va_arg(ap, u_char *);
- p = va_arg(ap, char *);
- if (!width)
- width = 16;
- while(width--) {
- PCHAR(hex2ascii(*up >> 4));
- PCHAR(hex2ascii(*up & 0x0f));
- up++;
- if (width)
- for (q=p;*q;q++)
- PCHAR(*q);
- }
- break;
- case 'd':
- case 'i':
- base = 10;
- sign = 1;
- goto handle_sign;
- case 'h':
- if (hflag) {
- hflag = 0;
- cflag = 1;
- } else
- hflag = 1;
- goto reswitch;
- case 'j':
- jflag = 1;
- goto reswitch;
- case 'l':
- if (lflag) {
- jflag = 1;
- } else
- lflag = 1;
- goto reswitch;
- case 'o':
- base = 8;
- goto handle_nosign;
- case 'p':
- base = 16;
- sharpflag = (width == 0);
- sign = 0;
- num = (uintptr_t)va_arg(ap, void *);
- goto number;
- case 's':
- p = va_arg(ap, char *);
- if (p == NULL)
- p = "(null)";
- if (!dot)
- n = strlen (p);
- else
- for (n = 0; n < dwidth && p[n]; n++)
- continue;
-
- width -= n;
-
- if (!ladjust && width > 0)
- while (width--)
- PCHAR(padc);
- while (n--)
- PCHAR(*p++);
- if (ladjust && width > 0)
- while (width--)
- PCHAR(padc);
- break;
- case 't':
- tflag = 1;
- goto reswitch;
- case 'u':
- base = 10;
- goto handle_nosign;
- case 'X':
- upper = 1;
- case 'x':
- base = 16;
- goto handle_nosign;
- case 'y':
- base = 16;
- sign = 1;
- goto handle_sign;
- case 'z':
- zflag = 1;
- goto reswitch;
-handle_nosign:
- sign = 0;
- if (jflag)
- num = va_arg(ap, uintmax_t);
-#if __SIZEOF_PTRDIFF_T__ != __SIZEOF_LONG__
- else if (tflag)
- num = va_arg(ap, ptrdiff_t);
-#endif
- else if (lflag)
- num = va_arg(ap, u_long);
-#if __SIZEOF_SIZE_T__ != __SIZEOF_LONG__
- else if (zflag)
- num = va_arg(ap, size_t);
-#endif
- else if (hflag)
- num = (u_short)va_arg(ap, int);
- else if (cflag)
- num = (u_char)va_arg(ap, int);
- else
- num = va_arg(ap, u_int);
- goto number;
-handle_sign:
- if (jflag)
- num = va_arg(ap, intmax_t);
-#if __SIZEOF_PTRDIFF_T__ == __SIZEOF_LONG__
- else if (tflag)
- num = va_arg(ap, ptrdiff_t);
-#endif
- else if (lflag)
- num = va_arg(ap, long);
-#if __SIZEOF_SIZE_T__ == __SIZEOF_LONG__
- else if (zflag)
- num = va_arg(ap, ssize_t);
-#endif
- else if (hflag)
- num = (short)va_arg(ap, int);
- else if (cflag)
- num = (char)va_arg(ap, int);
- else
- num = va_arg(ap, int);
-number:
- if (sign && (intmax_t)num < 0) {
- neg = 1;
- num = -(intmax_t)num;
- }
- p = ksprintn(nbuf, num, base, &n, upper);
- tmp = 0;
- if (sharpflag && num != 0) {
- if (base == 8)
- tmp++;
- else if (base == 16)
- tmp += 2;
- }
- if (neg)
- tmp++;
-
- if (!ladjust && padc == '0')
- dwidth = width - tmp;
- width -= tmp + imax(dwidth, n);
- dwidth -= n;
- if (!ladjust)
- while (width-- > 0)
- PCHAR(' ');
- if (neg)
- PCHAR('-');
- if (sharpflag && num != 0) {
- if (base == 8) {
- PCHAR('0');
- } else if (base == 16) {
- PCHAR('0');
- PCHAR('x');
- }
- }
- while (dwidth-- > 0)
- PCHAR('0');
-
- while (*p)
- PCHAR(*p--);
-
- if (ladjust)
- while (width-- > 0)
- PCHAR(' ');
-
- break;
- default:
- while (percent < fmt)
- PCHAR(*percent++);
- /*
- * Since we ignore a formatting argument it is no
- * longer safe to obey the remaining formatting
- * arguments as the arguments will no longer match
- * the format specs.
- */
- stop = 1;
- break;
- }
- }
-#undef PCHAR
-}
diff --git a/cpukit/score/src/isr.c b/cpukit/score/src/isr.c
index 75df00e228..7337028b0f 100644
--- a/cpukit/score/src/isr.c
+++ b/cpukit/score/src/isr.c
@@ -44,6 +44,8 @@
#include <rtems/score/percpu.h>
#include <rtems/config.h>
+const char * const volatile _ISR_Stack_size_object = _ISR_Stack_size;
+
void _ISR_Handler_initialization( void )
{
uint32_t cpu_max;
diff --git a/cpukit/score/src/isrisinprogress.c b/cpukit/score/src/isrisinprogress.c
index f1b533c718..036cca4cfa 100644
--- a/cpukit/score/src/isrisinprogress.c
+++ b/cpukit/score/src/isrisinprogress.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2013-2015 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2013, 2015 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/isrvectortable.c b/cpukit/score/src/isrvectortable.c
index 4bd892757e..86592bc483 100644
--- a/cpukit/score/src/isrvectortable.c
+++ b/cpukit/score/src/isrvectortable.c
@@ -9,7 +9,7 @@
*/
/*
- * Copyright (C) 2014 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2014 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/kern_ntptime.c b/cpukit/score/src/kern_ntptime.c
index cb39133408..c6f70079b3 100644
--- a/cpukit/score/src/kern_ntptime.c
+++ b/cpukit/score/src/kern_ntptime.c
@@ -58,6 +58,9 @@ __FBSDID("$FreeBSD$");
#include <sys/time.h>
#include <sys/timex.h>
#include <sys/timetc.h>
+#ifdef __rtems__
+#define _KERNEL
+#endif /* __rtems__ */
#include <sys/timepps.h>
#ifndef __rtems__
#include <sys/syscallsubr.h>
@@ -71,11 +74,31 @@ __FBSDID("$FreeBSD$");
#define ntp_update_second _Timecounter_NTP_update_second
#define time_uptime _Timecounter_Time_uptime
struct thread;
+
+static inline long
+lmax(long a, long b)
+{
+
+ if (a > b)
+ return (a);
+ return (b);
+}
+
+static inline quad_t
+qmin(quad_t a, quad_t b)
+{
+
+ if (a < b)
+ return (a);
+ return (b);
+}
#endif /* __rtems__ */
+#ifndef __rtems__
#ifdef PPS_SYNC
FEATURE(pps_sync, "Support usage of external PPS signal by kernel PLL");
#endif
+#endif /* __rtems__ */
/*
* Single-precision macros for 64-bit machines
@@ -374,7 +397,6 @@ SYSCTL_NODE(_kern, OID_AUTO, ntp_pll, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
SYSCTL_PROC(_kern_ntp_pll, OID_AUTO, gettime, CTLTYPE_OPAQUE | CTLFLAG_RD |
CTLFLAG_MPSAFE, 0, sizeof(struct ntptimeval) , ntp_sysctl, "S,ntptimeval",
"");
-#endif /* __rtems__ */
#ifdef PPS_SYNC
SYSCTL_INT(_kern_ntp_pll, OID_AUTO, pps_shiftmax, CTLFLAG_RW,
@@ -391,6 +413,7 @@ SYSCTL_S64(_kern_ntp_pll, OID_AUTO, time_freq, CTLFLAG_RD | CTLFLAG_MPSAFE,
&time_freq, 0,
"Frequency offset (ns/sec)");
#endif
+#endif /* __rtems__ */
/*
* ntp_adjtime() - NTP daemon application interface
@@ -531,16 +554,6 @@ kern_ntp_adjtime(struct thread *td, struct timex *ntv, int *retvalp)
ntv->jitcnt = pps_jitcnt;
ntv->stbcnt = pps_stbcnt;
#endif /* PPS_SYNC */
-#ifdef __rtems__
- ntv->ppsfreq = 0;
- ntv->jitter = 0;
- ntv->shift = 0;
- ntv->stabil = 0;
- ntv->jitcnt = 0;
- ntv->calcnt = 0;
- ntv->errcnt = 0;
- ntv->stbcnt = 0;
-#endif /* __rtems__ */
retval = ntp_is_time_error(time_status) ? TIME_ERROR : time_state;
NTP_UNLOCK();
@@ -769,8 +782,7 @@ RTEMS_SYSINIT_ITEM(_NTP_Initialize, RTEMS_SYSINIT_DEVICE_DRIVERS,
* is selected by the STA_MODE status bit.
*/
static void
-hardupdate(offset)
- long offset; /* clock offset (ns) */
+hardupdate(long offset /* clock offset (ns) */)
{
long mtemp;
l_fp ftemp;
@@ -849,11 +861,11 @@ hardupdate(offset)
* variables, except for the actual time and frequency variables, which
* are determined by this routine and updated atomically.
*
- * tsp - time at PPS
- * nsec - hardware counter at PPS
+ * tsp - time at current PPS event
+ * delta_nsec - time elapsed between the previous and current PPS event
*/
void
-hardpps(struct timespec *tsp, long nsec)
+hardpps(struct timespec *tsp, long delta_nsec)
{
long u_sec, u_nsec, v_nsec; /* temps */
l_fp ftemp;
@@ -888,19 +900,10 @@ hardpps(struct timespec *tsp, long nsec)
pps_tf[0].tv_nsec = u_nsec;
/*
- * Compute the difference between the current and previous
- * counter values. If the difference exceeds 0.5 s, assume it
- * has wrapped around, so correct 1.0 s. If the result exceeds
- * the tick interval, the sample point has crossed a tick
- * boundary during the last second, so correct the tick. Very
- * intricate.
+ * Update the frequency accumulator using the difference between the
+ * current and previous PPS event measured directly by the timecounter.
*/
- u_nsec = nsec;
- if (u_nsec > (NANOSECOND >> 1))
- u_nsec -= NANOSECOND;
- else if (u_nsec < -(NANOSECOND >> 1))
- u_nsec += NANOSECOND;
- pps_fcount += u_nsec;
+ pps_fcount += delta_nsec - NANOSECOND;
if (v_nsec > MAXFREQ || v_nsec < -MAXFREQ)
goto out;
time_status &= ~STA_PPSJITTER;
diff --git a/cpukit/score/src/kern_tc.c b/cpukit/score/src/kern_tc.c
index e57da2c0ca..95ae01b5b4 100644
--- a/cpukit/score/src/kern_tc.c
+++ b/cpukit/score/src/kern_tc.c
@@ -56,12 +56,17 @@
#define timecounter _Timecounter
#define time_second _Timecounter_Time_second
#define time_uptime _Timecounter_Time_uptime
+
#include <rtems/score/timecounterimpl.h>
+#include <rtems/score/assert.h>
#include <rtems/score/atomic.h>
#include <rtems/score/smp.h>
#include <rtems/score/todimpl.h>
#include <rtems/score/watchdogimpl.h>
#include <rtems/rtems/clock.h>
+
+#define ENOIOCTL EINVAL
+#define KASSERT(exp, arg) _Assert(exp)
#endif /* __rtems__ */
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
@@ -90,6 +95,7 @@ __FBSDID("$FreeBSD$");
#include <sys/vdso.h>
#endif /* __rtems__ */
#ifdef __rtems__
+#include <errno.h>
#include <limits.h>
#include <string.h>
#include <rtems.h>
@@ -115,6 +121,13 @@ atomic_thread_fence_rel(void)
}
static inline u_int
+atomic_load_int(Atomic_Uint *i)
+{
+
+ return (_Atomic_Load_uint(i, ATOMIC_ORDER_RELAXED));
+}
+
+static inline u_int
atomic_load_acq_int(Atomic_Uint *i)
{
@@ -1506,7 +1519,6 @@ unlock:
#endif /* __rtems__ */
}
-#ifndef __rtems__
/* Report the frequency of the current timecounter. */
uint64_t
tc_getfrequency(void)
@@ -1515,6 +1527,7 @@ tc_getfrequency(void)
return (timehands->th_counter->tc_frequency);
}
+#ifndef __rtems__
static bool
sleeping_on_old_rtc(struct thread *td)
{
@@ -1891,7 +1904,6 @@ SYSCTL_PROC(_kern_timecounter, OID_AUTO, choice,
"Timecounter hardware detected");
#endif /* __rtems__ */
-#ifndef __rtems__
/*
* RFC 2783 PPS-API implementation.
*/
@@ -1910,9 +1922,15 @@ abi_aware(struct pps_state *pps, int vers)
static int
pps_fetch(struct pps_fetch_args *fapi, struct pps_state *pps)
{
+#ifndef __rtems__
int err, timo;
+#else /* __rtems__ */
+ int err;
+#endif /* __rtems__ */
pps_seq_t aseq, cseq;
+#ifndef __rtems__
struct timeval tv;
+#endif /* __rtems__ */
if (fapi->tsformat && fapi->tsformat != PPS_TSFMT_TSPEC)
return (EINVAL);
@@ -1925,6 +1943,7 @@ pps_fetch(struct pps_fetch_args *fapi, struct pps_state *pps)
* sleep a long time.
*/
if (fapi->timeout.tv_sec || fapi->timeout.tv_nsec) {
+#ifndef __rtems__
if (fapi->timeout.tv_sec == -1)
timo = 0x7fffffff;
else {
@@ -1932,10 +1951,12 @@ pps_fetch(struct pps_fetch_args *fapi, struct pps_state *pps)
tv.tv_usec = fapi->timeout.tv_nsec / 1000;
timo = tvtohz(&tv);
}
+#endif /* __rtems__ */
aseq = atomic_load_int(&pps->ppsinfo.assert_sequence);
cseq = atomic_load_int(&pps->ppsinfo.clear_sequence);
while (aseq == atomic_load_int(&pps->ppsinfo.assert_sequence) &&
cseq == atomic_load_int(&pps->ppsinfo.clear_sequence)) {
+#ifndef __rtems__
if (abi_aware(pps, 1) && pps->driver_mtx != NULL) {
if (pps->flags & PPSFLAG_MTX_SPIN) {
err = msleep_spin(pps, pps->driver_mtx,
@@ -1956,6 +1977,12 @@ pps_fetch(struct pps_fetch_args *fapi, struct pps_state *pps)
} else if (err != 0) {
return (err);
}
+#else /* __rtems__ */
+ _Assert(pps->wait != NULL);
+ err = (*pps->wait)(pps, fapi->timeout);
+ if (err != 0)
+ return (err);
+#endif /* __rtems__ */
}
}
@@ -2051,9 +2078,43 @@ pps_ioctl(u_long cmd, caddr_t data, struct pps_state *pps)
}
}
+#ifdef __rtems__
+/*
+ * The real implementation of hardpps() is defined in kern_ntptime.c. Use it
+ * only if the NTP support is needed by the application.
+ */
+RTEMS_WEAK void
+hardpps(struct timespec *tsp, long nsec)
+{
+
+ (void)tsp;
+ (void)nsec;
+}
+
+static int
+default_wait(struct pps_state *pps, struct timespec timeout)
+{
+
+ (void)pps;
+ (void)timeout;
+
+ return (ETIMEDOUT);
+}
+
+static void
+default_wakeup(struct pps_state *pps)
+{
+
+ (void)pps;
+}
+#endif /* __rtems__ */
void
pps_init(struct pps_state *pps)
{
+#ifdef __rtems__
+ pps->wait = default_wait;
+ pps->wakeup = default_wakeup;
+#endif /* __rtems__ */
pps->ppscap |= PPS_TSFMT_TSPEC | PPS_CANWAIT;
if (pps->ppscap & PPS_CAPTUREASSERT)
pps->ppscap |= PPS_OFFSETASSERT;
@@ -2080,6 +2141,7 @@ void
pps_capture(struct pps_state *pps)
{
struct timehands *th;
+ struct timecounter *tc;
KASSERT(pps != NULL, ("NULL pps pointer in pps_capture"));
th = timehands;
@@ -2088,17 +2150,18 @@ pps_capture(struct pps_state *pps)
#ifdef FFCLOCK
pps->capffth = fftimehands;
#endif
- pps->capcount = th->th_counter->tc_get_timecount(th->th_counter);
- atomic_thread_fence_acq();
- if (pps->capgen != th->th_generation)
- pps->capgen = 0;
+ tc = th->th_counter;
+ pps->capcount = tc->tc_get_timecount(tc);
}
void
pps_event(struct pps_state *pps, int event)
{
+ struct timehands *capth;
+ struct timecounter *captc;
+ uint64_t capth_scale;
struct bintime bt;
- struct timespec ts, *tsp, *osp;
+ struct timespec *tsp, *osp;
uint32_t tcount, *pcount;
int foff;
pps_seq_t *pseq;
@@ -2115,9 +2178,21 @@ pps_event(struct pps_state *pps, int event)
/* Nothing to do if not currently set to capture this event type. */
if ((event & pps->ppsparam.mode) == 0)
return;
+
+ /* Make a snapshot of the captured timehand */
+ capth = pps->capth;
+ captc = capth->th_counter;
+ capth_scale = capth->th_scale;
+ tcount = capth->th_offset_count;
+ bt = capth->th_bintime;
+
/* If the timecounter was wound up underneath us, bail out. */
- if (pps->capgen == 0 || pps->capgen !=
- atomic_load_acq_int(&pps->capth->th_generation))
+ atomic_thread_fence_acq();
+#if defined(RTEMS_SMP)
+ if (pps->capgen == 0 || pps->capgen != capth->th_generation)
+#else
+ if (pps->capgen != capth->th_generation)
+#endif
return;
/* Things would be easier with arrays. */
@@ -2151,32 +2226,25 @@ pps_event(struct pps_state *pps, int event)
#endif
}
+ *pcount = pps->capcount;
+
/*
* If the timecounter changed, we cannot compare the count values, so
* we have to drop the rest of the PPS-stuff until the next event.
*/
- if (pps->ppstc != pps->capth->th_counter) {
- pps->ppstc = pps->capth->th_counter;
- *pcount = pps->capcount;
+ if (__predict_false(pps->ppstc != captc)) {
+ pps->ppstc = captc;
pps->ppscount[2] = pps->capcount;
return;
}
- /* Convert the count to a timespec. */
- tcount = pps->capcount - pps->capth->th_offset_count;
- tcount &= pps->capth->th_counter->tc_counter_mask;
- bt = pps->capth->th_bintime;
- bintime_addx(&bt, pps->capth->th_scale * tcount);
- bintime2timespec(&bt, &ts);
-
- /* If the timecounter was wound up underneath us, bail out. */
- atomic_thread_fence_acq();
- if (pps->capgen != pps->capth->th_generation)
- return;
-
- *pcount = pps->capcount;
(*pseq)++;
- *tsp = ts;
+
+ /* Convert the count to a timespec. */
+ tcount = pps->capcount - tcount;
+ tcount &= captc->tc_counter_mask;
+ bintime_addx(&bt, capth_scale * tcount);
+ bintime2timespec(&bt, tsp);
if (foff) {
timespecadd(tsp, osp, tsp);
@@ -2191,14 +2259,14 @@ pps_event(struct pps_state *pps, int event)
bt = pps->capffth->tick_time;
ffclock_convert_delta(tcount, pps->capffth->cest.period, &bt);
bintime_add(&bt, &pps->capffth->tick_time);
- bintime2timespec(&bt, &ts);
(*pseq_ffc)++;
- *tsp_ffc = ts;
+ bintime2timespec(&bt, tsp_ffc);
#endif
#ifdef PPS_SYNC
if (fhard) {
- uint64_t scale;
+ uint64_t delta_nsec;
+ uint64_t freq;
/*
* Feed the NTP PLL/FLL.
@@ -2207,24 +2275,23 @@ pps_event(struct pps_state *pps, int event)
*/
tcount = pps->capcount - pps->ppscount[2];
pps->ppscount[2] = pps->capcount;
- tcount &= pps->capth->th_counter->tc_counter_mask;
- scale = (uint64_t)1 << 63;
- scale /= pps->capth->th_counter->tc_frequency;
- scale *= 2;
- bt.sec = 0;
- bt.frac = 0;
- bintime_addx(&bt, scale * tcount);
- bintime2timespec(&bt, &ts);
- hardpps(tsp, ts.tv_nsec + 1000000000 * ts.tv_sec);
+ tcount &= captc->tc_counter_mask;
+ delta_nsec = 1000000000;
+ delta_nsec *= tcount;
+ freq = captc->tc_frequency;
+ delta_nsec = (delta_nsec + freq / 2) / freq;
+ hardpps(tsp, (long)delta_nsec);
}
#endif
/* Wakeup anyone sleeping in pps_fetch(). */
+#ifndef __rtems__
wakeup(pps);
-}
#else /* __rtems__ */
-/* FIXME: https://devel.rtems.org/ticket/2349 */
+ _Assert(pps->wakeup != NULL);
+ (*pps->wakeup)(pps);
#endif /* __rtems__ */
+}
/*
* Timecounters need to be updated every so often to prevent the hardware
@@ -2260,9 +2327,13 @@ _Timecounter_Tick(void)
{
Per_CPU_Control *cpu_self = _Per_CPU_Get();
+#if defined(RTEMS_SMP)
if (_Per_CPU_Is_boot_processor(cpu_self)) {
+#endif
tc_windup(NULL);
+#if defined(RTEMS_SMP)
}
+#endif
_Watchdog_Tick(cpu_self);
}
@@ -2424,7 +2495,7 @@ SYSINIT(timecounter, SI_SUB_CLOCKS, SI_ORDER_SECOND, inittimecounter, NULL);
/* Cpu tick handling -------------------------------------------------*/
-static int cpu_tick_variable;
+static bool cpu_tick_variable;
static uint64_t cpu_tick_frequency;
DPCPU_DEFINE_STATIC(uint64_t, tc_cpu_ticks_base);
@@ -2517,14 +2588,14 @@ cpu_tick_calibrate(int reset)
}
void
-set_cputicker(cpu_tick_f *func, uint64_t freq, unsigned var)
+set_cputicker(cpu_tick_f *func, uint64_t freq, bool isvariable)
{
if (func == NULL) {
cpu_ticks = tc_cpu_ticks;
} else {
cpu_tick_frequency = freq;
- cpu_tick_variable = var;
+ cpu_tick_variable = isvariable;
cpu_ticks = func;
}
}
@@ -2544,20 +2615,14 @@ cpu_tickrate(void)
* years) and in 64 bits at 4 GHz (146 years), but if we do a multiply
* before divide conversion (to retain precision) we find that the
* margin shrinks to 1.5 hours (one millionth of 146y).
- * With a three prong approach we never lose significant bits, no
- * matter what the cputick rate and length of timeinterval is.
*/
uint64_t
cputick2usec(uint64_t tick)
{
-
- if (tick > 18446744073709551LL) /* floor(2^64 / 1000) */
- return (tick / (cpu_tickrate() / 1000000LL));
- else if (tick > 18446744073709LL) /* floor(2^64 / 1000000) */
- return ((tick * 1000LL) / (cpu_tickrate() / 1000LL));
- else
- return ((tick * 1000000LL) / cpu_tickrate());
+ uint64_t tr;
+ tr = cpu_tickrate();
+ return ((tick / tr) * 1000000ULL) + ((tick % tr) * 1000000ULL) / tr;
}
cpu_tick_f *cpu_ticks = tc_cpu_ticks;
diff --git a/cpukit/score/src/libatomic.c b/cpukit/score/src/libatomic.c
index a586d4815e..fc0e3032ec 100644
--- a/cpukit/score/src/libatomic.c
+++ b/cpukit/score/src/libatomic.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2016 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/memoryallocate.c b/cpukit/score/src/memoryallocate.c
index e2aed7aa1d..791826ca6e 100644
--- a/cpukit/score/src/memoryallocate.c
+++ b/cpukit/score/src/memoryallocate.c
@@ -10,7 +10,7 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
- * Copyright (C) 2018, 2019 embedded brains GmbH
+ * Copyright (C) 2018, 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/memorydirtyfreeareas.c b/cpukit/score/src/memorydirtyfreeareas.c
index fc6c2630bf..885c2a503c 100644
--- a/cpukit/score/src/memorydirtyfreeareas.c
+++ b/cpukit/score/src/memorydirtyfreeareas.c
@@ -10,7 +10,7 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
- * Copyright (C) 2020 embedded brains GmbH
+ * Copyright (C) 2020, 2022 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -40,7 +40,14 @@
#include <rtems/score/memory.h>
+#include <string.h>
+
void _Memory_Dirty_free_areas( void )
{
_Memory_Fill( _Memory_Get(), 0xcf );
+ memset(
+ _Memory_Noinit_begin,
+ 0xcf,
+ (uintptr_t) _Memory_Noinit_end - (uintptr_t) _Memory_Noinit_begin
+ );
}
diff --git a/cpukit/score/src/memoryfill.c b/cpukit/score/src/memoryfill.c
index 617bf6911e..e9550d52d6 100644
--- a/cpukit/score/src/memoryfill.c
+++ b/cpukit/score/src/memoryfill.c
@@ -10,7 +10,7 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
- * Copyright (C) 2019 embedded brains GmbH
+ * Copyright (C) 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpuatomic.h b/cpukit/score/src/memorynoinit.c
index ed8091d73c..22c537820d 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpuatomic.h
+++ b/cpukit/score/src/memorynoinit.c
@@ -1,16 +1,16 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
/**
* @file
*
- * @ingroup RTEMSScoreCPU
+ * @ingroup RTEMSScoreMemory
*
- * @brief AArch64 Atomics support
+ * @brief This source file contains the definition of ::_Memory_Noinit_begin
+ * and ::_Memory_Noinit_end.
*/
/*
- * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
- * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2022 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -34,9 +34,12 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <rtems/score/memory.h>
-#include <rtems/score/cpustdatomic.h>
+RTEMS_SECTION( ".noinit.rtems.begin" ) char _Memory_Noinit_begin[ 0 ];
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
+RTEMS_SECTION( ".noinit.rtems.end" ) char _Memory_Noinit_end[ 0 ];
diff --git a/cpukit/score/src/memoryzerobeforeuse.c b/cpukit/score/src/memoryzerobeforeuse.c
index 9143cd9c7d..6893600db9 100644
--- a/cpukit/score/src/memoryzerobeforeuse.c
+++ b/cpukit/score/src/memoryzerobeforeuse.c
@@ -10,7 +10,7 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
- * Copyright (C) 2020 embedded brains GmbH
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/memoryzerofreeareas.c b/cpukit/score/src/memoryzerofreeareas.c
index 4ea0812426..08e11c41d4 100644
--- a/cpukit/score/src/memoryzerofreeareas.c
+++ b/cpukit/score/src/memoryzerofreeareas.c
@@ -10,7 +10,7 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
- * Copyright (C) 2020 embedded brains GmbH
+ * Copyright (C) 2020, 2022 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -40,7 +40,14 @@
#include <rtems/score/memory.h>
+#include <string.h>
+
void _Memory_Zero_free_areas( void )
{
_Memory_Fill( _Memory_Get(), 0 );
+ memset(
+ _Memory_Noinit_begin,
+ 0,
+ (uintptr_t) _Memory_Noinit_end - (uintptr_t) _Memory_Noinit_begin
+ );
}
diff --git a/cpukit/score/src/mpci.c b/cpukit/score/src/mpci.c
index 3b525a2066..458031c794 100644
--- a/cpukit/score/src/mpci.c
+++ b/cpukit/score/src/mpci.c
@@ -162,7 +162,7 @@ static void _MPCI_Create_server( void )
memset( &config, 0, sizeof( config ) );
config.scheduler = &_Scheduler_Table[ 0 ];
config.name = _Objects_Build_name( 'M', 'P', 'C', 'I' );
- config.priority = PRIORITY_PSEUDO_ISR;
+ config.priority = PRIORITY_MINIMUM;
config.is_fp = CPU_ALL_TASKS_ARE_FP;
config.stack_size = _Stack_Minimum()
+ _MPCI_Configuration.extra_mpci_receive_server_stack
diff --git a/cpukit/score/src/mutex.c b/cpukit/score/src/mutex.c
index 6708962b8e..40e6baa12c 100644
--- a/cpukit/score/src/mutex.c
+++ b/cpukit/score/src/mutex.c
@@ -13,7 +13,7 @@
*/
/*
- * Copyright (c) 2015, 2016 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2015, 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/objectactivecount.c b/cpukit/score/src/objectactivecount.c
index 028058e473..258ad6b49d 100644
--- a/cpukit/score/src/objectactivecount.c
+++ b/cpukit/score/src/objectactivecount.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -46,14 +46,22 @@ Objects_Maximum _Objects_Active_count(
const Objects_Information *information
)
{
- Objects_Maximum inactive;
- Objects_Maximum maximum;
+ Objects_Maximum active;
+ Objects_Maximum index;
+ Objects_Maximum maximum;
+ Objects_Control **local_table;
_Assert( _Objects_Allocator_is_owner() );
- inactive = (Objects_Maximum)
- _Chain_Node_count_unprotected( &information->Inactive );
+ active = 0;
maximum = _Objects_Get_maximum_index( information );
+ local_table = information->local_table;
- return maximum - inactive;
+ for ( index = 0; index < maximum; ++index ) {
+ if ( local_table[ index ] != NULL ) {
+ ++active;
+ }
+ }
+
+ return active;
}
diff --git a/cpukit/score/src/objectallocate.c b/cpukit/score/src/objectallocate.c
index ba126d2533..7f3f651ea0 100644
--- a/cpukit/score/src/objectallocate.c
+++ b/cpukit/score/src/objectallocate.c
@@ -10,7 +10,7 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
- * Copyright (C) 2014 embedded brains GmbH
+ * Copyright (C) 2014 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/objectallocatenone.c b/cpukit/score/src/objectallocatenone.c
index a1bead5f79..e8c0b49df4 100644
--- a/cpukit/score/src/objectallocatenone.c
+++ b/cpukit/score/src/objectallocatenone.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2019 embedded brains GmbH
+ * Copyright (C) 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/objectallocatestatic.c b/cpukit/score/src/objectallocatestatic.c
index 0521c8191f..3296e08ce5 100644
--- a/cpukit/score/src/objectallocatestatic.c
+++ b/cpukit/score/src/objectallocatestatic.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2019 embedded brains GmbH
+ * Copyright (C) 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/objectallocateunlimited.c b/cpukit/score/src/objectallocateunlimited.c
index 274a69640b..f317da9668 100644
--- a/cpukit/score/src/objectallocateunlimited.c
+++ b/cpukit/score/src/objectallocateunlimited.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2020 embedded brains GmbH
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/objectextendinformation.c b/cpukit/score/src/objectextendinformation.c
index 414766f219..9a627b1a7c 100644
--- a/cpukit/score/src/objectextendinformation.c
+++ b/cpukit/score/src/objectextendinformation.c
@@ -59,7 +59,7 @@ Objects_Maximum _Objects_Extend_information(
uint32_t index_base;
uint32_t index_end;
uint32_t index;
- Objects_Maximum extend_count;
+ uint32_t extend_count;
Objects_Maximum old_maximum;
uint32_t new_maximum;
size_t object_block_size;
diff --git a/cpukit/score/src/objectfree.c b/cpukit/score/src/objectfree.c
index 45b2ba2c86..06d7d82672 100644
--- a/cpukit/score/src/objectfree.c
+++ b/cpukit/score/src/objectfree.c
@@ -51,14 +51,16 @@ void _Objects_Free_unlimited(
if ( _Objects_Is_auto_extend( information ) ) {
Objects_Maximum objects_per_block;
- Objects_Maximum block;
- Objects_Maximum inactive;
+ Objects_Maximum index;
objects_per_block = information->objects_per_block;
- block = _Objects_Get_index( the_object->id ) - OBJECTS_INDEX_MINIMUM;
+ index = _Objects_Get_index( the_object->id ) - OBJECTS_INDEX_MINIMUM;
- if ( block > objects_per_block ) {
- block /= objects_per_block;
+ if ( _Objects_Is_in_allocated_block( index, objects_per_block ) ) {
+ Objects_Maximum block;
+ Objects_Maximum inactive;
+
+ block = index / objects_per_block;
++information->inactive_per_block[ block ];
diff --git a/cpukit/score/src/objectfreenothing.c b/cpukit/score/src/objectfreenothing.c
index 0845d4c140..941a7514af 100644
--- a/cpukit/score/src/objectfreenothing.c
+++ b/cpukit/score/src/objectfreenothing.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/objectfreestatic.c b/cpukit/score/src/objectfreestatic.c
index 4bdc0e1071..94bf906edd 100644
--- a/cpukit/score/src/objectfreestatic.c
+++ b/cpukit/score/src/objectfreestatic.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2019 embedded brains GmbH
+ * Copyright (C) 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/objectgetlocal.c b/cpukit/score/src/objectgetlocal.c
index 16b52150f8..1aad28efa1 100644
--- a/cpukit/score/src/objectgetlocal.c
+++ b/cpukit/score/src/objectgetlocal.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2016 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/objectinitializeinformation.c b/cpukit/score/src/objectinitializeinformation.c
index 3482f2871e..7c1bfd877f 100644
--- a/cpukit/score/src/objectinitializeinformation.c
+++ b/cpukit/score/src/objectinitializeinformation.c
@@ -42,7 +42,6 @@
#include <rtems/score/objectimpl.h>
#include <rtems/score/address.h>
#include <rtems/score/chainimpl.h>
-#include <rtems/score/interr.h>
#include <rtems/score/sysstate.h>
void _Objects_Initialize_information(
diff --git a/cpukit/score/src/once.c b/cpukit/score/src/once.c
index f3a29e5ec5..a395197c3a 100644
--- a/cpukit/score/src/once.c
+++ b/cpukit/score/src/once.c
@@ -10,7 +10,7 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
- * Copyright (C) 2019 embedded brains GmbH
+ * Copyright (C) 2019 embedded brains GmbH & Co. KG
* Copyright (C) 2019 Sebastian Huber
*
* Redistribution and use in source and binary forms, with or without
diff --git a/cpukit/score/src/opt_compat.h b/cpukit/score/src/opt_compat.h
index 13b719ccf8..db479044f3 100644
--- a/cpukit/score/src/opt_compat.h
+++ b/cpukit/score/src/opt_compat.h
@@ -9,7 +9,7 @@
*/
/*
- * Copyright (C) 2015 embedded brains Gmbh (http://www.embedded-brains.de)
+ * Copyright (C) 2015 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/opt_ffclock.h b/cpukit/score/src/opt_ffclock.h
index 13b719ccf8..db479044f3 100644
--- a/cpukit/score/src/opt_ffclock.h
+++ b/cpukit/score/src/opt_ffclock.h
@@ -9,7 +9,7 @@
*/
/*
- * Copyright (C) 2015 embedded brains Gmbh (http://www.embedded-brains.de)
+ * Copyright (C) 2015 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/opt_ntp.h b/cpukit/score/src/opt_ntp.h
index 13b719ccf8..db479044f3 100644
--- a/cpukit/score/src/opt_ntp.h
+++ b/cpukit/score/src/opt_ntp.h
@@ -9,7 +9,7 @@
*/
/*
- * Copyright (C) 2015 embedded brains Gmbh (http://www.embedded-brains.de)
+ * Copyright (C) 2015 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/percpuasm.c b/cpukit/score/src/percpuasm.c
index 6e5a727b76..01ad50a352 100644
--- a/cpukit/score/src/percpuasm.c
+++ b/cpukit/score/src/percpuasm.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2012, 2016 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2012, 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -44,7 +44,7 @@
#include <rtems/score/percpu.h>
#define PER_CPU_IS_POWER_OF_TWO( value ) \
- ( ( ( ( value ) - 1 ) & ( value ) ) == 0 )
+ ( ( value ) > 1 && ( ( ( value ) - 1 ) & ( value ) ) == 0 )
/*
* The minimum alignment of two is due to the Heap Handler which uses the
@@ -73,6 +73,11 @@ RTEMS_STATIC_ASSERT(
);
RTEMS_STATIC_ASSERT(
+ PER_CPU_IS_POWER_OF_TWO( CPU_STACK_MINIMUM_SIZE ),
+ CPU_STACK_MINIMUM_SIZE
+);
+
+RTEMS_STATIC_ASSERT(
sizeof(void *) == CPU_SIZEOF_POINTER,
CPU_SIZEOF_POINTER
);
diff --git a/cpukit/score/src/percpudata.c b/cpukit/score/src/percpudata.c
index c81c1b6a16..0dda6bdf1d 100644
--- a/cpukit/score/src/percpudata.c
+++ b/cpukit/score/src/percpudata.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2019, 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2019, 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -66,14 +66,19 @@ static void _Per_CPU_Data_initialize( void )
size = RTEMS_LINKER_SET_SIZE( _Per_CPU_Data );
if ( size > 0 ) {
+ char *data_begin;
const Memory_Information *mem;
Per_CPU_Control *cpu;
uint32_t cpu_index;
uint32_t cpu_max;
+ /* Prevent an out of bounds warning in the memcpy() below */
+ data_begin = RTEMS_LINKER_SET_BEGIN( _Per_CPU_Data );
+ RTEMS_OBFUSCATE_VARIABLE( data_begin );
+
mem = _Memory_Get();
cpu = _Per_CPU_Get_by_index( 0 );
- cpu->data = RTEMS_LINKER_SET_BEGIN( _Per_CPU_Data );
+ cpu->data = data_begin;
cpu_max = rtems_configuration_get_maximum_processors();
@@ -85,7 +90,7 @@ static void _Per_CPU_Data_initialize( void )
_Internal_error( INTERNAL_ERROR_NO_MEMORY_FOR_PER_CPU_DATA );
}
- memcpy( cpu->data, RTEMS_LINKER_SET_BEGIN( _Per_CPU_Data ), size);
+ memcpy( cpu->data, data_begin, size);
}
}
}
diff --git a/cpukit/score/src/percpujobs.c b/cpukit/score/src/percpujobs.c
index 3de3e4a7bd..0266bd5399 100644
--- a/cpukit/score/src/percpujobs.c
+++ b/cpukit/score/src/percpujobs.c
@@ -11,7 +11,7 @@
*/
/*
- * Copyright (C) 2019 embedded brains GmbH
+ * Copyright (C) 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/percpustatewait.c b/cpukit/score/src/percpustatewait.c
index cfeda7384b..54ab92427f 100644
--- a/cpukit/score/src/percpustatewait.c
+++ b/cpukit/score/src/percpustatewait.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2014 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2014 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/pheapiterate.c b/cpukit/score/src/pheapiterate.c
deleted file mode 100644
index a709e80335..0000000000
--- a/cpukit/score/src/pheapiterate.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/**
- * @file
- *
- * @ingroup RTEMSScoreProtHeap
- *
- * @brief This source file contains the implementation of
- * _Protected_heap_Iterate().
- */
-
-/*
- * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <rtems/score/protectedheap.h>
-
-void _Protected_heap_Iterate(
- Heap_Control *heap,
- Heap_Block_visitor visitor,
- void *visitor_arg
-)
-{
- _RTEMS_Lock_allocator();
- _Heap_Iterate( heap, visitor, visitor_arg );
- _RTEMS_Unlock_allocator();
-}
diff --git a/cpukit/score/src/pheapresizeblock.c b/cpukit/score/src/pheapresizeblock.c
deleted file mode 100644
index ffd765e860..0000000000
--- a/cpukit/score/src/pheapresizeblock.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/**
- * @file
- *
- * @ingroup RTEMSScoreProtHeap
- *
- * @brief This source file contains the implementation of
- * _Protected_heap_Resize_block().
- */
-
-/*
- * COPYRIGHT (c) 1989-2007.
- * On-Line Applications Research Corporation (OAR).
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <rtems/score/protectedheap.h>
-
-bool _Protected_heap_Resize_block(
- Heap_Control *the_heap,
- void *starting_address,
- uintptr_t size
-)
-{
- Heap_Resize_status status;
- uintptr_t old_mem_size;
- uintptr_t avail_mem_size;
-
- _RTEMS_Lock_allocator();
- status = _Heap_Resize_block(
- the_heap, starting_address, size, &old_mem_size, &avail_mem_size );
- _RTEMS_Unlock_allocator();
- return (status == HEAP_RESIZE_SUCCESSFUL);
-}
-
diff --git a/cpukit/score/src/processormaskcopy.c b/cpukit/score/src/processormaskcopy.c
index 8697edfa5c..863bd1574e 100644
--- a/cpukit/score/src/processormaskcopy.c
+++ b/cpukit/score/src/processormaskcopy.c
@@ -11,7 +11,7 @@
*/
/*
- * Copyright (c) 2017 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/profilingisrentryexit.c b/cpukit/score/src/profilingisrentryexit.c
index 2619bdc0c0..64905e5a42 100644
--- a/cpukit/score/src/profilingisrentryexit.c
+++ b/cpukit/score/src/profilingisrentryexit.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2014, 2016 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2014, 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -54,10 +54,7 @@ void _Profiling_Outer_most_interrupt_entry_and_exit(
_Assert( cpu->isr_nest_level == 1 );
stats = &cpu->Stats;
- delta = _CPU_Counter_difference(
- interrupt_exit_instant,
- interrupt_entry_instant
- );
+ delta = interrupt_exit_instant - interrupt_entry_instant;
++stats->interrupt_count;
stats->total_interrupt_time += delta;
diff --git a/cpukit/score/src/profilingsmplock.c b/cpukit/score/src/profilingsmplock.c
index 5c5b4d9196..af9d1cd22b 100644
--- a/cpukit/score/src/profilingsmplock.c
+++ b/cpukit/score/src/profilingsmplock.c
@@ -12,7 +12,7 @@
*/
/*
- * Copyright (c) 2014, 2018 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2014, 2018 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/rbtreeappend.c b/cpukit/score/src/rbtreeappend.c
index e36f6bc805..5ce7094b9d 100644
--- a/cpukit/score/src/rbtreeappend.c
+++ b/cpukit/score/src/rbtreeappend.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/rbtreeiterate.c b/cpukit/score/src/rbtreeiterate.c
index 496c058f32..f13a5db0af 100644
--- a/cpukit/score/src/rbtreeiterate.c
+++ b/cpukit/score/src/rbtreeiterate.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2012 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/rbtreemax.c b/cpukit/score/src/rbtreemax.c
index 1b0e463aa2..71f856bafd 100644
--- a/cpukit/score/src/rbtreemax.c
+++ b/cpukit/score/src/rbtreemax.c
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
/**
* @file
*
@@ -8,7 +10,7 @@
*/
/*
- * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/rbtreemin.c b/cpukit/score/src/rbtreemin.c
index b3cd4331c1..d82e1b2280 100644
--- a/cpukit/score/src/rbtreemin.c
+++ b/cpukit/score/src/rbtreemin.c
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
/**
* @file
*
@@ -8,7 +10,7 @@
*/
/*
- * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/rbtreenext.c b/cpukit/score/src/rbtreenext.c
index 5d43af0068..a7314ac095 100644
--- a/cpukit/score/src/rbtreenext.c
+++ b/cpukit/score/src/rbtreenext.c
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
/**
* @file
*
@@ -9,7 +11,7 @@
*/
/*
- * Copyright (C) 2012 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2012 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/rbtreepostorder.c b/cpukit/score/src/rbtreepostorder.c
index 2239838813..8e5cb2a788 100644
--- a/cpukit/score/src/rbtreepostorder.c
+++ b/cpukit/score/src/rbtreepostorder.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2018 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2018 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/rbtreeprepend.c b/cpukit/score/src/rbtreeprepend.c
index f154f51d36..a637461de5 100644
--- a/cpukit/score/src/rbtreeprepend.c
+++ b/cpukit/score/src/rbtreeprepend.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/rbtreeprev.c b/cpukit/score/src/rbtreeprev.c
index 9869cade99..9d417a79ff 100644
--- a/cpukit/score/src/rbtreeprev.c
+++ b/cpukit/score/src/rbtreeprev.c
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
/**
* @file
*
@@ -8,7 +10,7 @@
*/
/*
- * Copyright (C) 2012 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2012 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/rbtreereplace.c b/cpukit/score/src/rbtreereplace.c
index b7448d4f3f..4a022f5b69 100644
--- a/cpukit/score/src/rbtreereplace.c
+++ b/cpukit/score/src/rbtreereplace.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2015 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2015 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/sched.c b/cpukit/score/src/sched.c
index fcc1d399dd..f2ec838bb2 100644
--- a/cpukit/score/src/sched.c
+++ b/cpukit/score/src/sched.c
@@ -11,7 +11,7 @@
*/
/*
- * Copyright (c) 2015 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2015 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/schedulerdefaultmakecleansticky.c b/cpukit/score/src/schedulerdefaultmakecleansticky.c
index e2b2d659f1..51c893d510 100644
--- a/cpukit/score/src/schedulerdefaultmakecleansticky.c
+++ b/cpukit/score/src/schedulerdefaultmakecleansticky.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/schedulerdefaultmappriority.c b/cpukit/score/src/schedulerdefaultmappriority.c
index 015aee9fec..309f6b504b 100644
--- a/cpukit/score/src/schedulerdefaultmappriority.c
+++ b/cpukit/score/src/schedulerdefaultmappriority.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2016, 2017 embedded brains GmbH
+ * Copyright (C) 2016, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/schedulerdefaultpinunpin.c b/cpukit/score/src/schedulerdefaultpinunpin.c
index df41a29dcb..f39e5f7db5 100644
--- a/cpukit/score/src/schedulerdefaultpinunpin.c
+++ b/cpukit/score/src/schedulerdefaultpinunpin.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2018 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2018 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/schedulerdefaultpinunpindonothing.c b/cpukit/score/src/schedulerdefaultpinunpindonothing.c
index f3ecb0b718..b7b2a136a8 100644
--- a/cpukit/score/src/schedulerdefaultpinunpindonothing.c
+++ b/cpukit/score/src/schedulerdefaultpinunpindonothing.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2018 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2018 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/schedulerdefaultschedule.c b/cpukit/score/src/schedulerdefaultschedule.c
index a96055cd02..151b50a9fa 100644
--- a/cpukit/score/src/schedulerdefaultschedule.c
+++ b/cpukit/score/src/schedulerdefaultschedule.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2014 embedded brains GmbH
+ * Copyright (c) 2014 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/schedulerdefaultstartidle.c b/cpukit/score/src/schedulerdefaultstartidle.c
index 4cd4de2b47..64fc967619 100644
--- a/cpukit/score/src/schedulerdefaultstartidle.c
+++ b/cpukit/score/src/schedulerdefaultstartidle.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2013-2014 embedded brains GmbH
+ * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/scheduleredfblock.c b/cpukit/score/src/scheduleredfblock.c
index 56f7c9c021..cb7ab91450 100644
--- a/cpukit/score/src/scheduleredfblock.c
+++ b/cpukit/score/src/scheduleredfblock.c
@@ -47,11 +47,11 @@ void _Scheduler_EDF_Block(
Scheduler_Node *node
)
{
- _Scheduler_Generic_block(
+ _Scheduler_uniprocessor_Block(
scheduler,
the_thread,
node,
_Scheduler_EDF_Extract_body,
- _Scheduler_EDF_Schedule_body
+ _Scheduler_EDF_Get_highest_ready
);
}
diff --git a/cpukit/score/src/scheduleredfchangepriority.c b/cpukit/score/src/scheduleredfchangepriority.c
index 26ce1c348f..de17ca0fad 100644
--- a/cpukit/score/src/scheduleredfchangepriority.c
+++ b/cpukit/score/src/scheduleredfchangepriority.c
@@ -71,5 +71,8 @@ void _Scheduler_EDF_Update_priority(
_Scheduler_EDF_Extract( context, the_node );
_Scheduler_EDF_Enqueue( context, the_node, insert_priority );
- _Scheduler_EDF_Schedule_body( scheduler, the_thread, false );
+ _Scheduler_uniprocessor_Schedule(
+ scheduler,
+ _Scheduler_EDF_Get_highest_ready
+ );
}
diff --git a/cpukit/score/src/scheduleredfschedule.c b/cpukit/score/src/scheduleredfschedule.c
index d0acea7a30..40c5ab2c06 100644
--- a/cpukit/score/src/scheduleredfschedule.c
+++ b/cpukit/score/src/scheduleredfschedule.c
@@ -46,5 +46,8 @@ void _Scheduler_EDF_Schedule(
Thread_Control *the_thread
)
{
- _Scheduler_EDF_Schedule_body( scheduler, the_thread, false );
+ _Scheduler_uniprocessor_Schedule(
+ scheduler,
+ _Scheduler_EDF_Get_highest_ready
+ );
}
diff --git a/cpukit/score/src/scheduleredfsmp.c b/cpukit/score/src/scheduleredfsmp.c
index 59b222df74..07b28042d7 100644
--- a/cpukit/score/src/scheduleredfsmp.c
+++ b/cpukit/score/src/scheduleredfsmp.c
@@ -18,7 +18,7 @@
*/
/*
- * Copyright (c) 2017 embedded brains GmbH.
+ * Copyright (c) 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/scheduleredfunblock.c b/cpukit/score/src/scheduleredfunblock.c
index d6604686e3..4638eedf71 100644
--- a/cpukit/score/src/scheduleredfunblock.c
+++ b/cpukit/score/src/scheduleredfunblock.c
@@ -62,23 +62,5 @@ void _Scheduler_EDF_Unblock(
the_node->priority = priority;
_Scheduler_EDF_Enqueue( context, the_node, insert_priority );
-
- /*
- * If the thread that was unblocked is more important than the heir,
- * then we have a new heir. This may or may not result in a
- * context switch.
- *
- * Normal case:
- * If the current thread is preemptible, then we need to do
- * a context switch.
- * Pseudo-ISR case:
- * Even if the thread isn't preemptible, if the new heir is
- * a pseudo-ISR system task, we need to do a context switch.
- */
- if ( priority < _Thread_Get_priority( _Thread_Heir ) ) {
- _Scheduler_Update_heir(
- the_thread,
- priority == ( SCHEDULER_EDF_PRIO_MSB | PRIORITY_PSEUDO_ISR )
- );
- }
+ _Scheduler_uniprocessor_Unblock( scheduler, the_thread, priority );
}
diff --git a/cpukit/score/src/scheduleredfyield.c b/cpukit/score/src/scheduleredfyield.c
index d83e1d9268..d38bea705a 100644
--- a/cpukit/score/src/scheduleredfyield.c
+++ b/cpukit/score/src/scheduleredfyield.c
@@ -55,5 +55,5 @@ void _Scheduler_EDF_Yield(
_Scheduler_EDF_Extract( context, the_node );
_Scheduler_EDF_Enqueue( context, the_node, the_node->priority );
- _Scheduler_EDF_Schedule_body( scheduler, the_thread, true );
+ _Scheduler_uniprocessor_Yield( scheduler, _Scheduler_EDF_Get_highest_ready );
}
diff --git a/cpukit/score/src/schedulergetaffinity.c b/cpukit/score/src/schedulergetaffinity.c
index dac73c230f..28dc514499 100644
--- a/cpukit/score/src/schedulergetaffinity.c
+++ b/cpukit/score/src/schedulergetaffinity.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2014, 2017 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2014, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/schedulerpriorityblock.c b/cpukit/score/src/schedulerpriorityblock.c
index 53636940dc..ffc7a3ad86 100644
--- a/cpukit/score/src/schedulerpriorityblock.c
+++ b/cpukit/score/src/schedulerpriorityblock.c
@@ -49,11 +49,11 @@ void _Scheduler_priority_Block(
Scheduler_Node *node
)
{
- _Scheduler_Generic_block(
+ _Scheduler_uniprocessor_Block(
scheduler,
the_thread,
node,
_Scheduler_priority_Extract_body,
- _Scheduler_priority_Schedule_body
+ _Scheduler_priority_Get_highest_ready
);
}
diff --git a/cpukit/score/src/schedulerprioritychangepriority.c b/cpukit/score/src/schedulerprioritychangepriority.c
index 8a059763de..3588a2ce42 100644
--- a/cpukit/score/src/schedulerprioritychangepriority.c
+++ b/cpukit/score/src/schedulerprioritychangepriority.c
@@ -96,5 +96,8 @@ void _Scheduler_priority_Update_priority(
);
}
- _Scheduler_priority_Schedule_body( scheduler, the_thread, false );
+ _Scheduler_uniprocessor_Schedule(
+ scheduler,
+ _Scheduler_priority_Get_highest_ready
+ );
}
diff --git a/cpukit/score/src/schedulerpriorityschedule.c b/cpukit/score/src/schedulerpriorityschedule.c
index bde749f9bc..bb7cf87399 100644
--- a/cpukit/score/src/schedulerpriorityschedule.c
+++ b/cpukit/score/src/schedulerpriorityschedule.c
@@ -46,5 +46,8 @@ void _Scheduler_priority_Schedule(
Thread_Control *the_thread
)
{
- _Scheduler_priority_Schedule_body( scheduler, the_thread, false );
+ _Scheduler_uniprocessor_Schedule(
+ scheduler,
+ _Scheduler_priority_Get_highest_ready
+ );
}
diff --git a/cpukit/score/src/schedulerprioritysmp.c b/cpukit/score/src/schedulerprioritysmp.c
index 5858c9a910..1d3ed4f110 100644
--- a/cpukit/score/src/schedulerprioritysmp.c
+++ b/cpukit/score/src/schedulerprioritysmp.c
@@ -21,7 +21,7 @@
*/
/*
- * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/schedulerpriorityunblock.c b/cpukit/score/src/schedulerpriorityunblock.c
index 190c126908..f9b6cabff7 100644
--- a/cpukit/score/src/schedulerpriorityunblock.c
+++ b/cpukit/score/src/schedulerpriorityunblock.c
@@ -76,19 +76,5 @@ void _Scheduler_priority_Unblock (
/* TODO: flash critical section? */
- /*
- * If the thread that was unblocked is more important than the heir,
- * then we have a new heir. This may or may not result in a
- * context switch.
- *
- * Normal case:
- * If the current thread is preemptible, then we need to do
- * a context switch.
- * Pseudo-ISR case:
- * Even if the thread isn't preemptible, if the new heir is
- * a pseudo-ISR system task, we need to do a context switch.
- */
- if ( priority < _Thread_Get_priority( _Thread_Heir ) ) {
- _Scheduler_Update_heir( the_thread, priority == PRIORITY_PSEUDO_ISR );
- }
+ _Scheduler_uniprocessor_Unblock( scheduler, the_thread, priority );
}
diff --git a/cpukit/score/src/schedulerpriorityyield.c b/cpukit/score/src/schedulerpriorityyield.c
index 77fcecc418..adb443df94 100644
--- a/cpukit/score/src/schedulerpriorityyield.c
+++ b/cpukit/score/src/schedulerpriorityyield.c
@@ -59,5 +59,8 @@ void _Scheduler_priority_Yield(
_Chain_Append_unprotected( ready_chain, &the_thread->Object.Node );
}
- _Scheduler_priority_Schedule_body( scheduler, the_thread, true );
+ _Scheduler_uniprocessor_Yield(
+ scheduler,
+ _Scheduler_priority_Get_highest_ready
+ );
}
diff --git a/cpukit/score/src/schedulersetaffinity.c b/cpukit/score/src/schedulersetaffinity.c
index 0563e458c0..45b62d7024 100644
--- a/cpukit/score/src/schedulersetaffinity.c
+++ b/cpukit/score/src/schedulersetaffinity.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2014, 2017 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2014, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/schedulersimpleblock.c b/cpukit/score/src/schedulersimpleblock.c
index a8229d409f..dfd18df3a2 100644
--- a/cpukit/score/src/schedulersimpleblock.c
+++ b/cpukit/score/src/schedulersimpleblock.c
@@ -47,11 +47,11 @@ void _Scheduler_simple_Block(
Scheduler_Node *node
)
{
- _Scheduler_Generic_block(
+ _Scheduler_uniprocessor_Block(
scheduler,
the_thread,
node,
_Scheduler_simple_Extract,
- _Scheduler_simple_Schedule_body
+ _Scheduler_simple_Get_highest_ready
);
}
diff --git a/cpukit/score/src/schedulersimplechangepriority.c b/cpukit/score/src/schedulersimplechangepriority.c
index b4711dfd01..5c53c96fb3 100644
--- a/cpukit/score/src/schedulersimplechangepriority.c
+++ b/cpukit/score/src/schedulersimplechangepriority.c
@@ -60,5 +60,8 @@ void _Scheduler_simple_Update_priority(
_Scheduler_simple_Extract( scheduler, the_thread, node );
_Scheduler_simple_Insert( &context->Ready, the_thread, new_priority );
- _Scheduler_simple_Schedule_body( scheduler, the_thread, false );
+ _Scheduler_uniprocessor_Schedule(
+ scheduler,
+ _Scheduler_simple_Get_highest_ready
+ );
}
diff --git a/cpukit/score/src/schedulersimpleschedule.c b/cpukit/score/src/schedulersimpleschedule.c
index 4108fdaee8..83a3fed7fe 100644
--- a/cpukit/score/src/schedulersimpleschedule.c
+++ b/cpukit/score/src/schedulersimpleschedule.c
@@ -46,5 +46,8 @@ void _Scheduler_simple_Schedule(
Thread_Control *the_thread
)
{
- _Scheduler_simple_Schedule_body( scheduler, the_thread, false );
+ _Scheduler_uniprocessor_Schedule(
+ scheduler,
+ _Scheduler_simple_Get_highest_ready
+ );
}
diff --git a/cpukit/score/src/schedulersimplesmp.c b/cpukit/score/src/schedulersimplesmp.c
index 572252c2fa..eed96617b2 100644
--- a/cpukit/score/src/schedulersimplesmp.c
+++ b/cpukit/score/src/schedulersimplesmp.c
@@ -19,7 +19,7 @@
*/
/*
- * Copyright (c) 2013, 2016 embedded brains GmbH.
+ * Copyright (C) 2013, 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/schedulersimpleunblock.c b/cpukit/score/src/schedulersimpleunblock.c
index 7791503d7a..436f20ac38 100644
--- a/cpukit/score/src/schedulersimpleunblock.c
+++ b/cpukit/score/src/schedulersimpleunblock.c
@@ -58,23 +58,5 @@ void _Scheduler_simple_Unblock(
priority = _Thread_Get_priority( the_thread );
insert_priority = SCHEDULER_PRIORITY_APPEND( priority );
_Scheduler_simple_Insert( &context->Ready, the_thread, insert_priority );
-
- /*
- * If the thread that was unblocked is more important than the heir,
- * then we have a new heir. This may or may not result in a
- * context switch.
- *
- * Normal case:
- * If the current thread is preemptible, then we need to do
- * a context switch.
- * Pseudo-ISR case:
- * Even if the thread isn't preemptible, if the new heir is
- * a pseudo-ISR system task, we need to do a context switch.
- */
- if ( priority < _Thread_Get_priority( _Thread_Heir ) ) {
- _Scheduler_Update_heir(
- the_thread,
- priority == PRIORITY_PSEUDO_ISR
- );
- }
+ _Scheduler_uniprocessor_Unblock( scheduler, the_thread, priority );
}
diff --git a/cpukit/score/src/schedulersimpleyield.c b/cpukit/score/src/schedulersimpleyield.c
index c25cceb8a7..ed8dd5b4cc 100644
--- a/cpukit/score/src/schedulersimpleyield.c
+++ b/cpukit/score/src/schedulersimpleyield.c
@@ -58,5 +58,8 @@ void _Scheduler_simple_Yield(
insert_priority = (unsigned int) _Thread_Get_priority( the_thread );
insert_priority = SCHEDULER_PRIORITY_APPEND( insert_priority );
_Scheduler_simple_Insert( &context->Ready, the_thread, insert_priority );
- _Scheduler_simple_Schedule_body( scheduler, the_thread, false );
+ _Scheduler_uniprocessor_Yield(
+ scheduler,
+ _Scheduler_simple_Get_highest_ready
+ );
}
diff --git a/cpukit/score/src/schedulersmp.c b/cpukit/score/src/schedulersmp.c
index 12a9bda454..e26caac3e3 100644
--- a/cpukit/score/src/schedulersmp.c
+++ b/cpukit/score/src/schedulersmp.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2014, 2017 embedded brains GmbH.
+ * Copyright (C) 2014, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/schedulersmpstartidle.c b/cpukit/score/src/schedulersmpstartidle.c
index 3e1b2d4820..b53a788ba1 100644
--- a/cpukit/score/src/schedulersmpstartidle.c
+++ b/cpukit/score/src/schedulersmpstartidle.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2013, 2017 embedded brains GmbH.
+ * Copyright (C) 2013, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/schedulerstrongapa.c b/cpukit/score/src/schedulerstrongapa.c
index c897652320..b38a0f96f0 100644
--- a/cpukit/score/src/schedulerstrongapa.c
+++ b/cpukit/score/src/schedulerstrongapa.c
@@ -38,7 +38,7 @@
/*
* Copyright (C) 2020 Richi Dubey
- * Copyright (C) 2013, 2016 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2013, 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/semaphore.c b/cpukit/score/src/semaphore.c
index f5d8b89bce..77b569db3a 100644
--- a/cpukit/score/src/semaphore.c
+++ b/cpukit/score/src/semaphore.c
@@ -11,7 +11,7 @@
*/
/*
- * Copyright (c) 2015, 2017 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2015, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/smp.c b/cpukit/score/src/smp.c
index 7c068f3c51..75520829e1 100644
--- a/cpukit/score/src/smp.c
+++ b/cpukit/score/src/smp.c
@@ -311,10 +311,7 @@ void _SMP_Request_shutdown( void )
}
}
-long unsigned _SMP_Process_message(
- Per_CPU_Control *cpu_self,
- long unsigned message
-)
+void _SMP_Process_message( Per_CPU_Control *cpu_self, long unsigned message )
{
if ( ( message & SMP_MESSAGE_SHUTDOWN ) != 0 ) {
ISR_Level level;
@@ -332,8 +329,6 @@ long unsigned _SMP_Process_message(
if ( ( message & SMP_MESSAGE_PERFORM_JOBS ) != 0 ) {
_Per_CPU_Perform_jobs( cpu_self );
}
-
- return message;
}
void _SMP_Try_to_process_message(
diff --git a/cpukit/score/src/smpbarrierwait.c b/cpukit/score/src/smpbarrierwait.c
index c3cf542016..58293dc566 100644
--- a/cpukit/score/src/smpbarrierwait.c
+++ b/cpukit/score/src/smpbarrierwait.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/smpbroadcastaction.c b/cpukit/score/src/smpbroadcastaction.c
index 767c6d4c7e..9543bbb9cf 100644
--- a/cpukit/score/src/smpbroadcastaction.c
+++ b/cpukit/score/src/smpbroadcastaction.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2019 embedded brains GmbH
+ * Copyright (C) 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/smplock.c b/cpukit/score/src/smplock.c
index c3a41300bb..31d6ea85c5 100644
--- a/cpukit/score/src/smplock.c
+++ b/cpukit/score/src/smplock.c
@@ -12,7 +12,7 @@
*/
/*
- * Copyright (c) 2015, 2016 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2015, 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/smpmulticastaction.c b/cpukit/score/src/smpmulticastaction.c
index b4068c23c9..4eec04c50d 100644
--- a/cpukit/score/src/smpmulticastaction.c
+++ b/cpukit/score/src/smpmulticastaction.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2019 embedded brains GmbH
+ * Copyright (C) 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/smpothercastaction.c b/cpukit/score/src/smpothercastaction.c
index 4279c4bf54..d4696a78c6 100644
--- a/cpukit/score/src/smpothercastaction.c
+++ b/cpukit/score/src/smpothercastaction.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2019 embedded brains GmbH
+ * Copyright (C) 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/smpsynchronize.c b/cpukit/score/src/smpsynchronize.c
index d01a15cb28..540156af10 100644
--- a/cpukit/score/src/smpsynchronize.c
+++ b/cpukit/score/src/smpsynchronize.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2019 embedded brains GmbH
+ * Copyright (C) 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/smpunicastaction.c b/cpukit/score/src/smpunicastaction.c
index fa5b5bb7c6..2fb06b84ae 100644
--- a/cpukit/score/src/smpunicastaction.c
+++ b/cpukit/score/src/smpunicastaction.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2019 embedded brains GmbH
+ * Copyright (C) 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/stackallocator.c b/cpukit/score/src/stackallocator.c
index 920aee86c1..a0d0f4802a 100644
--- a/cpukit/score/src/stackallocator.c
+++ b/cpukit/score/src/stackallocator.c
@@ -11,7 +11,7 @@
*/
/*
- * Copyright (C) 2019 embedded brains GmbH
+ * Copyright (C) 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/stackallocatorforidle.c b/cpukit/score/src/stackallocatorforidle.c
index 76b6ace1f4..c8c8c0b766 100644
--- a/cpukit/score/src/stackallocatorforidle.c
+++ b/cpukit/score/src/stackallocatorforidle.c
@@ -1,6 +1,15 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreStack
*
+ * @brief This source file contains the implementation of
+ * _Stack_Allocator_allocate_for_idle_static().
+ */
+
+/*
* Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
*
* Redistribution and use in source and binary forms, with or without
@@ -30,36 +39,21 @@
#endif
#include <rtems/score/stack.h>
-#include <rtems/score/thread.h>
#include <rtems/score/assert.h>
-/**
- * @brief Default stack allocator allocate for idle handler.
- *
- * The allocate for idle handler is optional even when the user thread stack
- * allocator and deallocator are configured.
- *
- * The default allocator for IDLE thread stacks gets the memory from a
- * statically allocated area provided via confdefs.h.
- *
- * @param cpu_index Index of the CPU for the IDLE thread using this stack
- * @param stack_size The size of the stack area to allocate in bytes.
- *
- * @retval NULL Not enough memory (never returned).
- * @retval other Pointer to begin of stack area.
- */
-static void *_Stack_Allocator_allocate_for_idle_default(
+void *_Stack_Allocator_allocate_for_idle_static(
uint32_t cpu_index,
- size_t stack_size
+ size_t *storage_size
)
{
+ size_t size;
+
+ size = _Stack_Allocator_allocate_for_idle_storage_size;
+ *storage_size = size;
#if defined(RTEMS_SMP)
- return &_Thread_Idle_stacks[ cpu_index * stack_size ];
+ return &_Stack_Allocator_allocate_for_idle_storage_areas[ cpu_index * size ];
#else
_Assert( cpu_index == 0 );
- return &_Thread_Idle_stacks[ 0 ];
+ return &_Stack_Allocator_allocate_for_idle_storage_areas[ 0 ];
#endif
}
-
-const Stack_Allocator_allocate_for_idle _Stack_Allocator_allocate_for_idle =
- _Stack_Allocator_allocate_for_idle_default;
diff --git a/cpukit/score/src/pheapgetblocksize.c b/cpukit/score/src/stackallocatorforidlewkspace.c
index c53a66b5d4..c57f245407 100644
--- a/cpukit/score/src/pheapgetblocksize.c
+++ b/cpukit/score/src/stackallocatorforidlewkspace.c
@@ -3,15 +3,14 @@
/**
* @file
*
- * @ingroup RTEMSScoreProtHeap
+ * @ingroup RTEMSScoreStack
*
* @brief This source file contains the implementation of
- * _Protected_heap_Get_block_size().
+ * _Stack_Allocator_allocate_for_idle_workspace().
*/
/*
- * COPYRIGHT (c) 1989-2007.
- * On-Line Applications Research Corporation (OAR).
+ * Copyright (C) 2022 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -39,18 +38,23 @@
#include "config.h"
#endif
-#include <rtems/score/protectedheap.h>
+#include <rtems/score/stack.h>
+#include <rtems/score/interr.h>
+#include <rtems/score/wkspace.h>
-bool _Protected_heap_Get_block_size(
- Heap_Control *the_heap,
- void *starting_address,
- uintptr_t *size
+void *_Stack_Allocator_allocate_for_idle_workspace(
+ uint32_t unused,
+ size_t *storage_size
)
{
- bool status;
+ void *area;
- _RTEMS_Lock_allocator();
- status = _Heap_Size_of_alloc_area( the_heap, starting_address, size );
- _RTEMS_Unlock_allocator();
- return status;
+ (void) unused;
+ area = _Workspace_Allocate( *storage_size );
+
+ if ( area == NULL ) {
+ _Internal_error( INTERNAL_ERROR_NO_MEMORY_FOR_IDLE_TASK_STORAGE );
+ }
+
+ return area;
}
diff --git a/cpukit/score/src/stackallocatorfree.c b/cpukit/score/src/stackallocatorfree.c
index f32912ea9c..54f76e313f 100644
--- a/cpukit/score/src/stackallocatorfree.c
+++ b/cpukit/score/src/stackallocatorfree.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2019 embedded brains GmbH
+ * Copyright (C) 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/stackallocatorinit.c b/cpukit/score/src/stackallocatorinit.c
index a57a253301..8f2512bee7 100644
--- a/cpukit/score/src/stackallocatorinit.c
+++ b/cpukit/score/src/stackallocatorinit.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadallocateunlimited.c b/cpukit/score/src/threadallocateunlimited.c
index 6bd3b3ec7a..48e69822a7 100644
--- a/cpukit/score/src/threadallocateunlimited.c
+++ b/cpukit/score/src/threadallocateunlimited.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2019, 2020 embedded brains GmbH
+ * Copyright (C) 2019, 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadchangepriority.c b/cpukit/score/src/threadchangepriority.c
index 321bb15cab..78291b7798 100644
--- a/cpukit/score/src/threadchangepriority.c
+++ b/cpukit/score/src/threadchangepriority.c
@@ -16,7 +16,7 @@
* COPYRIGHT (c) 1989-2014.
* On-Line Applications Research Corporation (OAR).
*
- * Copyright (c) 2013, 2016 embedded brains GmbH
+ * Copyright (C) 2013, 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -111,6 +111,7 @@ static void _Thread_Priority_action_change(
void *arg
)
{
+ (void) arg;
_Thread_Set_scheduler_node_priority(
priority_aggregation,
priority_group_order
@@ -135,11 +136,15 @@ static void _Thread_Priority_do_perform_actions(
priority_aggregation = _Priority_Actions_move( &queue_context->Priority.Actions );
do {
+#if defined(RTEMS_SMP)
Priority_Aggregation *next_aggregation;
+#endif
Priority_Node *priority_action_node;
Priority_Action_type priority_action_type;
+#if defined(RTEMS_SMP)
next_aggregation = _Priority_Get_next_action( priority_aggregation );
+#endif
priority_action_node = priority_aggregation->Action.node;
priority_action_type = priority_aggregation->Action.type;
@@ -198,8 +203,12 @@ static void _Thread_Priority_do_perform_actions(
break;
}
+#if defined(RTEMS_SMP)
priority_aggregation = next_aggregation;
- } while ( _Priority_Actions_is_valid( priority_aggregation ) );
+ } while ( priority_aggregation != NULL );
+#else
+ } while ( false );
+#endif
if ( !_Priority_Actions_is_empty( &queue_context->Priority.Actions ) ) {
_Thread_queue_Context_add_priority_update( queue_context, the_thread );
@@ -352,6 +361,7 @@ void _Thread_Priority_changed(
);
}
+#if defined(RTEMS_SMP)
void _Thread_Priority_replace(
Thread_Control *the_thread,
Priority_Node *victim_node,
@@ -367,6 +377,7 @@ void _Thread_Priority_replace(
replacement_node
);
}
+#endif
void _Thread_Priority_update( Thread_queue_Context *queue_context )
{
diff --git a/cpukit/score/src/threadcreateidle.c b/cpukit/score/src/threadcreateidle.c
index 9f3c01d118..4f16a57099 100644
--- a/cpukit/score/src/threadcreateidle.c
+++ b/cpukit/score/src/threadcreateidle.c
@@ -39,17 +39,24 @@
#include "config.h"
#endif
-#include <rtems/score/threadidledata.h>
#include <rtems/score/threadimpl.h>
+
#include <rtems/score/assert.h>
+#include <rtems/score/cpuimpl.h>
+#include <rtems/score/interr.h>
#include <rtems/score/schedulerimpl.h>
#include <rtems/score/stackimpl.h>
#include <rtems/score/sysstate.h>
+#include <rtems/score/threadidledata.h>
+#include <rtems/score/tls.h>
#include <rtems/score/userextimpl.h>
#include <string.h>
-static void _Thread_Create_idle_for_CPU( Per_CPU_Control *cpu )
+static void _Thread_Create_idle_for_CPU(
+ Per_CPU_Control *cpu,
+ uintptr_t storage_size
+)
{
Thread_Configuration config;
Thread_Control *idle;
@@ -65,18 +72,22 @@ static void _Thread_Create_idle_for_CPU( Per_CPU_Control *cpu )
config.name = _Objects_Build_name( 'I', 'D', 'L', 'E' );
config.is_fp = CPU_IDLE_TASK_IS_FP;
config.is_preemptible = true;
- config.stack_size = _Thread_Idle_stack_size
- + CPU_IDLE_TASK_IS_FP * CONTEXT_FP_SIZE;
+ config.stack_free = _Objects_Free_nothing;
+ config.stack_size = storage_size;
/*
* The IDLE thread stacks may be statically allocated or there may be a
* custom allocator provided just as with user threads.
*/
- config.stack_area = (*_Stack_Allocator_allocate_for_idle)(
+ config.stack_area = ( *_Stack_Allocator_allocate_for_idle )(
_Per_CPU_Get_index( cpu ),
- config.stack_size
+ &config.stack_size
);
+ if ( config.stack_size < storage_size ) {
+ _Internal_error( INTERNAL_ERROR_IDLE_THREAD_STACK_TOO_SMALL );
+ }
+
/*
* The entire workspace is zeroed during its initialization. Thus, all
* fields not explicitly assigned were explicitly zeroed by
@@ -86,13 +97,15 @@ static void _Thread_Create_idle_for_CPU( Per_CPU_Control *cpu )
_Assert( idle != NULL );
status = _Thread_Initialize( &_Thread_Information, idle, &config );
- _Assert_Unused_variable_equals( status, STATUS_SUCCESSFUL );
+ if ( status != STATUS_SUCCESSFUL ) {
+ _Internal_error( INTERNAL_ERROR_IDLE_THREAD_CREATE_FAILED );
+ }
/*
* WARNING!!! This is necessary to "kick" start the system and
* MUST be done before _Thread_Start is invoked.
*/
- cpu->heir =
+ cpu->heir = idle;
cpu->executing = idle;
#if defined(RTEMS_SMP)
cpu->ancestor = idle;
@@ -111,17 +124,32 @@ static void _Thread_Create_idle_for_CPU( Per_CPU_Control *cpu )
void _Thread_Create_idle( void )
{
- uint32_t cpu_max;
- uint32_t cpu_index;
+ uintptr_t storage_size;
+#if defined(RTEMS_SMP)
+ uint32_t cpu_max;
+ uint32_t cpu_index;
+#endif
- _System_state_Set( SYSTEM_STATE_BEFORE_MULTITASKING );
+ storage_size = _TLS_Get_allocation_size() +
+ CPU_IDLE_TASK_IS_FP * CONTEXT_FP_SIZE +
+ _Thread_Idle_stack_size;
+
+#if defined(RTEMS_SMP)
cpu_max = _SMP_Get_processor_maximum();
for ( cpu_index = 0 ; cpu_index < cpu_max ; ++cpu_index ) {
Per_CPU_Control *cpu = _Per_CPU_Get_by_index( cpu_index );
if ( _Per_CPU_Is_processor_online( cpu ) ) {
- _Thread_Create_idle_for_CPU( cpu );
+ _Thread_Create_idle_for_CPU( cpu, storage_size );
}
}
+#else
+ _Thread_Create_idle_for_CPU( _Per_CPU_Get(), storage_size );
+#endif
+
+ _CPU_Use_thread_local_storage(
+ &_Per_CPU_Get_executing( _Per_CPU_Get() )->Registers
+ );
+ _System_state_Set( SYSTEM_STATE_BEFORE_MULTITASKING );
}
diff --git a/cpukit/score/src/threaddispatch.c b/cpukit/score/src/threaddispatch.c
index b2426fa8ac..7c3326803c 100644
--- a/cpukit/score/src/threaddispatch.c
+++ b/cpukit/score/src/threaddispatch.c
@@ -15,7 +15,7 @@
* COPYRIGHT (c) 1989-2009.
* On-Line Applications Research Corporation (OAR).
*
- * Copyright (c) 2014, 2018 embedded brains GmbH.
+ * Copyright (C) 2014, 2018 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -301,12 +301,13 @@ void _Thread_Do_dispatch( Per_CPU_Control *cpu_self, ISR_Level level )
heir = _Thread_Get_heir_and_make_it_executing( cpu_self );
/*
- * When the heir and executing are the same, then we are being
- * requested to do the post switch dispatching. This is normally
- * done to dispatch signals.
+ * If the heir and executing are the same, then there is no need to do a
+ * context switch. Proceed to run the post switch actions. This is
+ * normally done to dispatch signals.
*/
- if ( heir == executing )
- goto post_switch;
+ if ( heir == executing ) {
+ break;
+ }
/*
* Since heir and executing are not the same, we need to do a real
@@ -341,7 +342,11 @@ void _Thread_Do_dispatch( Per_CPU_Control *cpu_self, ISR_Level level )
_ISR_Local_disable( level );
} while ( cpu_self->dispatch_necessary );
-post_switch:
+ /*
+ * We are done with context switching. Proceed to run the post switch
+ * actions.
+ */
+
_Assert( cpu_self->thread_dispatch_disable_level == 1 );
cpu_self->thread_dispatch_disable_level = 0;
_Profiling_Thread_dispatch_enable( cpu_self, 0 );
diff --git a/cpukit/score/src/threadentryadaptoridle.c b/cpukit/score/src/threadentryadaptoridle.c
index f2fb21b901..912e6c5187 100644
--- a/cpukit/score/src/threadentryadaptoridle.c
+++ b/cpukit/score/src/threadentryadaptoridle.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2015 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2015 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadentryadaptornumeric.c b/cpukit/score/src/threadentryadaptornumeric.c
index 8fbc4f04dc..a0499eb7ce 100644
--- a/cpukit/score/src/threadentryadaptornumeric.c
+++ b/cpukit/score/src/threadentryadaptornumeric.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2015 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2015 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadentryadaptorpointer.c b/cpukit/score/src/threadentryadaptorpointer.c
index 99a758a2e0..3b431ca95a 100644
--- a/cpukit/score/src/threadentryadaptorpointer.c
+++ b/cpukit/score/src/threadentryadaptorpointer.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2015 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2015 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadexhausttimeslice.c b/cpukit/score/src/threadexhausttimeslice.c
index f3f6924e44..4e7503bee6 100644
--- a/cpukit/score/src/threadexhausttimeslice.c
+++ b/cpukit/score/src/threadexhausttimeslice.c
@@ -11,7 +11,7 @@
*/
/*
- * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadgetcputimeused.c b/cpukit/score/src/threadgetcputimeused.c
index cefd0f2910..82ad7a3043 100644
--- a/cpukit/score/src/threadgetcputimeused.c
+++ b/cpukit/score/src/threadgetcputimeused.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2016 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadgetcputimeusedafterreset.c b/cpukit/score/src/threadgetcputimeusedafterreset.c
index 1ab4aa16fb..40c5d01cc3 100644
--- a/cpukit/score/src/threadgetcputimeusedafterreset.c
+++ b/cpukit/score/src/threadgetcputimeusedafterreset.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadidledefault.c b/cpukit/score/src/threadidledefault.c
index 2386c0317d..bb9d476018 100644
--- a/cpukit/score/src/threadidledefault.c
+++ b/cpukit/score/src/threadidledefault.c
@@ -10,7 +10,7 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadinitialize.c b/cpukit/score/src/threadinitialize.c
index 457fdaa54a..e1a6c7de93 100644
--- a/cpukit/score/src/threadinitialize.c
+++ b/cpukit/score/src/threadinitialize.c
@@ -139,7 +139,10 @@ static void _Thread_Initialize_scheduler_and_wait_nodes(
* The application configuration ensures that we have at least one scheduler
* configured.
*/
- while ( scheduler_index < _Scheduler_Count ) {
+
+ _Assert ( _Scheduler_Count >= 1 );
+
+ do {
Priority_Control priority;
if ( scheduler == config->scheduler ) {
@@ -172,7 +175,7 @@ static void _Thread_Initialize_scheduler_and_wait_nodes(
( (uintptr_t) scheduler_node + _Scheduler_Node_size );
++scheduler;
++scheduler_index;
- }
+ } while ( scheduler_index < _Scheduler_Count );
/*
* The thread is initialized to use exactly one scheduler node which is
@@ -267,12 +270,8 @@ static bool _Thread_Try_initialize(
/* Allocate thread-local storage (TLS) area in stack area */
if ( tls_size > 0 ) {
- uintptr_t tls_align;
-
stack_end -= tls_size;
- tls_align = (uintptr_t) _TLS_Alignment;
- the_thread->Start.tls_area = (void *)
- ( ( (uintptr_t) stack_end + tls_align - 1 ) & ~( tls_align - 1 ) );
+ the_thread->Start.tls_area = stack_end;
}
_Stack_Initialize(
@@ -298,6 +297,7 @@ static bool _Thread_Try_initialize(
the_thread->Start.is_preemptible = config->is_preemptible;
the_thread->Start.cpu_budget_operations = config->cpu_budget_operations;
the_thread->Start.stack_free = config->stack_free;
+ the_thread->Join_queue.Queue.owner = the_thread;
_Thread_Timer_initialize( &the_thread->Timer, cpu );
_Thread_Initialize_scheduler_and_wait_nodes( the_thread, config );
diff --git a/cpukit/score/src/threaditerate.c b/cpukit/score/src/threaditerate.c
index b82c87ba47..c0a54340e0 100644
--- a/cpukit/score/src/threaditerate.c
+++ b/cpukit/score/src/threaditerate.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2016 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadname.c b/cpukit/score/src/threadname.c
index 465f1871fb..55a67e5b6d 100644
--- a/cpukit/score/src/threadname.c
+++ b/cpukit/score/src/threadname.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2017 embedded brains GmbH.
+ * Copyright (c) 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadplaindispatch.c b/cpukit/score/src/threadplaindispatch.c
index eeb52ec42d..5eca17351f 100644
--- a/cpukit/score/src/threadplaindispatch.c
+++ b/cpukit/score/src/threadplaindispatch.c
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (C) 2015, 2017 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2015, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadq.c b/cpukit/score/src/threadq.c
index e694029a46..3c6d72bd14 100644
--- a/cpukit/score/src/threadq.c
+++ b/cpukit/score/src/threadq.c
@@ -179,5 +179,7 @@ void _Thread_queue_MP_callout_do_nothing(
)
{
/* Do nothing */
+ (void) the_proxy;
+ (void) mp_id;
}
#endif
diff --git a/cpukit/score/src/threadqenqueue.c b/cpukit/score/src/threadqenqueue.c
index 462cb3719a..038c483f65 100644
--- a/cpukit/score/src/threadqenqueue.c
+++ b/cpukit/score/src/threadqenqueue.c
@@ -19,7 +19,7 @@
* COPYRIGHT (c) 1989-2014.
* On-Line Applications Research Corporation (OAR).
*
- * Copyright (c) 2015, 2016 embedded brains GmbH.
+ * Copyright (C) 2015, 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -400,6 +400,7 @@ void _Thread_queue_Deadlock_status( Thread_Control *the_thread )
void _Thread_queue_Deadlock_fatal( Thread_Control *the_thread )
{
+ (void) the_thread;
_Internal_error( INTERNAL_ERROR_THREAD_QUEUE_DEADLOCK );
}
diff --git a/cpukit/score/src/threadqextract.c b/cpukit/score/src/threadqextract.c
index e08b902508..32985a0f3a 100644
--- a/cpukit/score/src/threadqextract.c
+++ b/cpukit/score/src/threadqextract.c
@@ -13,7 +13,7 @@
* COPYRIGHT (c) 1989-2014.
* On-Line Applications Research Corporation (OAR).
*
- * Copyright (c) 2015, 2016 embedded brains GmbH.
+ * Copyright (C) 2015, 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadqgetnameandid.c b/cpukit/score/src/threadqgetnameandid.c
index ea4e2203e6..82c13c4633 100644
--- a/cpukit/score/src/threadqgetnameandid.c
+++ b/cpukit/score/src/threadqgetnameandid.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2017 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadqops.c b/cpukit/score/src/threadqops.c
index 33fc5a44cb..9a09b4c442 100644
--- a/cpukit/score/src/threadqops.c
+++ b/cpukit/score/src/threadqops.c
@@ -12,7 +12,7 @@
*/
/*
- * Copyright (c) 2015, 2021 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2015, 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -156,6 +156,8 @@ static void _Thread_queue_FIFO_do_initialize(
{
Scheduler_Node *scheduler_node;
+ (void) queue;
+ (void) queue_context;
scheduler_node = _Thread_Scheduler_get_home_node( the_thread );
_Chain_Initialize_node( &scheduler_node->Wait.Priority.Node.Node.Chain );
@@ -291,6 +293,7 @@ static Thread_queue_Priority_queue *_Thread_queue_Priority_queue_by_index(
)
{
#if defined(RTEMS_SMP)
+ _Assert( scheduler_index < _Scheduler_Count );
return &heads->Priority[ scheduler_index ];
#else
(void) scheduler_index;
@@ -404,8 +407,12 @@ static void _Thread_queue_Priority_priority_actions(
break;
}
+#if defined(RTEMS_SMP)
priority_aggregation = _Priority_Get_next_action( priority_aggregation );
- } while ( _Priority_Actions_is_valid( priority_aggregation ) );
+ } while ( priority_aggregation != NULL );
+#else
+ } while ( false );
+#endif
}
static void _Thread_queue_Priority_do_initialize(
@@ -734,14 +741,18 @@ static void _Thread_queue_Priority_inherit_priority_actions(
priority_aggregation = _Priority_Actions_move( priority_actions );
do {
+#if defined(RTEMS_SMP)
Priority_Aggregation *next_aggregation;
+#endif
Scheduler_Node *scheduler_node;
size_t scheduler_index;
Thread_queue_Priority_queue *priority_queue;
Scheduler_Node *scheduler_node_of_owner;
Priority_Action_type priority_action_type;
+#if defined(RTEMS_SMP)
next_aggregation = _Priority_Get_next_action( priority_aggregation );
+#endif
scheduler_node = SCHEDULER_NODE_OF_WAIT_PRIORITY( priority_aggregation );
scheduler_index = _Thread_queue_Scheduler_index( scheduler_node );
@@ -797,8 +808,12 @@ static void _Thread_queue_Priority_inherit_priority_actions(
break;
}
+#if defined(RTEMS_SMP)
priority_aggregation = next_aggregation;
- } while ( _Priority_Actions_is_valid( priority_aggregation ) );
+ } while ( priority_aggregation != NULL );
+#else
+ } while ( false );
+#endif
}
static void _Thread_queue_Priority_inherit_do_initialize(
diff --git a/cpukit/score/src/threadqtimeout.c b/cpukit/score/src/threadqtimeout.c
index 271ea27f27..e30a2ffded 100644
--- a/cpukit/score/src/threadqtimeout.c
+++ b/cpukit/score/src/threadqtimeout.c
@@ -12,7 +12,7 @@
*/
/*
- * Copyright (c) 2016, 2021 embedded brains GmbH
+ * Copyright (C) 2016, 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -53,6 +53,7 @@ void _Thread_queue_Add_timeout_ticks(
{
Watchdog_Interval ticks;
+ (void) queue;
ticks = queue_context->Timeout.ticks;
if ( ticks != WATCHDOG_NO_TIMEOUT ) {
@@ -132,7 +133,7 @@ void _Thread_queue_Add_timeout_monotonic_timespec(
{
struct timespec now;
- _Timecounter_Getnanouptime( &now );
+ _Timecounter_Nanouptime( &now );
_Thread_queue_Add_timeout_timespec(
queue,
the_thread,
@@ -152,7 +153,7 @@ void _Thread_queue_Add_timeout_realtime_timespec(
{
struct timespec now;
- _Timecounter_Getnanotime( &now );
+ _Timecounter_Nanotime( &now );
_Thread_queue_Add_timeout_timespec(
queue,
the_thread,
diff --git a/cpukit/score/src/threadresettimeslice.c b/cpukit/score/src/threadresettimeslice.c
index ed4d6fb3e3..4697ef74de 100644
--- a/cpukit/score/src/threadresettimeslice.c
+++ b/cpukit/score/src/threadresettimeslice.c
@@ -12,7 +12,7 @@
*/
/*
- * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2021 embedded brains GmbH & Co. KG
* Copyright (C) 2010 Gedare Bloom <gedare@rtems.org>
*
* Redistribution and use in source and binary forms, with or without
diff --git a/cpukit/score/src/threadrestart.c b/cpukit/score/src/threadrestart.c
index 25f57e2a40..72326682ca 100644
--- a/cpukit/score/src/threadrestart.c
+++ b/cpukit/score/src/threadrestart.c
@@ -14,7 +14,7 @@
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
- * Copyright (c) 2014, 2021 embedded brains GmbH.
+ * Copyright (C) 2014, 2022 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -46,16 +46,16 @@
#include <rtems/score/apimutex.h>
#include <rtems/score/assert.h>
#include <rtems/score/chainimpl.h>
-#include <rtems/score/freechainimpl.h>
#include <rtems/score/isrlock.h>
#include <rtems/score/schedulerimpl.h>
-#include <rtems/score/stackimpl.h>
#include <rtems/score/sysstate.h>
#include <rtems/score/threadqimpl.h>
#include <rtems/score/userextimpl.h>
#include <rtems/score/watchdogimpl.h>
-#define THREAD_JOIN_TQ_OPERATIONS &_Thread_queue_Operations_priority
+#include <pthread.h>
+
+#define THREAD_JOIN_TQ_OPERATIONS &_Thread_queue_Operations_priority_inherit
static void _Thread_Life_action_handler(
Thread_Control *executing,
@@ -70,31 +70,6 @@ Thread_Zombie_registry _Thread_Zombies = {
.Chain = CHAIN_INITIALIZER_EMPTY( _Thread_Zombies.Chain )
};
-static void _Thread_Raise_real_priority(
- Thread_Control *the_thread,
- Priority_Control priority
-)
-{
- Thread_queue_Context queue_context;
-
- _Thread_queue_Context_initialize( &queue_context );
- _Thread_queue_Context_clear_priority_updates( &queue_context );
- _Thread_Wait_acquire( the_thread, &queue_context );
-
- if ( priority < the_thread->Real_priority.priority ) {
- _Thread_Priority_change(
- the_thread,
- &the_thread->Real_priority,
- priority,
- PRIORITY_GROUP_LAST,
- &queue_context
- );
- }
-
- _Thread_Wait_release( the_thread, &queue_context );
- _Thread_Priority_update( &queue_context );
-}
-
typedef struct {
Thread_queue_Context Base;
void *exit_value;
@@ -108,6 +83,7 @@ static Thread_Control *_Thread_Join_flush_filter(
{
Thread_Join_context *join_context;
+ (void) queue;
join_context = (Thread_Join_context *) queue_context;
the_thread->Wait.return_argument = join_context->exit_value;
@@ -388,18 +364,37 @@ static void _Thread_Remove_life_change_request( Thread_Control *the_thread )
_Thread_State_release( the_thread, &lock_context );
}
-void _Thread_Join(
+static void _Thread_Clear_waiting_for_join_at_exit(
+ Thread_queue_Queue *queue,
+ Thread_Control *the_thread,
+ Per_CPU_Control *cpu_self,
+ Thread_queue_Context *queue_context
+)
+{
+ (void) the_thread;
+ (void) cpu_self;
+ (void) queue_context;
+ _Thread_Clear_state( queue->owner, STATES_WAITING_FOR_JOIN_AT_EXIT );
+}
+
+Status_Control _Thread_Join(
Thread_Control *the_thread,
States_Control waiting_for_join,
Thread_Control *executing,
Thread_queue_Context *queue_context
)
{
- _Assert( the_thread != executing );
_Assert( _Thread_State_is_owner( the_thread ) );
executing->Wait.return_argument = NULL;
-
+ _Thread_queue_Context_set_enqueue_callout(
+ queue_context,
+ _Thread_Clear_waiting_for_join_at_exit
+ );
+ _Thread_queue_Context_set_deadlock_callout(
+ queue_context,
+ _Thread_queue_Deadlock_status
+ );
_Thread_queue_Context_set_thread_state( queue_context, waiting_for_join );
_Thread_queue_Enqueue(
&the_thread->Join_queue.Queue,
@@ -407,6 +402,7 @@ void _Thread_Join(
executing,
queue_context
);
+ return _Thread_Wait_get_status( executing );
}
static void _Thread_Set_exit_value(
@@ -435,77 +431,70 @@ static void _Thread_Try_life_change_request(
}
}
-void _Thread_Cancel(
- Thread_Control *the_thread,
- Thread_Control *executing,
- void *exit_value
+Thread_Cancel_state _Thread_Cancel(
+ Thread_Control *the_thread,
+ Thread_Control *executing,
+ Thread_Life_state life_states_to_clear
)
{
- ISR_lock_Context lock_context;
- Thread_Life_state previous;
- Per_CPU_Control *cpu_self;
+ ISR_lock_Context lock_context;
+ Thread_Life_state previous;
_Assert( the_thread != executing );
_Thread_State_acquire( the_thread, &lock_context );
- _Thread_Set_exit_value( the_thread, exit_value );
+ _Thread_Set_exit_value( the_thread, PTHREAD_CANCELED );
previous = _Thread_Change_life_locked(
the_thread,
- 0,
+ life_states_to_clear,
THREAD_LIFE_TERMINATING,
0
);
- cpu_self = _Thread_Dispatch_disable_critical( &lock_context );
-
if ( _States_Is_dormant( the_thread->current_state ) ) {
_Thread_State_release( the_thread, &lock_context );
_Thread_Make_zombie( the_thread );
- } else {
- Priority_Control priority;
-
- _Thread_Try_life_change_request( the_thread, previous, &lock_context );
- priority = _Thread_Get_priority( executing );
- _Thread_Raise_real_priority( the_thread, priority );
+ return THREAD_CANCEL_DONE;
}
- _Thread_Dispatch_enable( cpu_self );
+ _Thread_Try_life_change_request( the_thread, previous, &lock_context );
+ return THREAD_CANCEL_IN_PROGRESS;
}
-static void _Thread_Close_enqueue_callout(
- Thread_queue_Queue *queue,
+Status_Control _Thread_Close(
Thread_Control *the_thread,
- Per_CPU_Control *cpu_self,
+ Thread_Control *executing,
Thread_queue_Context *queue_context
)
{
- Thread_Close_context *context;
-
- context = (Thread_Close_context *) queue_context;
- _Thread_Cancel( context->cancel, the_thread, NULL );
-}
+ Per_CPU_Control *cpu_self;
+ Thread_Cancel_state cancel_state;
-void _Thread_Close(
- Thread_Control *the_thread,
- Thread_Control *executing,
- Thread_Close_context *context
-)
-{
- context->cancel = the_thread;
- _Thread_queue_Context_set_enqueue_callout(
- &context->Base,
- _Thread_Close_enqueue_callout
+ cpu_self = _Thread_Dispatch_disable_critical(
+ &queue_context->Lock_context.Lock_context
);
+ _ISR_lock_ISR_enable( &queue_context->Lock_context.Lock_context );
+
+ cancel_state = _Thread_Cancel( the_thread, executing, THREAD_LIFE_DETACHED );
+
+ if ( cancel_state == THREAD_CANCEL_DONE ) {
+ _Thread_Dispatch_enable( cpu_self );
+ return STATUS_SUCCESSFUL;
+ }
+
+ _ISR_lock_ISR_disable( &queue_context->Lock_context.Lock_context );
+ _Thread_Dispatch_unnest( cpu_self );
_Thread_State_acquire_critical(
the_thread,
- &context->Base.Lock_context.Lock_context
+ &queue_context->Lock_context.Lock_context
);
- _Thread_Join(
+
+ return _Thread_Join(
the_thread,
STATES_WAITING_FOR_JOIN,
executing,
- &context->Base
+ queue_context
);
}
diff --git a/cpukit/score/src/threadscheduler.c b/cpukit/score/src/threadscheduler.c
index ba4c3ca6f0..6e5812e1ce 100644
--- a/cpukit/score/src/threadscheduler.c
+++ b/cpukit/score/src/threadscheduler.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2016 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadselfid.c b/cpukit/score/src/threadselfid.c
index a8b4315f27..ee802c7444 100644
--- a/cpukit/score/src/threadselfid.c
+++ b/cpukit/score/src/threadselfid.c
@@ -9,7 +9,7 @@
*/
/*
- * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2021 embedded brains GmbH & Co. KG
* Copyright (C) 1995 On-Line Applications Research Corporation (OAR)
*
* Redistribution and use in source and binary forms, with or without
diff --git a/cpukit/score/src/threadunpin.c b/cpukit/score/src/threadunpin.c
index ce97fb14bc..e8ebcbd45b 100644
--- a/cpukit/score/src/threadunpin.c
+++ b/cpukit/score/src/threadunpin.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2018 embedded brains GmbH
+ * Copyright (c) 2018 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadwaitgetid.c b/cpukit/score/src/threadwaitgetid.c
index 4e6649dc9c..433755f930 100644
--- a/cpukit/score/src/threadwaitgetid.c
+++ b/cpukit/score/src/threadwaitgetid.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2016, 2017 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2016, 2017 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/threadyield.c b/cpukit/score/src/threadyield.c
index 144b734436..3cc2f07caf 100644
--- a/cpukit/score/src/threadyield.c
+++ b/cpukit/score/src/threadyield.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2014 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2014 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/tlsallocsize.c b/cpukit/score/src/tlsallocsize.c
index d761f3b6cf..fa28391b83 100644
--- a/cpukit/score/src/tlsallocsize.c
+++ b/cpukit/score/src/tlsallocsize.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2014, 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2014, 2023 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -42,14 +42,47 @@
#include <rtems/score/interr.h>
#include <rtems/score/thread.h>
+extern char _TLS_Data_begin[];
+
+extern char _TLS_Data_size[];
+
+extern char _TLS_BSS_begin[];
+
+extern char _TLS_BSS_size[];
+
+extern char _TLS_Size[];
+
+/**
+ * @brief The TLS section alignment.
+ *
+ * This symbol is provided by the linker command file as the maximum alignment
+ * of the .tdata and .tbss sections. The linker ensures that the first TLS
+ * output section is aligned to the maximum alignment of all TLS output
+ * sections, see function _bfd_elf_tls_setup() in bfd/elflink.c of the GNU
+ * Binutils sources. The linker command file must take into account the case
+ * that the .tdata section is empty and the .tbss section is non-empty.
+ */
+extern char _TLS_Alignment[];
+
+const volatile TLS_Configuration _TLS_Configuration = {
+ .data_begin = _TLS_Data_begin,
+ .data_size = _TLS_Data_size,
+ .bss_begin = _TLS_BSS_begin,
+ .bss_size = _TLS_BSS_size,
+ .size = _TLS_Size,
+ .alignment = _TLS_Alignment
+};
+
static uintptr_t _TLS_Allocation_size;
uintptr_t _TLS_Get_allocation_size( void )
{
- uintptr_t size;
- uintptr_t allocation_size;
+ const volatile TLS_Configuration *config;
+ uintptr_t size;
+ uintptr_t allocation_size;
- size = _TLS_Get_size();
+ config = &_TLS_Configuration;
+ size = (uintptr_t) config->size;
if ( size == 0 ) {
return 0;
@@ -58,29 +91,45 @@ uintptr_t _TLS_Get_allocation_size( void )
allocation_size = _TLS_Allocation_size;
if ( allocation_size == 0 ) {
- uintptr_t alignment;
-
- alignment = _TLS_Align_up( (uintptr_t) _TLS_Alignment );
-
- allocation_size = size;
- allocation_size += _TLS_Get_thread_control_block_area_size( alignment );
-#ifndef __i386__
- allocation_size += sizeof( TLS_Dynamic_thread_vector );
-#endif
+ uintptr_t tls_align;
+ uintptr_t stack_align;
/*
* The TLS area is allocated in the thread storage area. Each allocation
* shall meet the stack alignment requirement.
*/
- allocation_size = _TLS_Align_up( allocation_size );
+ stack_align = CPU_STACK_ALIGNMENT;
+ tls_align = RTEMS_ALIGN_UP( (uintptr_t) config->alignment, stack_align );
+
+#ifndef __i386__
+ /* Reserve space for the dynamic thread vector */
+ allocation_size +=
+ RTEMS_ALIGN_UP( sizeof( TLS_Dynamic_thread_vector ), stack_align );
+#endif
+
+ /* Reserve space for the thread control block */
+ allocation_size +=
+#if CPU_THREAD_LOCAL_STORAGE_VARIANT == 11
+ RTEMS_ALIGN_UP( sizeof( TLS_Thread_control_block ), tls_align );
+#else
+ RTEMS_ALIGN_UP( sizeof( TLS_Thread_control_block ), stack_align );
+#endif
+
+ /* Reserve space for the thread-local storage data */
+ allocation_size +=
+#if CPU_THREAD_LOCAL_STORAGE_VARIANT == 20
+ RTEMS_ALIGN_UP( size, tls_align );
+#else
+ RTEMS_ALIGN_UP( size, stack_align );
+#endif
/*
* The stack allocator does not support aligned allocations. Allocate
* enough to do the alignment manually.
*/
- if ( alignment > CPU_STACK_ALIGNMENT ) {
- _Assert( alignment % CPU_STACK_ALIGNMENT == 0 );
- allocation_size += alignment - CPU_STACK_ALIGNMENT;
+ if ( tls_align > stack_align ) {
+ _Assert( tls_align % stack_align == 0 );
+ allocation_size += tls_align - stack_align;
}
if ( _Thread_Maximum_TLS_size != 0 ) {
diff --git a/cpukit/score/src/userextiterate.c b/cpukit/score/src/userextiterate.c
index 5808c4a728..cae76d173c 100644
--- a/cpukit/score/src/userextiterate.c
+++ b/cpukit/score/src/userextiterate.c
@@ -17,7 +17,7 @@
*/
/*
- * Copyright (c) 2012, 2019 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2012, 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -47,8 +47,6 @@
#include <rtems/score/userextimpl.h>
-#include <pthread.h>
-
User_extensions_List _User_extensions_List = {
CHAIN_INITIALIZER_EMPTY( _User_extensions_List.Active ),
CHAIN_ITERATOR_REGISTRY_INITIALIZER( _User_extensions_List.Iterators )
@@ -120,6 +118,8 @@ void _User_extensions_Thread_begin_visitor(
{
User_extensions_thread_begin_extension callout = callouts->thread_begin;
+ (void) arg;
+
if ( callout != NULL ) {
(*callout)( executing );
}
diff --git a/cpukit/score/src/watchdoginsert.c b/cpukit/score/src/watchdoginsert.c
index f75a28b15d..9d07fa01ed 100644
--- a/cpukit/score/src/watchdoginsert.c
+++ b/cpukit/score/src/watchdoginsert.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2016 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/watchdogremove.c b/cpukit/score/src/watchdogremove.c
index d264f793bb..1cb3450a02 100644
--- a/cpukit/score/src/watchdogremove.c
+++ b/cpukit/score/src/watchdogremove.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2016 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/watchdogtick.c b/cpukit/score/src/watchdogtick.c
index 6edb3f071a..695fee7e0f 100644
--- a/cpukit/score/src/watchdogtick.c
+++ b/cpukit/score/src/watchdogtick.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2015, 2016 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2015, 2016 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -83,9 +83,13 @@ void _Watchdog_Tick( Per_CPU_Control *cpu )
Thread_Control *executing;
const Thread_CPU_budget_operations *cpu_budget_operations;
+#ifdef RTEMS_SMP
if ( _Per_CPU_Is_boot_processor( cpu ) ) {
+#endif
++_Watchdog_Ticks_since_boot;
+#ifdef RTEMS_SMP
}
+#endif
_ISR_lock_ISR_disable_and_acquire( &cpu->Watchdog.Lock, &lock_context );
diff --git a/cpukit/score/src/watchdogtimeslicedefault.c b/cpukit/score/src/watchdogtimeslicedefault.c
index 56f6bdb5d5..4b6adf6cba 100644
--- a/cpukit/score/src/watchdogtimeslicedefault.c
+++ b/cpukit/score/src/watchdogtimeslicedefault.c
@@ -10,7 +10,7 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/wkspace.c b/cpukit/score/src/wkspace.c
index 5b8c980384..3309658dff 100644
--- a/cpukit/score/src/wkspace.c
+++ b/cpukit/score/src/wkspace.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/wkspaceisunifieddefault.c b/cpukit/score/src/wkspaceisunifieddefault.c
index db38c968b7..ee1cdf1676 100644
--- a/cpukit/score/src/wkspaceisunifieddefault.c
+++ b/cpukit/score/src/wkspaceisunifieddefault.c
@@ -10,7 +10,7 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/wkspacemallocinitdefault.c b/cpukit/score/src/wkspacemallocinitdefault.c
index 6ee951cff1..42f4b5c68b 100644
--- a/cpukit/score/src/wkspacemallocinitdefault.c
+++ b/cpukit/score/src/wkspacemallocinitdefault.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/wkspacemallocinitunified.c b/cpukit/score/src/wkspacemallocinitunified.c
index d21ef22d19..a35ee73175 100644
--- a/cpukit/score/src/wkspacemallocinitunified.c
+++ b/cpukit/score/src/wkspacemallocinitunified.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/src/wkstringduplicate.c b/cpukit/score/src/wkstringduplicate.c
index b8111e1fa7..63ab8c240f 100644
--- a/cpukit/score/src/wkstringduplicate.c
+++ b/cpukit/score/src/wkstringduplicate.c
@@ -10,7 +10,7 @@
*/
/*
- * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2011 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions