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-rw-r--r--cpukit/score/src/threaddispatch.c57
1 files changed, 43 insertions, 14 deletions
diff --git a/cpukit/score/src/threaddispatch.c b/cpukit/score/src/threaddispatch.c
index 1d317ad2b1..7c3326803c 100644
--- a/cpukit/score/src/threaddispatch.c
+++ b/cpukit/score/src/threaddispatch.c
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
/**
* @file
*
@@ -13,11 +15,28 @@
* COPYRIGHT (c) 1989-2009.
* On-Line Applications Research Corporation (OAR).
*
- * Copyright (c) 2014, 2018 embedded brains GmbH.
+ * Copyright (C) 2014, 2018 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
*
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
*/
#ifdef HAVE_CONFIG_H
@@ -172,8 +191,8 @@ static ISR_Level _Thread_Preemption_intervention(
Thread_Control *the_thread;
node = _Chain_Get_first_unprotected( &cpu_self->Threads_in_need_for_help );
- _Chain_Set_off_chain( node );
the_thread = THREAD_OF_SCHEDULER_HELP_NODE( node );
+ the_thread->Scheduler.ask_for_help_cpu = NULL;
_Per_CPU_Release( cpu_self, &lock_context );
@@ -275,25 +294,31 @@ void _Thread_Do_dispatch( Per_CPU_Control *cpu_self, ISR_Level level )
executing = cpu_self->executing;
do {
- Thread_Control *heir;
+ Thread_Control *heir;
+ const Thread_CPU_budget_operations *cpu_budget_operations;
level = _Thread_Preemption_intervention( executing, cpu_self, level );
heir = _Thread_Get_heir_and_make_it_executing( cpu_self );
/*
- * When the heir and executing are the same, then we are being
- * requested to do the post switch dispatching. This is normally
- * done to dispatch signals.
+ * If the heir and executing are the same, then there is no need to do a
+ * context switch. Proceed to run the post switch actions. This is
+ * normally done to dispatch signals.
*/
- if ( heir == executing )
- goto post_switch;
+ if ( heir == executing ) {
+ break;
+ }
/*
* Since heir and executing are not the same, we need to do a real
* context switch.
*/
- if ( heir->budget_algorithm == THREAD_CPU_BUDGET_ALGORITHM_RESET_TIMESLICE )
- heir->cpu_time_budget = rtems_configuration_get_ticks_per_timeslice();
+
+ cpu_budget_operations = heir->CPU_budget.operations;
+
+ if ( cpu_budget_operations != NULL ) {
+ ( *cpu_budget_operations->at_context_switch )( heir );
+ }
_ISR_Local_enable( level );
@@ -317,7 +342,11 @@ void _Thread_Do_dispatch( Per_CPU_Control *cpu_self, ISR_Level level )
_ISR_Local_disable( level );
} while ( cpu_self->dispatch_necessary );
-post_switch:
+ /*
+ * We are done with context switching. Proceed to run the post switch
+ * actions.
+ */
+
_Assert( cpu_self->thread_dispatch_disable_level == 1 );
cpu_self->thread_dispatch_disable_level = 0;
_Profiling_Thread_dispatch_enable( cpu_self, 0 );