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-rw-r--r--cpukit/score/cpu/aarch64/aarch64-exception-default.c20
-rw-r--r--cpukit/score/cpu/aarch64/cpu.c2
-rw-r--r--cpukit/score/cpu/aarch64/include/rtems/score/cpu.h2
-rw-r--r--cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h3
-rw-r--r--cpukit/score/cpu/arm/__aeabi_read_tp.c6
-rw-r--r--cpukit/score/cpu/arm/__tls_get_addr.c6
-rw-r--r--cpukit/score/cpu/arm/armv7m-context-initialize.c2
-rw-r--r--cpukit/score/cpu/arm/cpu.c17
-rw-r--r--cpukit/score/cpu/arm/include/rtems/score/cpu.h10
-rw-r--r--cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h2
-rw-r--r--cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h2
-rw-r--r--cpukit/score/cpu/i386/cpu.c2
-rw-r--r--cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h2
-rw-r--r--cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h2
-rw-r--r--cpukit/score/cpu/m68k/__m68k_read_tp.c4
-rw-r--r--cpukit/score/cpu/m68k/cpu.c5
-rw-r--r--cpukit/score/cpu/m68k/include/rtems/score/cpu.h1
-rw-r--r--cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h2
-rw-r--r--cpukit/score/cpu/microblaze/__tls_get_addr.c10
-rw-r--r--cpukit/score/cpu/microblaze/cpu.c2
-rw-r--r--cpukit/score/cpu/microblaze/include/rtems/score/cpu.h1
-rw-r--r--cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h3
-rw-r--r--cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h2
-rw-r--r--cpukit/score/cpu/moxie/include/rtems/score/cpu.h2
-rw-r--r--cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h2
-rw-r--r--cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h2
-rw-r--r--cpukit/score/cpu/nios2/nios2-context-initialize.c5
-rw-r--r--cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h3
-rw-r--r--cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h18
-rw-r--r--cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h2
-rw-r--r--cpukit/score/cpu/powerpc/cpu.c1
-rw-r--r--cpukit/score/cpu/powerpc/include/rtems/score/cpu.h9
-rw-r--r--cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h2
-rw-r--r--cpukit/score/cpu/riscv/cpu.c12
-rw-r--r--cpukit/score/cpu/riscv/include/libcpu/access.h25
-rw-r--r--cpukit/score/cpu/riscv/include/rtems/score/cpu.h28
-rw-r--r--cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h12
-rw-r--r--cpukit/score/cpu/riscv/riscv-context-initialize.c2
-rw-r--r--cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h2
-rw-r--r--cpukit/score/cpu/sparc/cpu.c2
-rw-r--r--cpukit/score/cpu/sparc/include/libcpu/grlib-tn-0018.h2
-rw-r--r--cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h2
-rw-r--r--cpukit/score/cpu/sparc64/cpu.c2
-rw-r--r--cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h2
-rw-r--r--cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h2
-rw-r--r--cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h2
46 files changed, 168 insertions, 81 deletions
diff --git a/cpukit/score/cpu/aarch64/aarch64-exception-default.c b/cpukit/score/cpu/aarch64/aarch64-exception-default.c
index 3494c88ea6..f1591cbd5d 100644
--- a/cpukit/score/cpu/aarch64/aarch64-exception-default.c
+++ b/cpukit/score/cpu/aarch64/aarch64-exception-default.c
@@ -48,6 +48,26 @@
void _AArch64_Exception_default( CPU_Exception_frame *frame )
{
+ uint64_t EC = AARCH64_ESR_EL1_EC_GET( frame->register_syndrome );
+
+ /* Emulate FPSR flags for FENV if a FPU exception occurred */
+ if ( EC == 0x2c ) {
+ /*
+ * This must be done because FENV depends on FPSR values, but trapped FPU
+ * exceptions don't set FPSR bits. In the case where a signal is mapped, the
+ * signal code executes after the exception frame is restored and FENV
+ * functions executed in that context will need this information to be
+ * accurate.
+ */
+ uint64_t ISS = AARCH64_ESR_EL1_EC_GET( frame->register_syndrome );
+
+ /* If the exception bits are valid, use them */
+ if ( ( ISS & ( 1 << 23 ) ) != 0 ) {
+ /* The bits of the lower byte match the FPSR exception bits */
+ frame->register_fpsr |= ( ISS & 0xff );
+ }
+ }
+
rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame );
}
diff --git a/cpukit/score/cpu/aarch64/cpu.c b/cpukit/score/cpu/aarch64/cpu.c
index 923f53da08..207508302b 100644
--- a/cpukit/score/cpu/aarch64/cpu.c
+++ b/cpukit/score/cpu/aarch64/cpu.c
@@ -142,7 +142,7 @@ void _CPU_Context_Initialize(
the_context->thread_id = (uintptr_t) tls_area;
if ( tls_area != NULL ) {
- _TLS_TCB_at_area_begin_initialize( tls_area );
+ the_context->thread_id = (uintptr_t) _TLS_Initialize_area( tls_area );
}
}
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
index 399e0fc802..aa4f90f1a8 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
@@ -102,7 +102,7 @@
#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
-#define CPU_STACK_MINIMUM_SIZE (1024 * 10)
+#define CPU_STACK_MINIMUM_SIZE (1024 * 8)
/* This could be either 4 or 8, depending on the ABI in use.
* Could also use __LP64__ or __ILP32__ */
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
index 880ae7d9f7..b520e8bffb 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
@@ -50,8 +50,11 @@
*/
#define CPU_PER_CPU_CONTROL_SIZE 0
+
#define CPU_INTERRUPT_FRAME_SIZE 0x2E0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 11
+
#ifndef ASM
#ifdef __cplusplus
diff --git a/cpukit/score/cpu/arm/__aeabi_read_tp.c b/cpukit/score/cpu/arm/__aeabi_read_tp.c
index 671065825d..8ae218bbcb 100644
--- a/cpukit/score/cpu/arm/__aeabi_read_tp.c
+++ b/cpukit/score/cpu/arm/__aeabi_read_tp.c
@@ -42,15 +42,15 @@ void __attribute__((naked)) __aeabi_read_tp(void)
"ldr r0, =_Per_CPU_Information\n"
"ldr r0, [r0, %[executingoff]]\n"
#if defined(__thumb__) && !defined(__thumb2__)
- "add r0, %[tlsareaoff]\n"
+ "add r0, %[threadidoff]\n"
"ldr r0, [r0]\n"
#else
- "ldr r0, [r0, %[tlsareaoff]]\n"
+ "ldr r0, [r0, %[threadidoff]]\n"
#endif
"bx lr\n"
:
: [executingoff] "I" (offsetof(Per_CPU_Control, executing)),
- [tlsareaoff] "I" (offsetof(Thread_Control, Start.tls_area))
+ [threadidoff] "I" (offsetof(Thread_Control, Registers.thread_id))
);
}
diff --git a/cpukit/score/cpu/arm/__tls_get_addr.c b/cpukit/score/cpu/arm/__tls_get_addr.c
index 5c8e60ae06..d75ddf93de 100644
--- a/cpukit/score/cpu/arm/__tls_get_addr.c
+++ b/cpukit/score/cpu/arm/__tls_get_addr.c
@@ -39,10 +39,10 @@ void *__tls_get_addr(const TLS_Index *ti);
void *__tls_get_addr(const TLS_Index *ti)
{
const Thread_Control *executing = _Thread_Get_executing();
- void *tls_block = (char *) executing->Start.tls_area
- + _TLS_Get_thread_control_block_area_size( (uintptr_t) _TLS_Alignment );
+ void *tls_data = (char *) executing->Registers.thread_id
+ + _TLS_Get_thread_control_block_area_size();
assert(ti->module == 1);
- return (char *) tls_block + ti->offset;
+ return (char *) tls_data + ti->offset;
}
diff --git a/cpukit/score/cpu/arm/armv7m-context-initialize.c b/cpukit/score/cpu/arm/armv7m-context-initialize.c
index 6bdedecb77..a078c8f757 100644
--- a/cpukit/score/cpu/arm/armv7m-context-initialize.c
+++ b/cpukit/score/cpu/arm/armv7m-context-initialize.c
@@ -61,7 +61,7 @@ void _CPU_Context_Initialize(
context->register_sp = stack_area_end;
if ( tls_area != NULL ) {
- _TLS_TCB_at_area_begin_initialize( tls_area );
+ context->thread_id = (uint32_t) _TLS_Initialize_area( tls_area );
}
}
diff --git a/cpukit/score/cpu/arm/cpu.c b/cpukit/score/cpu/arm/cpu.c
index b2cc6039b0..b685c4d6ab 100644
--- a/cpukit/score/cpu/arm/cpu.c
+++ b/cpukit/score/cpu/arm/cpu.c
@@ -56,13 +56,11 @@
);
#endif
-#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
- RTEMS_STATIC_ASSERT(
- offsetof( Context_Control, thread_id )
- == ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET,
- ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET
- );
-#endif
+RTEMS_STATIC_ASSERT(
+ offsetof( Context_Control, thread_id )
+ == ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET,
+ ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET
+);
#ifdef ARM_MULTILIB_ARCH_V4
RTEMS_STATIC_ASSERT(
@@ -118,13 +116,10 @@ void _CPU_Context_Initialize(
the_context->register_sp = (uint32_t) stack_area_begin + stack_area_size;
the_context->register_lr = (uint32_t) entry_point;
the_context->isr_dispatch_disable = 0;
-
-#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
the_context->thread_id = (uint32_t) tls_area;
-#endif
if ( tls_area != NULL ) {
- _TLS_TCB_at_area_begin_initialize( tls_area );
+ the_context->thread_id = (uint32_t) _TLS_Initialize_area( tls_area );
}
}
diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu.h b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
index beb917a0b7..70b53ded62 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
@@ -176,9 +176,7 @@
#define CPU_MAXIMUM_PROCESSORS 32
-#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
- #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44
-#endif
+#define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44
#ifdef ARM_MULTILIB_VFP
#define ARM_CONTEXT_CONTROL_D8_OFFSET 48
@@ -191,10 +189,8 @@
#ifdef RTEMS_SMP
#if defined(ARM_MULTILIB_VFP)
#define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112
- #elif defined(ARM_MULTILIB_HAS_THREAD_ID_REGISTER)
- #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48
#else
- #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 44
+ #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48
#endif
#endif
@@ -240,9 +236,7 @@ typedef struct {
#else
void *register_sp;
#endif
-#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
uint32_t thread_id;
-#endif
#ifdef ARM_MULTILIB_VFP
uint64_t register_d8;
uint64_t register_d9;
diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
index 6e8230ce30..56eccf2e6f 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
@@ -60,6 +60,8 @@
#endif /* ARM_MULTILIB_ARCH_V4 */
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 11
+
#ifndef ASM
#ifdef __cplusplus
diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
index a03bc596ba..695963858a 100644
--- a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
@@ -29,6 +29,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
diff --git a/cpukit/score/cpu/i386/cpu.c b/cpukit/score/cpu/i386/cpu.c
index e89cdebdbe..9a3b188d10 100644
--- a/cpukit/score/cpu/i386/cpu.c
+++ b/cpukit/score/cpu/i386/cpu.c
@@ -193,7 +193,7 @@ void _CPU_Context_Initialize(
the_context->esp = (void *) _stack;
if ( tls_area != NULL ) {
- tcb = (uint32_t) _TLS_TCB_after_TLS_block_initialize( tls_area );
+ tcb = (uint32_t) _TLS_Initialize_area( tls_area );
} else {
tcb = 0;
}
diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
index 4f99f64711..6f67fa2878 100644
--- a/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
@@ -50,6 +50,8 @@
#define CPU_INTERRUPT_FRAME_SIZE 52
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 20
+
#ifndef ASM
#ifdef __cplusplus
diff --git a/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
index dce0cc6017..c49012af1f 100644
--- a/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
@@ -28,6 +28,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
diff --git a/cpukit/score/cpu/m68k/__m68k_read_tp.c b/cpukit/score/cpu/m68k/__m68k_read_tp.c
index e15ac3fed3..43dd1d16ac 100644
--- a/cpukit/score/cpu/m68k/__m68k_read_tp.c
+++ b/cpukit/score/cpu/m68k/__m68k_read_tp.c
@@ -37,9 +37,7 @@ void __m68k_read_tp(void);
void __m68k_read_tp(void)
{
const Thread_Control *executing = _Thread_Get_executing();
- void *tp = (char *) executing->Start.tls_area +
- _TLS_Get_thread_control_block_area_size((uintptr_t) _TLS_Alignment)
- + 0x7000;
+ void *tp = executing->Registers.thread_pointer;
__asm__ volatile (
"move.l %0, %%a0"
diff --git a/cpukit/score/cpu/m68k/cpu.c b/cpukit/score/cpu/m68k/cpu.c
index 9f6fb9223e..44dc06cc91 100644
--- a/cpukit/score/cpu/m68k/cpu.c
+++ b/cpukit/score/cpu/m68k/cpu.c
@@ -279,6 +279,9 @@ void _CPU_Context_Initialize(
#endif
if ( tls_area != NULL ) {
- _TLS_TCB_before_TLS_block_initialize( tls_area );
+ the_context->thread_pointer =
+ (char *) _TLS_Initialize_area( tls_area ) + 0x7000;
+ } else {
+ the_context->thread_pointer = NULL;
}
}
diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpu.h b/cpukit/score/cpu/m68k/include/rtems/score/cpu.h
index 8fdcb8c15a..ae3194b9bb 100644
--- a/cpukit/score/cpu/m68k/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m68k/include/rtems/score/cpu.h
@@ -145,6 +145,7 @@ typedef struct {
#if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
uint8_t fpu_dis;
#endif
+ void *thread_pointer;
} Context_Control;
#define _CPU_Context_Get_SP( _context ) \
diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
index b94c846bf2..f712433833 100644
--- a/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
@@ -48,6 +48,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
diff --git a/cpukit/score/cpu/microblaze/__tls_get_addr.c b/cpukit/score/cpu/microblaze/__tls_get_addr.c
index e779a63488..b7e7890013 100644
--- a/cpukit/score/cpu/microblaze/__tls_get_addr.c
+++ b/cpukit/score/cpu/microblaze/__tls_get_addr.c
@@ -46,9 +46,11 @@ void *__tls_get_addr( const TLS_Index *ti );
void *__tls_get_addr( const TLS_Index *ti )
{
- const Thread_Control *executing = _Thread_Get_executing();
- void *tls_block = (char *) executing->Start.tls_area
- + _TLS_Get_thread_control_block_area_size( (uintptr_t) _TLS_Alignment );
+ const Thread_Control *executing;
- return (char *) tls_block + ti->offset;
+ (void) ti;
+
+ executing = _Thread_Get_executing();
+
+ return executing->Registers.thread_pointer;
}
diff --git a/cpukit/score/cpu/microblaze/cpu.c b/cpukit/score/cpu/microblaze/cpu.c
index 1e829a4714..823825d2b1 100644
--- a/cpukit/score/cpu/microblaze/cpu.c
+++ b/cpukit/score/cpu/microblaze/cpu.c
@@ -73,7 +73,7 @@ void _CPU_Context_Initialize(
context->rmsr = msr;
if ( tls_area != NULL ) {
- _TLS_TCB_at_area_begin_initialize( tls_area );
+ context->thread_pointer = _TLS_Initialize_area( tls_area );
}
}
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
index 1325962f7c..3d865732d6 100644
--- a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
@@ -137,6 +137,7 @@ typedef struct {
uint32_t r30;
uint32_t r31;
uint32_t rmsr;
+ void *thread_pointer;
} Context_Control;
/**
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
index 0b9e06cfa8..4e315e856d 100644
--- a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
@@ -49,8 +49,11 @@
*/
#define CPU_PER_CPU_CONTROL_SIZE 0
+
#define CPU_INTERRUPT_FRAME_SIZE 56
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#define MICROBLAZE_INTERRUPT_FRAME_R3 0
#define MICROBLAZE_INTERRUPT_FRAME_R4 4
#define MICROBLAZE_INTERRUPT_FRAME_R5 8
diff --git a/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h
index cb4c925630..64be130906 100644
--- a/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h
@@ -48,6 +48,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
diff --git a/cpukit/score/cpu/moxie/include/rtems/score/cpu.h b/cpukit/score/cpu/moxie/include/rtems/score/cpu.h
index b94d47ab31..cc1900a852 100644
--- a/cpukit/score/cpu/moxie/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/moxie/include/rtems/score/cpu.h
@@ -228,7 +228,7 @@ typedef struct {
*
* XXX
*/
-#define CPU_STACK_MINIMUM_SIZE (1536)
+#define CPU_STACK_MINIMUM_SIZE (2048)
/**
* Size of a pointer.
diff --git a/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h
index 9c6ae11d74..d009186bbc 100644
--- a/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h
@@ -48,6 +48,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
diff --git a/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h
index 56c2cb0108..f257cba55f 100644
--- a/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h
@@ -48,6 +48,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
diff --git a/cpukit/score/cpu/nios2/nios2-context-initialize.c b/cpukit/score/cpu/nios2/nios2-context-initialize.c
index fe458cc2ca..14a06374b4 100644
--- a/cpukit/score/cpu/nios2/nios2-context-initialize.c
+++ b/cpukit/score/cpu/nios2/nios2-context-initialize.c
@@ -90,9 +90,6 @@ void _CPU_Context_Initialize(
}
if ( tls_area != NULL ) {
- context->r23 = (uintptr_t) tls_area +
- _TLS_Get_thread_control_block_area_size( (uintptr_t) _TLS_Alignment ) +
- 0x7000;
- _TLS_TCB_before_TLS_block_initialize( tls_area );
+ context->r23 = (uintptr_t) _TLS_Initialize_area( tls_area ) + 0x7000;
}
}
diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
index 962fc486fc..9ef6f43eb9 100644
--- a/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
@@ -554,7 +554,8 @@ extern Context_Control_fp _CPU_Null_fp_context;
* @addtogroup RTEMSScoreCPUExampleContext
*
* Should be large enough to run all RTEMS tests. This ensures
- * that a "reasonable" small application should not have any problems.
+ * that a "reasonable" small application should not have any problems. The
+ * size shall be a power of two.
*
* Port Specific Information:
*
diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
index d5082383e8..72d223de24 100644
--- a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
@@ -54,6 +54,24 @@
*/
#define CPU_PER_CPU_CONTROL_SIZE 0
+/**
+ * @brief Defines the thread-local storage (TLS) variant.
+ *
+ * Use one of the following values:
+ *
+ * 10: The architecture uses Variant I and the TLS offsets emitted by the
+ * linker neglect the TCB (examples: nios2, m68k, microblaze, powerpc,
+ * riscv). The thread pointer directly references the thread-local data
+ * area.
+ *
+ * 11: The architecture uses Variant I and the TLS offsets emitted by the
+ * linker take the TCB into account (examples: arm, aarch64).
+ * The thread pointer references the TCB.
+ *
+ * 20: The architecture uses Variant II (examples: i386, sparc).
+ */
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h
index 352f14589a..8fbf8ba547 100644
--- a/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h
@@ -48,6 +48,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
diff --git a/cpukit/score/cpu/powerpc/cpu.c b/cpukit/score/cpu/powerpc/cpu.c
index bdb9cf6ab5..e809c93975 100644
--- a/cpukit/score/cpu/powerpc/cpu.c
+++ b/cpukit/score/cpu/powerpc/cpu.c
@@ -358,4 +358,5 @@ void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
: "r" (source), "r" (error)
: "memory"
);
+ RTEMS_UNREACHABLE();
}
diff --git a/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h
index 84f0bf3f65..4351cb97eb 100644
--- a/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h
@@ -449,8 +449,8 @@ static inline ppc_context *ppc_get_context( const Context_Control *context )
#endif
#ifndef ASM
-typedef struct {
#if (PPC_HAS_FPU == 1)
+typedef struct {
/* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
* procedure calls. However, this would mean that the interrupt
* frame had to hold f0-f13, and the fpscr. And as the majority
@@ -464,9 +464,8 @@ typedef struct {
float f[32];
uint32_t fpscr;
#endif
-#endif /* (PPC_HAS_FPU == 1) */
} Context_Control_fp;
-
+#endif /* (PPC_HAS_FPU == 1) */
#endif /* ASM */
/*
@@ -562,7 +561,9 @@ typedef struct {
* CPUs with a "floating point save context" instruction.
*/
+#if (PPC_HAS_FPU == 1)
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
+#endif
/*
* (Optional) # of bytes for libmisc/stackchk to check
@@ -940,6 +941,7 @@ RTEMS_NO_RETURN void _CPU_Context_switch_no_return(
RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
+#if (PPC_HAS_FPU == 1)
/*
* _CPU_Context_save_fp
*
@@ -959,6 +961,7 @@ void _CPU_Context_save_fp(
void _CPU_Context_restore_fp(
Context_Control_fp **fp_context_ptr
);
+#endif
#ifdef RTEMS_SMP
uint32_t _CPU_SMP_Initialize( void );
diff --git a/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h
index c81675b53d..fa223f9aa8 100644
--- a/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h
@@ -151,6 +151,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifdef RTEMS_SMP
/* Use SPRG0 for the per-CPU control of the current processor */
diff --git a/cpukit/score/cpu/riscv/cpu.c b/cpukit/score/cpu/riscv/cpu.c
index 62150d4ea5..926b2c3926 100644
--- a/cpukit/score/cpu/riscv/cpu.c
+++ b/cpukit/score/cpu/riscv/cpu.c
@@ -173,18 +173,6 @@ RTEMS_STATIC_ASSERT(
riscv_interrupt_frame_size
);
-void _init(void);
-
-void _fini(void);
-
-void _init(void)
-{
-}
-
-void _fini(void)
-{
-}
-
/**
* @brief Performs processor dependent initialization.
*/
diff --git a/cpukit/score/cpu/riscv/include/libcpu/access.h b/cpukit/score/cpu/riscv/include/libcpu/access.h
index 4f2a780895..f414d6f22f 100644
--- a/cpukit/score/cpu/riscv/include/libcpu/access.h
+++ b/cpukit/score/cpu/riscv/include/libcpu/access.h
@@ -1,12 +1,31 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
/*
* access.h - access routines for SPARC. SPARC is big endian only.
*
* COPYRIGHT (c) 2011
* Aeroflex Gaisler.
*
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LIBCPU_ACCESS_H
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index 88f7e7960c..f74ce99684 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -193,21 +193,19 @@ static inline bool _CPU_ISR_Is_enabled( unsigned long level )
static inline void _CPU_ISR_Set_level( uint32_t level )
{
- if ( ( level & CPU_MODES_INTERRUPT_MASK) == 0 ) {
- __asm__ volatile (
- ".option push\n"
- ".option arch, +zicsr\n"
- "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
- ".option pop"
- );
- } else {
- __asm__ volatile (
- ".option push\n"
- ".option arch, +zicsr\n"
- "csrrc zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
- ".option pop"
- );
- }
+ /*
+ * Where CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE, the only supported
+ * interrupt level allowed to set is 0 (interrupts enabled). This constraint
+ * is enforced by the API level functions which return an error status for
+ * other interrupt levels.
+ */
+ (void) level;
+ __asm__ volatile (
+ ".option push\n"
+ ".option arch, +zicsr\n"
+ "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
+ ".option pop"
+ );
}
uint32_t _CPU_ISR_Get_level( void );
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
index 5fd25e32cf..ea1e139d55 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
@@ -54,6 +54,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 16
#endif
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifdef RTEMS_SMP
#define RISCV_CONTEXT_IS_EXECUTING 0
#endif
@@ -296,6 +298,16 @@
extern "C" {
#endif
+static inline uint32_t _RISCV_Map_hardid_to_cpu_index( uint32_t hardid )
+{
+ return hardid - RISCV_BOOT_HARTID;
+}
+
+static inline uint32_t _RISCV_Map_cpu_index_to_hardid( uint32_t cpu_index )
+{
+ return cpu_index + RISCV_BOOT_HARTID;
+}
+
/* Core Local Interruptor (CLINT) */
typedef union {
diff --git a/cpukit/score/cpu/riscv/riscv-context-initialize.c b/cpukit/score/cpu/riscv/riscv-context-initialize.c
index c6bd99ebbd..572dc3ede3 100644
--- a/cpukit/score/cpu/riscv/riscv-context-initialize.c
+++ b/cpukit/score/cpu/riscv/riscv-context-initialize.c
@@ -68,7 +68,7 @@ void _CPU_Context_Initialize(
if ( tls_area != NULL ) {
void *tls_block;
- tls_block = _TLS_TCB_before_TLS_block_initialize( tls_area );
+ tls_block = _TLS_Initialize_area( tls_area );
context->tp = (uintptr_t) tls_block;
}
}
diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h
index 295b01eeaa..1746d677c0 100644
--- a/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h
@@ -29,6 +29,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c
index b910d96d8d..ca11229023 100644
--- a/cpukit/score/cpu/sparc/cpu.c
+++ b/cpukit/score/cpu/sparc/cpu.c
@@ -319,7 +319,7 @@ void _CPU_Context_Initialize(
the_context->isr_dispatch_disable = 0;
if ( tls_area != NULL ) {
- void *tcb = _TLS_TCB_after_TLS_block_initialize( tls_area );
+ void *tcb = _TLS_Initialize_area( tls_area );
the_context->g7 = (uintptr_t) tcb;
}
diff --git a/cpukit/score/cpu/sparc/include/libcpu/grlib-tn-0018.h b/cpukit/score/cpu/sparc/include/libcpu/grlib-tn-0018.h
index 62f33da6e8..bb43234128 100644
--- a/cpukit/score/cpu/sparc/include/libcpu/grlib-tn-0018.h
+++ b/cpukit/score/cpu/sparc/include/libcpu/grlib-tn-0018.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (C) 2020 Cobham Gailer AB
+ * Copyright (C) 2020 Cobham Gaisler AB
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h
index e98a75cf32..7a97db7097 100644
--- a/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h
@@ -120,6 +120,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
#endif
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 20
+
#if ( SPARC_HAS_FPU == 1 )
/**
* @brief Offset of the CPU_Per_CPU_control::fsr field relative to the
diff --git a/cpukit/score/cpu/sparc64/cpu.c b/cpukit/score/cpu/sparc64/cpu.c
index c93b68a2cc..ae3b359876 100644
--- a/cpukit/score/cpu/sparc64/cpu.c
+++ b/cpukit/score/cpu/sparc64/cpu.c
@@ -132,7 +132,7 @@ void _CPU_Context_Initialize(
the_context->isr_dispatch_disable = 0;
if ( tls_area != NULL ) {
- void *tcb = _TLS_TCB_after_TLS_block_initialize( tls_area );
+ void *tcb = _TLS_Initialize_area( tls_area );
the_context->g7 = (uintptr_t) tcb;
}
diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h
index 8df4c8814c..10fe696fab 100644
--- a/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h
@@ -48,6 +48,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 20
+
#ifndef ASM
#ifdef __cplusplus
diff --git a/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h
index 4b0f78c845..df0b9bc9e9 100644
--- a/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h
@@ -48,6 +48,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h
index 742763c168..bee49ca124 100644
--- a/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h
@@ -32,6 +32,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 20
+
#ifndef ASM
#ifdef __cplusplus