diff options
Diffstat (limited to 'cpukit/score/cpu/sparc64/include/rtems/score/cpu.h')
-rw-r--r-- | cpukit/score/cpu/sparc64/include/rtems/score/cpu.h | 60 |
1 files changed, 23 insertions, 37 deletions
diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h b/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h index e0f56b8e89..90ffe96341 100644 --- a/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -16,9 +18,26 @@ * to support the SPARC64 processor. * COPYRIGHT (c) 2010. Gedare Bloom. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _RTEMS_SCORE_CPU_H @@ -652,12 +671,6 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template; */ /* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* * Disable all interrupts for a critical section. The previous * level is returned in _level. */ @@ -684,7 +697,7 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template; #define _CPU_ISR_Flash( _level ) \ sparc_flash_interrupts( _level ) -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return ( level & SPARC_PSTATE_IE_MASK ) != 0; } @@ -775,25 +788,6 @@ void _CPU_Context_Initialize( /* end of Context handler macros */ -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _source, _error ) \ - do { \ - uint32_t level; \ - \ - level = sparc_disable_interrupts(); \ - __asm__ volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ - while (1); /* loop forever */ \ - } while (0) - -/* end of Fatal Error manager macros */ - #define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE /* Bitfield handler macros */ @@ -940,14 +934,6 @@ uint32_t _CPU_Counter_frequency( void ); CPU_Counter_ticks _CPU_Counter_read( void ); -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - /** Type that can store a 32-bit integer or a pointer. */ typedef uintptr_t CPU_Uint32ptr; |