diff options
Diffstat (limited to 'cpukit/score/cpu/sparc/cpu_asm.S')
| -rw-r--r-- | cpukit/score/cpu/sparc/cpu_asm.S | 64 |
1 files changed, 12 insertions, 52 deletions
diff --git a/cpukit/score/cpu/sparc/cpu_asm.S b/cpukit/score/cpu/sparc/cpu_asm.S index 16f5c70206..45d1495af7 100644 --- a/cpukit/score/cpu/sparc/cpu_asm.S +++ b/cpukit/score/cpu/sparc/cpu_asm.S @@ -295,7 +295,7 @@ SYM(_CPU_Context_restore): mov %i0, %o1 ! in the delay slot /* - * void _ISR_Handler() + * void _SPARC_Interrupt_trap() * * This routine provides the RTEMS interrupt management. * @@ -305,28 +305,14 @@ SYM(_CPU_Context_restore): * l0 = PSR * l1 = PC * l2 = nPC - * l3 = trap type + * l3 = interrupt vector number (this is not the trap type) * - * NOTE: By an executive defined convention, trap type is between 0 and 255 if - * it is an asynchonous trap and 256 and 511 if it is synchronous. + * NOTE: This trap handler is intended to service external interrupts. */ .align 4 - PUBLIC(_ISR_Handler) -SYM(_ISR_Handler): - /* - * Fix the return address for synchronous traps. - */ - - andcc %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0 - ! Is this a synchronous trap? - be,a win_ovflow ! No, then skip the adjustment - nop ! DELAY - mov %l1, %l6 ! save trapped pc for debug info - mov %l2, %l1 ! do not return to the instruction - add %l2, 4, %l2 ! indicated - -win_ovflow: + PUBLIC(_SPARC_Interrupt_trap) +SYM(_SPARC_Interrupt_trap): /* * Save the globals this block uses. * @@ -413,7 +399,7 @@ dont_do_the_window: * includes a regular minimum stack frame which will be used if * needed by register window overflow and underflow handlers. * - * REGISTERS SAME AS AT _ISR_Handler + * REGISTERS SAME AS AT _SPARC_Interrupt_trap() */ sub %fp, CPU_INTERRUPT_FRAME_SIZE, %sp @@ -439,9 +425,6 @@ dont_do_the_window: rd %y, %g1 st %g1, [%sp + ISF_Y_OFFSET] ! save y - st %l6, [%sp + ISF_TPC_OFFSET] ! save real trapped pc - - mov %sp, %o1 ! 2nd arg to ISR Handler /* * Increment ISR nest level and Thread dispatch disable level. @@ -520,26 +503,16 @@ dont_switch_stacks: sub %sp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp /* - * Check if we have an external interrupt (trap 0x11 - 0x1f). If so, - * set the PIL in the %psr to mask off interrupts with lower priority. + * Set the PIL in the %psr to mask off interrupts with lower priority. * The original %psr in %l0 is not modified since it will be restored * when the interrupt handler returns. */ mov %l0, %g5 - and %l3, 0x0ff, %g4 - subcc %g4, 0x11, %g0 - bl dont_fix_pil - subcc %g4, 0x1f, %g0 - bg dont_fix_pil - sll %g4, 8, %g4 + sll %l3, 8, %g4 and %g4, SPARC_PSR_PIL_MASK, %g4 andn %l0, SPARC_PSR_PIL_MASK, %g5 - ba pil_fixed or %g4, %g5, %g5 -dont_fix_pil: - or %g5, SPARC_PSR_PIL_MASK, %g5 -pil_fixed: #if SPARC_HAS_FPU == 1 /* @@ -552,23 +525,10 @@ pil_fixed: wr %g5, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** /* - * Vector to user's handler. - * - * NOTE: TBR may no longer have vector number in it since - * we just enabled traps. It is definitely in l3. + * Call _SPARC_Interrupt_dispatch( %l3 ) */ - - sethi %hi(SYM(_ISR_Vector_table)), %g4 - or %g4, %lo(SYM(_ISR_Vector_table)), %g4 - and %l3, 0xFF, %g5 ! remove synchronous trap indicator - sll %g5, 2, %g5 ! g5 = offset into table - ld [%g4 + %g5], %g4 ! g4 = _ISR_Vector_table[ vector ] - - - ! o1 = 2nd arg = address of the ISF - ! WAS LOADED WHEN ISF WAS SAVED!!! mov %l3, %o0 ! o0 = 1st arg = vector number - call %g4 + call SYM(_SPARC_Interrupt_dispatch) #if defined(RTEMS_PROFILING) mov %o5, %l3 ! save interrupt entry instant #else @@ -780,8 +740,8 @@ isr_dispatch: * The CWP in place at this point may be different from * that which was in effect at the beginning of the ISR if we * have been context switched between the beginning of this invocation - * of _ISR_Handler and this point. Thus the CWP and WIM should - * not be changed back to their values at ISR entry time. Any + * of _SPARC_Interrupt_trap() and this point. Thus the CWP and WIM + * should not be changed back to their values at ISR entry time. Any * changes to the PSR must preserve the CWP. */ |