diff options
Diffstat (limited to 'cpukit/score/cpu/sh/include')
-rw-r--r-- | cpukit/score/cpu/sh/include/rtems/asm.h | 137 | ||||
-rw-r--r-- | cpukit/score/cpu/sh/include/rtems/score/cpu.h | 738 | ||||
-rw-r--r-- | cpukit/score/cpu/sh/include/rtems/score/cpuatomic.h | 14 | ||||
-rw-r--r-- | cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h | 34 | ||||
-rw-r--r-- | cpukit/score/cpu/sh/include/rtems/score/sh.h | 277 | ||||
-rw-r--r-- | cpukit/score/cpu/sh/include/rtems/score/sh_io.h | 51 | ||||
-rw-r--r-- | cpukit/score/cpu/sh/include/rtems/score/types.h | 56 |
7 files changed, 1307 insertions, 0 deletions
diff --git a/cpukit/score/cpu/sh/include/rtems/asm.h b/cpukit/score/cpu/sh/include/rtems/asm.h new file mode 100644 index 0000000000..ac730310cd --- /dev/null +++ b/cpukit/score/cpu/sh/include/rtems/asm.h @@ -0,0 +1,137 @@ +/** + * @file + * + * @brief Address the Problems Caused by Incompatible Flavor of + * Assemblers and Toolsets + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * @note The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998-2001. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif + +#include <rtems/score/cpuopts.h> +#include <rtems/score/sh.h> + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +#include <rtems/concat.h> + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ +#define r0 REG (r0) +#define r1 REG (r1) +#define r2 REG (r2) +#define r3 REG (r3) +#define r4 REG (r4) +#define r5 REG (r5) +#define r6 REG (r6) +#define r7 REG (r7) +#define r8 REG (r8) +#define r9 REG (r9) +#define r10 REG (r10) +#define r11 REG (r11) +#define r12 REG (r12) +#define r13 REG (r13) +#define r14 REG (r14) +#define r15 REG (r15) +#define vbr REG (vbr) +#define gbr REG (gbr) +#define pr REG (pr) +#define mach REG (mach) +#define macl REG (macl) +#define sr REG (sr) +#define pc REG (pc) + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .global SYM (sym) +#define EXTERN(sym) .global SYM (sym) + +#endif diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpu.h b/cpukit/score/cpu/sh/include/rtems/score/cpu.h new file mode 100644 index 0000000000..c2b7081e9e --- /dev/null +++ b/cpukit/score/cpu/sh/include/rtems/score/cpu.h @@ -0,0 +1,738 @@ +/** + * @file rtems/score/cpu.h + */ + +/* + * This include file contains information pertaining to the Hitachi SH + * processor. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998-2006. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rtems/score/types.h> +#include <rtems/score/sh.h> + +/* conditional compilation parameters */ + +/* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * SH Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/* + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + */ + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/* + * We define the interrupt stack in the linker script + */ +#define CPU_ALLOCATE_INTERRUPT_STACK FALSE + +/* + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + */ + +#define CPU_ISR_PASSES_FRAME_POINTER FALSE + +/* + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * We currently support sh1 only, which has no FPU, other SHes have an FPU + * + * The macro name "SH_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + */ + +#if SH_HAS_FPU +#define CPU_HARDWARE_FP TRUE +#define CPU_SOFTWARE_FP FALSE +#else +#define CPU_SOFTWARE_FP FALSE +#define CPU_HARDWARE_FP FALSE +#endif + +/* + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + */ + +#if SH_HAS_FPU +#define CPU_ALL_TASKS_ARE_FP TRUE +#else +#define CPU_ALL_TASKS_ARE_FP FALSE +#endif + +/* + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + */ + +#if SH_HAS_FPU +#define CPU_IDLE_TASK_IS_FP TRUE +#else +#define CPU_IDLE_TASK_IS_FP FALSE +#endif + +/* + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + */ + +#if SH_HAS_FPU +#define CPU_USE_DEFERRED_FP_SWITCH FALSE +#else +#define CPU_USE_DEFERRED_FP_SWITCH TRUE +#endif + +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE + +/* + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * 1. BSP provided + * 2. CPU dependent (if provided) + * 3. generic (if no BSP and no CPU dependent) + */ + +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE + +/* + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + */ + +#define CPU_STACK_GROWS_UP FALSE + +/* FIXME: Is this the right value? */ +#define CPU_CACHE_LINE_BYTES 16 + +#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) + +/* + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). + */ + +#define CPU_MODES_INTERRUPT_MASK 0x0000000f + +#define CPU_MAXIMUM_PROCESSORS 32 + +/* + * Processor defined structures required for cpukit/score. + */ + +/* may need to put some structures here. */ + +/* + * Contexts + * + * Generally there are 2 types of context to save. + * 1. Interrupt registers to save + * 2. Task level registers to save + * + * This means we have the following 3 context items: + * 1. task level context stuff:: Context_Control + * 2. floating point task stuff:: Context_Control_fp + * 3. special interrupt level context :: Context_Control_interrupt + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + */ + +typedef struct { + uint32_t *r15; /* stack pointer */ + + uint32_t macl; + uint32_t mach; + uint32_t *pr; + + uint32_t *r14; /* frame pointer/call saved */ + + uint32_t r13; /* call saved */ + uint32_t r12; /* call saved */ + uint32_t r11; /* call saved */ + uint32_t r10; /* call saved */ + uint32_t r9; /* call saved */ + uint32_t r8; /* call saved */ + + uint32_t *r7; /* arg in */ + uint32_t *r6; /* arg in */ + +#if 0 + uint32_t *r5; /* arg in */ + uint32_t *r4; /* arg in */ +#endif + + uint32_t *r3; /* scratch */ + uint32_t *r2; /* scratch */ + uint32_t *r1; /* scratch */ + + uint32_t *r0; /* arg return */ + + uint32_t gbr; + uint32_t sr; + +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->r15 + +typedef struct { +#if SH_HAS_FPU +#ifdef SH4_USE_X_REGISTERS + union { + float f[16]; + double d[8]; + } x; +#endif + union { + float f[16]; + double d[8]; + } r; + float fpul; /* fp communication register */ + uint32_t fpscr; /* fp control register */ +#endif /* SH_HAS_FPU */ +} Context_Control_fp; + +typedef struct { +} CPU_Interrupt_frame; + +/* + * This variable is optional. It is used on CPUs on which it is difficult + * to generate an "uninitialized" FP context. It is filled in by + * _CPU_Initialize and copied into the task's FP context area during + * _CPU_Context_Initialize. + */ + +#if SH_HAS_FPU +extern Context_Control_fp _CPU_Null_fp_context; +#endif + +/* + * Nothing prevents the porter from declaring more CPU specific variables. + */ + +/* XXX: if needed, put more variables here */ +void CPU_delay( uint32_t microseconds ); + +/* + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + */ + +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +/* + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + */ + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/* + * This defines the number of entries in the ISR_Vector_table managed + * by RTEMS. + */ + +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) + +/* + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable _ISR_Nest_level. + */ + +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/* + * Should be large enough to run all RTEMS tests. This ensures + * that a "reasonable" small application should not have any problems. + * + * We have been able to run the sptests with this value, but have not + * been able to run the tmtest suite. + */ + +#define CPU_STACK_MINIMUM_SIZE 4096 + +#define CPU_SIZEOF_POINTER 4 + +/* + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + */ +#if defined(__SH4__) +/* FIXME: sh3 and SH3E? */ +#define CPU_ALIGNMENT 8 +#else +#define CPU_ALIGNMENT 4 +#endif + +/* + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, + * then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict + * enough for the partition, then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT + * is strict enough for the stack, then this should be set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. + */ + +#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT + +/* + * ISR handler macros + */ + +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + * + * SH Specific Information: NONE + */ + +#define _CPU_Initialize_vectors() + +/* + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in _level. + */ + +#define _CPU_ISR_Disable( _level) \ + sh_disable_interrupts( _level ) + +/* + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * _level is not modified. + */ + +#define _CPU_ISR_Enable( _level) \ + sh_enable_interrupts( _level) + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _level is not + * modified. + */ + +#define _CPU_ISR_Flash( _level) \ + sh_flash_interrupts( _level) + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + sh_get_interrupt_level( level ); + return level == 0; +} + +/* + * Map interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + * This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + */ + +#define _CPU_ISR_Set_level( _newlevel) \ + sh_set_interrupt_level(_newlevel) + +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* Context handler macros */ + +/* + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * NOTE: This is_fp parameter is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + */ + +/* + * FIXME: defined as a function for debugging - should be a macro + */ +void _CPU_Context_Initialize( + Context_Control *_the_context, + void *_stack_base, + uint32_t _size, + uint32_t _isr, + void (*_entry_point)(void), + int _is_fp, + void *_tls_area ); + +/* + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. Context_Restore should work most of the time. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + */ + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/* + * This routine initializes the FP context area passed to it to. + * There are a few standard ways in which to initialize the + * floating point context. The code included for this macro assumes + * that this is a CPU in which a "initial" FP context was saved into + * _CPU_Null_fp_context and it simply copies it to the destination + * context passed to it. + * + * Other models include (1) not doing anything, and (2) putting + * a "null FP status word" in the correct place in the FP context. + * SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have. + */ + +#if SH_HAS_FPU +#define _CPU_Context_Initialize_fp( _destination ) \ + do { \ + *(*(_destination)) = _CPU_Null_fp_context;\ + } while(0) +#else +#define _CPU_Context_Initialize_fp( _destination ) \ + { } +#endif + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/* + * FIXME: Trap32 ??? + * + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * invokes a Trap32 Instruction which returns to the breakpoint + * routine of cmon. + */ + +#ifdef BSP_FATAL_HALT + /* we manage the fatal error in the board support package */ + void bsp_fatal_halt( uint32_t _error); +#define _CPU_Fatal_halt( _source, _error ) bsp_fatal_halt( _error) +#else +#define _CPU_Fatal_halt( _source, _error)\ +{ \ + __asm__ volatile("mov.l %0,r0"::"m" (_error)); \ + __asm__ volatile("mov #1, r4"); \ + __asm__ volatile("trapa #34"); \ +} +#endif + +/* end of Fatal Error manager macros */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +/* functions */ + +/* + * @brief CPU Initialize + * + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + */ +void _CPU_Initialize(void); + +/* + * _CPU_ISR_install_raw_handler + * + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + */ + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + */ + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_Install_interrupt_stack + * + * This routine installs the hardware interrupt stack pointer. + * + * NOTE: It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + */ + +void _CPU_Install_interrupt_stack( void ); + +/* + * _CPU_Thread_Idle_body + * + * This routine is the CPU dependent IDLE thread body. + * + * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + */ + +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + */ + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/* + * _CPU_Context_restore + * + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + */ + +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +/* + * @brief This routine saves the floating point context passed to it. + * + * _CPU_Context_save_fp + * + */ +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); + +/* + * @brief This routine restores the floating point context passed to it. + * + * _CPU_Context_restore_fp + * + */ +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); + +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) +{ + /* TODO */ +} + +static inline void _CPU_Context_validate( uintptr_t pattern ) +{ + while (1) { + /* TODO */ + } +} + +/* FIXME */ +typedef CPU_Interrupt_frame CPU_Exception_frame; + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +typedef uint32_t CPU_Counter_ticks; + +CPU_Counter_ticks _CPU_Counter_read( void ); + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/sh/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/sh/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include <rtems/score/cpustdatomic.h> + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..789f2badd9 --- /dev/null +++ b/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h @@ -0,0 +1,34 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2013 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include <rtems/score/cpu.h> + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/sh/include/rtems/score/sh.h b/cpukit/score/cpu/sh/include/rtems/score/sh.h new file mode 100644 index 0000000000..4e26478b8b --- /dev/null +++ b/cpukit/score/cpu/sh/include/rtems/score/sh.h @@ -0,0 +1,277 @@ +/** + * @file + * + * @brief Hitachi SH CPU Department Source + * + * This include file contains information pertaining to the Hitachi SH + * processor. + */ + +/* + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE + * + * + * COPYRIGHT (c) 1998-2001. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_SH_H +#define _RTEMS_SCORE_SH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the "SH" family. + * + * It does this by setting variables to indicate which implementation + * dependent features are present in a particular member of the family. + */ + +/* + * Figure out all CPU Model Feature Flags based upon compiler + * predefines. + */ + +#if defined(__SH2E__) || defined(__SH3E__) + +/* FIXME: SH-DSP context not currently supported */ +#define SH_HAS_FPU 0 + +#elif defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) + +/* + * Define this if you want to use XD-registers. + * Then this registers will be saved/restored on context switch. + * ! They will not be saved/restored on interrupts! + */ +#define SH4_USE_X_REGISTERS 0 + +#if defined(__LITTLE_ENDIAN__) +#define SH_HAS_FPU 1 +#else +/* FIXME: Context_Control_fp does not support big endian */ +#warning FPU not supported +#define SH_HAS_FPU 0 +#endif + +#elif defined(__sh1__) || defined(__sh2__) || defined(__sh3__) +#define SH_HAS_FPU 0 +#else +#warning Cannot detect FPU support, assuming no FPU +#define SH_HAS_FPU 0 +#endif + +/* this should not be here */ +#ifndef CPU_MODEL_NAME +#define CPU_MODEL_NAME "SH-Multilib" +#endif + +/* + * If the following macro is set to 0 there will be no software irq stack + */ + +#ifndef SH_HAS_SEPARATE_STACKS +#define SH_HAS_SEPARATE_STACKS 1 +#endif + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "Hitachi SH" + +#ifndef ASM + +#if defined(__sh1__) || defined(__sh2__) + +/* + * Mask for disabling interrupts + */ +#define SH_IRQDIS_VALUE 0xf0 + +#define sh_disable_interrupts( _level ) \ + __asm__ volatile ( \ + "stc sr,%0\n\t" \ + "ldc %1,sr\n\t"\ + : "=&r" (_level ) \ + : "r" (SH_IRQDIS_VALUE) ); + +#define sh_enable_interrupts( _level ) \ + __asm__ volatile( "ldc %0,sr\n\t" \ + "nop\n\t" \ + :: "r" (_level) ); + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _level is not + * modified. + */ + +#define sh_flash_interrupts( _level ) \ + __asm__ volatile( \ + "ldc %1,sr\n\t" \ + "nop\n\t" \ + "ldc %0,sr\n\t" \ + "nop\n\t" \ + : : "r" (SH_IRQDIS_VALUE), "r" (_level) ); + +#else + +#define SH_IRQDIS_MASK 0xf0 + +#define sh_disable_interrupts( _level ) \ + __asm__ volatile ( \ + "stc sr,%0\n\t" \ + "mov %0,r5\n\t" \ + "or %1,r5\n\t" \ + "ldc r5,sr\n\t"\ + : "=&r" (_level ) \ + : "r" (SH_IRQDIS_MASK) \ + : "r5" ); + +#define sh_enable_interrupts( _level ) \ + __asm__ volatile( "ldc %0,sr\n\t" \ + "nop\n\t" \ + :: "r" (_level) ); + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _level is not + * modified. + */ + +#define sh_flash_interrupts( _level ) \ + __asm__ volatile( \ + "stc sr,r5\n\t" \ + "ldc %1,sr\n\t" \ + "nop\n\t" \ + "or %0,r5\n\t" \ + "ldc r5,sr\n\t" \ + "nop\n\t" \ + : : "r" (SH_IRQDIS_MASK), "r" (_level) : "r5"); + +#endif + +#define sh_get_interrupt_level( _level ) \ +{ \ + register uint32_t _tmpsr ; \ + \ + __asm__ volatile( "stc sr, %0" : "=r" (_tmpsr) ); \ + _level = (_tmpsr & 0xf0) >> 4 ; \ +} + +#define sh_set_interrupt_level( _newlevel ) \ +{ \ + register uint32_t _tmpsr; \ + \ + __asm__ volatile ( "stc sr, %0" : "=r" (_tmpsr) ); \ + _tmpsr = ( _tmpsr & ~0xf0 ) | ((_newlevel) << 4) ; \ + __asm__ volatile( "ldc %0,sr" :: "r" (_tmpsr) ); \ +} + +/* + * The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + */ + +static inline uint32_t sh_swap_u32( + uint32_t value +) +{ + register uint32_t swapped; + + __asm__ volatile ( + "swap.b %1,%0; " + "swap.w %0,%0; " + "swap.b %0,%0" + : "=r" (swapped) + : "r" (value) ); + + return( swapped ); +} + +static inline uint16_t sh_swap_u16( + uint16_t value +) +{ + register uint16_t swapped ; + + __asm__ volatile ( "swap.b %1,%0" : "=r" (swapped) : "r" (value) ); + + return( swapped ); +} + +#define CPU_swap_u32( value ) sh_swap_u32( value ) +#define CPU_swap_u16( value ) sh_swap_u16( value ) + +extern unsigned int sh_set_irq_priority( + unsigned int irq, + unsigned int prio ); + +#endif /* !ASM */ + +/* + * Bits on SH-4 registers. + * See SH-4 Programming manual for more details. + * + * Added by Alexandra Kossovsky <sasha@oktet.ru> + */ + +#if defined(__SH4__) +#define SH4_SR_MD 0x40000000 /* Priveleged mode */ +#define SH4_SR_RB 0x20000000 /* General register bank specifier */ +#define SH4_SR_BL 0x10000000 /* Exeption/interrupt masking bit */ +#define SH4_SR_FD 0x00008000 /* FPU disable bit */ +#define SH4_SR_M 0x00000200 /* For signed division: + divisor (module) is negative */ +#define SH4_SR_Q 0x00000100 /* For signed division: + dividend (and quotient) is negative */ +#define SH4_SR_IMASK 0x000000f0 /* Interrupt mask level */ +#define SH4_SR_IMASK_S 4 +#define SH4_SR_S 0x00000002 /* Saturation for MAC instruction: + if set, data in MACH/L register + is restricted to 48/32 bits + for MAC.W/L instructions */ +#define SH4_SR_T 0x00000001 /* 1 if last condiyion was true */ +#define SH4_SR_RESERV 0x8fff7d0d /* Reserved bits, read/write as 0 */ + +/* FPSCR -- FPU Status/Control Register */ +#define SH4_FPSCR_FR 0x00200000 /* FPU register bank specifier */ +#define SH4_FPSCR_SZ 0x00100000 /* FMOV 64-bit transfer mode */ +#define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point + operations flag */ + /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */ +#define SH4_FPSCR_DN 0x00040000 /* Treat denormalized number as zero */ +#define SH4_FPSCR_CAUSE 0x0003f000 /* FPU exeption cause field */ +#define SH4_FPSCR_CAUSE_S 12 +#define SH4_FPSCR_ENABLE 0x00000f80 /* FPU exeption enable field */ +#define SH4_FPSCR_ENABLE_s 7 +#define SH4_FPSCR_FLAG 0x0000007d /* FPU exeption flag field */ +#define SH4_FPSCR_FLAG_S 2 +#define SH4_FPSCR_RM 0x00000001 /* Rounding mode: + 1/0 -- round to zero/nearest */ +#define SH4_FPSCR_RESERV 0xffd00000 /* Reserved bits, read/write as 0 */ + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/sh/include/rtems/score/sh_io.h b/cpukit/score/cpu/sh/include/rtems/score/sh_io.h new file mode 100644 index 0000000000..8d81965f78 --- /dev/null +++ b/cpukit/score/cpu/sh/include/rtems/score/sh_io.h @@ -0,0 +1,51 @@ +/** + * @file + * + * @brief Macros to Access Memory Mapped Devices on the SH7000-Architecture + * + * These are some macros to access memory mapped devices + * on the SH7000-architecture. + */ + +/* + * Inspired from the linux kernel's include/asm/io.h + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1996-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998-2001. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_SH_IO_H +#define _RTEMS_SCORE_SH_IO_H + +#define readb(addr) (*(volatile unsigned char *) (addr)) +#define readw(addr) (*(volatile unsigned short *) (addr)) +#define readl(addr) (*(volatile unsigned int *) (addr)) +#define read8(addr) (*(volatile uint8_t *) (addr)) +#define read16(addr) (*(volatile uint16_t *) (addr)) +#define read32(addr) (*(volatile uint32_t *) (addr)) + +#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b)) +#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b)) +#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) +#define write8(b,addr) ((*(volatile uint8_t *) (addr)) = (b)) +#define write16(b,addr) ((*(volatile uint16_t *) (addr)) = (b)) +#define write32(b,addr) ((*(volatile uint32_t *) (addr)) = (b)) + +#define inb(addr) readb(addr) +#define outb(b,addr) writeb(b,addr) + +#endif diff --git a/cpukit/score/cpu/sh/include/rtems/score/types.h b/cpukit/score/cpu/sh/include/rtems/score/types.h new file mode 100644 index 0000000000..a449a6d6e3 --- /dev/null +++ b/cpukit/score/cpu/sh/include/rtems/score/types.h @@ -0,0 +1,56 @@ +/** + * @file + * + * @brief Hitachi SH CPU Type Definitions + * + * This include file contains information pertaining to the Hitachi SH + * processor. + */ + +/* + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998-2001. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include <rtems/score/basedefs.h> + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +typedef void sh_isr; +typedef void ( *sh_isr_entry )( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif |