1 files changed, 0 insertions, 43 deletions
diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpu.h b/cpukit/score/cpu/sh/include/rtems/score/cpu.h
index d3c9bc6d39..3952abeae5 100644
--- a/cpukit/score/cpu/sh/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sh/include/rtems/score/cpu.h
@@ -50,38 +50,6 @@ extern "C" {
 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
 
 /*
- *  Does RTEMS manage a dedicated interrupt stack in software?
- *
- *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
- *  If FALSE, nothing is done.
- *
- *  If the CPU supports a dedicated interrupt stack in hardware,
- *  then it is generally the responsibility of the BSP to allocate it
- *  and set it up.
- *
- *  If the CPU does not support a dedicated interrupt stack, then
- *  the porter has two options: (1) execute interrupts on the
- *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
- *  interrupt stack.
- *
- *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
- *
- *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
- */
-
-#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
-#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
-
-/*
- * We define the interrupt stack in the linker script
- */
-#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
-
-/*
  *  Does the RTEMS invoke the user's ISR with the vector number and
  *  a pointer to the saved interrupt frame (1) or just the vector
  *  number (0)?
@@ -641,17 +609,6 @@ void _CPU_ISR_install_vector(
 );
 
 /*
- *  _CPU_Install_interrupt_stack
- *
- *  This routine installs the hardware interrupt stack pointer.
- *
- *  NOTE:  It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
- *         is TRUE.
- */
-
-void _CPU_Install_interrupt_stack( void );
-
-/*
  *  _CPU_Thread_Idle_body
  *
  *  This routine is the CPU dependent IDLE thread body.