diff options
Diffstat (limited to 'cpukit/score/cpu/riscv/riscv-context-switch.S')
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-context-switch.S | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/cpukit/score/cpu/riscv/riscv-context-switch.S b/cpukit/score/cpu/riscv/riscv-context-switch.S index 830f8629a4..a00c842de2 100644 --- a/cpukit/score/cpu/riscv/riscv-context-switch.S +++ b/cpukit/score/cpu/riscv/riscv-context-switch.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham ALmatary <hesham@alumni.york.ac.uk> @@ -35,10 +35,14 @@ .section .text, "ax", @progbits .align 2 + .option arch, +zicsr PUBLIC(_CPU_Context_switch) PUBLIC(_CPU_Context_switch_no_return) PUBLIC(_CPU_Context_restore) +#ifdef RTEMS_SMP +PUBLIC(_RISCV_Start_multitasking) +#endif SYM(_CPU_Context_switch): SYM(_CPU_Context_switch_no_return): @@ -174,4 +178,16 @@ SYM(_CPU_Context_restore): sw a5, PER_CPU_OFFSET_EXECUTING(a2) j .Ltry_update_is_executing + +SYM(_RISCV_Start_multitasking): + mv a1, a0 + GET_SELF_CPU_CONTROL a2 + + /* Switch the stack to the temporary interrupt stack of this processor */ + addi sp, a2, PER_CPU_INTERRUPT_FRAME_AREA + CPU_INTERRUPT_FRAME_SIZE + + /* Enable interrupts */ + csrrs zero, mstatus, RISCV_MSTATUS_MIE + + j .Ltry_update_is_executing #endif |