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-rw-r--r--cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h39
1 files changed, 35 insertions, 4 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
index 5162cbbd51..13fd60ed8c 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
@@ -5,7 +5,7 @@
*/
/*
- * Copyright (c) 2013, 2018 embedded brains GmbH
+ * Copyright (C) 2013, 2018 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -54,6 +54,8 @@
#define CPU_PER_CPU_CONTROL_SIZE 16
#endif
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifdef RTEMS_SMP
#define RISCV_CONTEXT_IS_EXECUTING 0
#endif
@@ -296,6 +298,16 @@
extern "C" {
#endif
+static inline uint32_t _RISCV_Map_hardid_to_cpu_index( uint32_t hardid )
+{
+ return hardid - RISCV_BOOT_HARTID;
+}
+
+static inline uint32_t _RISCV_Map_cpu_index_to_hardid( uint32_t cpu_index )
+{
+ return cpu_index + RISCV_BOOT_HARTID;
+}
+
/* Core Local Interruptor (CLINT) */
typedef union {
@@ -325,7 +337,7 @@ typedef struct {
uint32_t priority[RISCV_PLIC_MAX_INTERRUPTS];
uint32_t pending[1024];
uint32_t enable[16320][32];
- RISCV_PLIC_hart_regs harts[CPU_MAXIMUM_PROCESSORS];
+ RISCV_PLIC_hart_regs harts[CPU_MAXIMUM_PROCESSORS + RISCV_BOOT_HARTID];
} RISCV_PLIC_regs;
typedef struct {
@@ -420,16 +432,35 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( "unimp" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ register uintptr_t tp __asm__( "tp" );
+
+ tp = context->tp;
+
+ /* Make sure that the register assignment is not optimized away */
+ __asm__ volatile ( "" : : "r" ( tp ) );
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ return (void *) context->tp;
+}
+
#ifdef __cplusplus
}
#endif