diff options
Diffstat (limited to 'cpukit/score/cpu/powerpc')
| -rw-r--r-- | cpukit/score/cpu/powerpc/.cvsignore | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/ChangeLog | 945 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/Makefile.am | 22 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/cpu.c | 17 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/preinstall.am | 50 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/rtems/asm.h | 271 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/rtems/powerpc/registers.h | 541 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/rtems/score/cpu.h | 979 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/rtems/score/powerpc.h | 168 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/rtems/score/types.h | 59 |
10 files changed, 3054 insertions, 0 deletions
diff --git a/cpukit/score/cpu/powerpc/.cvsignore b/cpukit/score/cpu/powerpc/.cvsignore new file mode 100644 index 0000000000..282522db03 --- /dev/null +++ b/cpukit/score/cpu/powerpc/.cvsignore @@ -0,0 +1,2 @@ +Makefile +Makefile.in diff --git a/cpukit/score/cpu/powerpc/ChangeLog b/cpukit/score/cpu/powerpc/ChangeLog new file mode 100644 index 0000000000..1d9117764e --- /dev/null +++ b/cpukit/score/cpu/powerpc/ChangeLog @@ -0,0 +1,945 @@ +2011-02-16 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/powerpc/registers.h: Added FSL_EIS_ATBL, FSL_EIS_ATBL, and + FSL_EIS_SPEFSCR defines. + +2011-02-15 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/powerpc/registers.h: Added MSR_UCLE, MSR_SPE, MSR_WE, and + MSR_UBLE defines. + +2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/powerpc/registers.h, rtems/score/cpu.h: + Use "__asm__" instead of "asm" for improved c99-compliance. + +2011-01-31 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/powerpc/registers.h: Changed Freescale EIS prefix. More + Freescale EIS defines. Added MSR_IS, MSR_DS, and MSR_PMM defines. + +2011-01-26 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/powerpc/registers.h: Added BOOKE_PIR define. + +2010-10-29 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/powerpc/registers.h: Added HID2 define. Fixed comments. + +2010-10-21 Joel Sherrill <joel.sherrill@oarcorp.com> + + * rtems/score/cpu.h: Add RTEMS_COMPILER_NO_RETURN_ATTRIBUTE to + _CPU_Context_restore() because it does not return. Telling GCC this + avoids generation of dead code. + +2010-07-29 Gedare Bloom <giddyup44@yahoo.com> + + PR 1635/cpukit + * rtems/score/cpu.h, rtems/score/types.h: Refactoring of priority + handling, to isolate the bitmap implementation of priorities in the + supercore so that priority management is a little more modular. This + change is in anticipation of scheduler implementations that can + select how they manage tracking priority levels / finding the highest + priority ready task. Note that most of the changes here are simple + renaming, to clarify the use of the bitmap-based priority management. + +2010-07-16 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/new-exceptions/cpu.h: Removed file. + * Makefile.am, preinstall.am: Reflect change above. + * rtems/score/cpu.h: Include <rtems/score/types.h> first. Added + contents of <rtems/new-exceptions/cpu.h>. + * rtems/score/types.h: Use <rtems/score/basedefs.h> header file. + +2010-06-30 Peter Dufault <dufault@hda.com> + + PR 1588/cpukit + * rtems/powerpc/registers.h: Renamed defines SR0 .. SR15 in + PPC_SR0 .. PPC_SR15. + +2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com> + + PR 1573/cpukit + * rtems/new-exceptions/cpu.h: Add a per cpu data structure which + contains the information required by RTEMS for each CPU core. This + encapsulates information such as thread executing, heir, idle and + dispatch needed. + +2010-03-27 Joel Sherrill <joel.sherrill@oarcorp.com> + + * cpu.c: Add include of config.h + +2009-12-01 Till Straumann <strauman@slac.stanford.edu> + + * score/cpu/powerpc/rtems/score/cpu.h: Added space for non- + volatile AltiVec registers to context struct. Added declaration + for AltiVec-related routines to be implemented by CPU/BSP + support. + +2009-10-21 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + + * score/cpu/powerpc/rtems/score/cpu.h: moved timebase/decrementer + access from cpukit to libcpu + +2009-10-21 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/powerpc/registers.h: Added defines DEAR_BOOKE and DEAR_405. + * rtems/score/cpu.h: Changed fpscr field to an integer type in + Context_Control_fp. Fixed warnings in PPC_Set_timebase_register(). + Changed _CPU_Context_Initialize_fp() to initialize all fields and + avoid floating-point instructions. + * rtems/score/powerpc.h: Removed PPC_INIT_FPSCR define. + +2009-02-27 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/powerpc/registers.h: Added Freescale Book E Implementation + Standards (EIS) special purpose register definitions for MMU and L1 + cache. + +2009-02-11 Joel Sherrill <joel.sherrill@oarcorp.com> + + * rtems/new-exceptions/cpu.h, rtems/score/cpu.h: Eliminate + _CPU_Thread_dispatch_pointer and passing address of _Thread_Dispatch + to _CPU_Initialize. Clean up comments. + +2008-09-14 Joel Sherrill <joel.sherrill@oarcorp.com> + + * rtems/score/cpu.h: Move extern of bsp_clicks_per_usec so it is not + nested inside braces. + +2008-09-11 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: Do not define boolean, single_precision, + double_precision unless RTEMS_DEPRECATED_TYPES is given. + +2008-09-05 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/new-exceptions/cpu.h, rtems/score/cpu.h: Convert to "bool". + +2008-08-21 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: Include stdbool.h. + Use bool as base-type for boolean. + +2008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/powerpc/registers.h: Removed obsolete defines MSR_, MSR_KERNEL + and MSR_USER. Added missing prototypes. + +2008-08-04 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/new-exceptions/cpu.h: Changed define + CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER to UINT32_MAX to avoid comparison + between signed and unsigned. + +2008-07-18 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/powerpc/registers.h: Added masks for BOOKE_TCR fields. + +2008-07-14 Thomas Doerfler <thomas.doerfler@embedded-brains.de> + * rtems/powerpc/registers.h: + + Added PPC405EX support contributed by Michael Hamel + +2008-07-10 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/asm.h: Added defines for save and restore registers and + special purpose registers 4 to 7. + + * rtems/new-exceptions/cpu.h: Changed define PPC_BSP_HAS_FIXED_PR288 to + a value that results in a compile time error on usage since SPRG0 is + now used for the interrupt disable mask. + + * rtems/powerpc/registers.h: Bugfix: Swapped values of TBWU and TBWL. + + Added defines SPRG4..7 and USPRG0. + + Changed _CPU_ISR_{Disable, Enable, Flush} to use static inline + functions. The interrupt disable mask is now stored in SPRG0. Which + was previously denoted to indicate a PR288 bugfix. You may now + initialize the interrupt disable mask via + ppc_interrupt_set_disable_mask() and + PPC_INTERRUPT_DISABLE_MASK_DEFAULT. The default value will be set in + bootcard.c. + +2008-02-20 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/old-exceptions/cpu.h: Remove (Abandoned). + * rtems/score/cpu.h: Remove ref to rtems/old-exceptions/cpu.h. + * Makefile.am: Remove ref to rtems/old-exceptions/cpu.h. + +2007-12-17 Joel Sherrill <joel.sherrill@oarcorp.com> + + * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility. + +2007-12-17 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/powerpc/registers.h, rtems/score/cpu.h: Sweep to make sure grep + for COPYRIGHT passes. + +2007-12-03 Till Straumann <strauman@slac.stanford.edu> + + * rtems/powerpc/registers.h: added definitions for MSR_CE, + MSR_DE (bookE). + +2007-12-06 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/old-exceptions/cpu.h: Remove extra ifndef. + +2007-12-04 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/new-exceptions/cpu.h, rtems/old-exceptions/cpu.h, + rtems/score/cpu.h: Move interrupt_stack_size field from CPU Table to + Configuration Table. Eliminate CPU Table from all ports. Delete + references to CPU Table in all forms. + +2007-12-03 Till Straumann <strauman@slac.stanford.edu> + + * rtems/score/cpu.h: Added comment that GDB patch sim/2376 + is needed for reading the time-base with the new (more + portable) method. + +2007-12-03 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/new-exceptions/cpu.h, rtems/old-exceptions/cpu.h: Moved most of + the remaining CPU Table fields to the Configuration Table. This + included pretasking_hook, predriver_hook, postdriver_hook, idle_task, + do_zero_of_workspace, extra_mpci_receive_server_stack, + stack_allocate_hook, and stack_free_hook. As a side-effect of this + effort some multiprocessing code was made conditional and some style + clean up occurred. + +2007-11-30 Till Straumann <strauman@slac.stanford.edu> + + * rtems/score/cpu.h: Wonderful bookE doesn't have mftb/mftbu; + ( CPU_Get_timebase_low() ) they only define the TBRU/TBRL SPRs + so we use these. Should work on all CPUs. + +2007-11-28 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/new-exceptions/cpu.h, rtems/old-exceptions/cpu.h, + rtems/score/cpu.h: Eliminate PowerPC specific elements from the CPU + Table. They have been replaced with variables named bsp_XXX as + needed. + +2007-11-13 Till Straumann <strauman@slac.stanford.edu> + + * rtems/score/powerpc.h: Added a '__ppc_generic' CPU variant. + The goal would be making cpukit and hopefully libcpu work + for all (or at least most) CPUs/BSPs with -D__ppc_generic so + that eventually all tests [#if defined(<cpu_flavor>)] for CPU + flavors can be eliminated. + +2007-11-13 Till Straumann <strauman@slac.stanford.edu> + + * rtems/powerpc/registers.h: Added SPR definitions for BookE + DECAR, TCR, TSR. + +2007-05-09 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES. + +2007-04-17 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/score/cpu.h: + Use Context_Control_fp* instead of void* for fp_contexts. + Eliminate evil casts. + +2006-12-12 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/score/ppc.h: Remove (Deprecated in 4.7). + * Makefile: Remove rtems/score/ppc.h. + +2006-11-17 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: Remove unsigned64, signed64. + +2006-08-09 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: Because gcc implicitly uses floating point turn on + floating point for all threads if there is a hardware FPU. + +2006-07-12 Till Straumann <strauman@slac.stanford.edu> + + * rtems/old-exceptions/cpu.h, rtems/powerpc/registers.h: + Checked inline assembly; added early-clobber '&' to output operands + of multi-instruction asms. + +2006-01-16 Joel Sherrill <joel@OARcorp.com> + + * rtems/new-exceptions/cpu.h, rtems/old-exceptions/cpu.h, + rtems/score/cpu.h: Part of a large patch to improve Doxygen output. + As a side-effect, grammar and spelling errors were corrected, spacing + errors were address, and some variable names were improved. + +2005-11-08 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: Eliminate unsigned16, unsigned32. + +2005-11-02 Till Straumann <strauman@slac.stanford.edu> + + * rtems/powerpc/registers.h: recognize mpc7457 CPU; added definitions + for high bats (#4..7) on 7450 CPUs + +2005-10-27 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/asm.h: Remove private version of CONCAT macros. + Include <rtems/concat.h> instead. + +2005-05-06 Jennifer Averett <jennifer.averett@oarcorp.com> + + * rtems/score/powerpc.h: Removed warning + +2005-02-21 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/powerpc.h: Add "defined(mpc7400) || defined(mpc7450) + || defined(mpc7455)" to altivec (gcc-3.2.x compatibility). + +2005-02-18 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/new-exceptions/cpu.h (CPU_HARDWARE_FP, CPU_ALL_TASKS_ARE_FP, + CPU_IDLE_TASK_IS_FP): Remove. + * rtems/old-exceptions/cpu.h (CPU_HARDWARE_FP, CPU_ALL_TASKS_ARE_FP, + CPU_IDLE_TASK_IS_FP): Remove. + * rtems/score/cpu.h (CPU_HARDWARE_FP, CPU_ALL_TASKS_ARE_FP, + CPU_IDLE_TASK_IS_FP, CPU_SOFTWARE_FP): New. + +2005-02-18 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/cpu.h: Derive CPU_{BIG|LITTLE}_ENDIAN from + __BIG_ENDIAN__. + +2005-02-18 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/cpu.h (CPU_PROVIDES_IDLE_THREAD_BODY, + CPU_STACK_GROWS_UP, CPU_STRUCTURE_ALIGNMENT, + CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES, CPU_BIG_ENDIAN, + CPU_LITTLE_ENDIAN): Add. + * rtems/old-exceptions/cpu.h (CPU_PROVIDES_IDLE_THREAD_BODY, + CPU_STACK_GROWS_UP, CPU_STRUCTURE_ALIGNMENT, + CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES, CPU_BIG_ENDIAN, + CPU_LITTLE_ENDIAN): Remove. + * rtems/new-exceptions/cpu.h (CPU_PROVIDES_IDLE_THREAD_BODY, + CPU_STACK_GROWS_UP, CPU_STRUCTURE_ALIGNMENT, + CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES, CPU_BIG_ENDIAN, + CPU_LITTLE_ENDIAN): Remove. + +2005-02-18 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/cpu.h: + (rtems_cpu_configuration_get_serial_per_sec, + rtems_cpu_configuration_get_serial_external_clock, + rtems_cpu_configuration_get_serial_xon_xoff, + rtems_cpu_configuration_get_serial_cts_rts, + rtems_cpu_configuration_get_serial_rate, + rtems_cpu_configuration_get_timer_average_overhead, + rtems_cpu_configuration_get_timer_least_valid, + rtems_cpu_configuration_get_timer_internal_clock, + rtems_cpu_configuration_get_clock_speed): New. + * rtems/old-exceptions/cpu.h: + (rtems_cpu_configuration_get_serial_per_sec, + rtems_cpu_configuration_get_serial_external_clock, + rtems_cpu_configuration_get_serial_xon_xoff, + rtems_cpu_configuration_get_serial_cts_rts, + rtems_cpu_configuration_get_serial_rate, + rtems_cpu_configuration_get_timer_average_overhead, + rtems_cpu_configuration_get_timer_least_valid, + rtems_cpu_configuration_get_timer_internal_clock, + rtems_cpu_configuration_get_clock_speed): Remove. + +2005-02-18 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/new-exceptions/cpu.h, rtems/old-exceptions/cpu.h + (rtems_cpu_table): Sync defines between {old|new}-exceptions. + +2005-02-18 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/new-exceptions/cpu.h (Context_Control, + Context_Control_fp, CPU_Interrupt_frame): Remove. + * rtems/old-exceptions/cpu.h (Context_Control, + Context_Control_fp, CPU_Interrupt_frame): Remove. + * rtems/score/cpu.h (Context_Control, + Context_Control_fp, CPU_Interrupt_frame): Add. + +2005-02-16 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/new-exceptions/cpu.h (CPU_STACK_MINIMUM_SIZE, + CPU_ALIGNMENT, CPU_HEAP_ALIGNMENT, + CPU_PARTITION_ALIGNMENT, CPU_STACK_ALIGNMENT): Remove. + * rtems/old-exceptions/cpu.h (CPU_STACK_MINIMUM_SIZE, + CPU_ALIGNMENT, CPU_HEAP_ALIGNMENT, + CPU_PARTITION_ALIGNMENT, CPU_STACK_ALIGNMENT): Remove. + * rtems/score/cpu.h (CPU_STACK_MINIMUM_SIZE, + CPU_ALIGNMENT, CPU_HEAP_ALIGNMENT, + CPU_PARTITION_ALIGNMENT, CPU_STACK_ALIGNMENT): Add. + +2005-02-15 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/new-exceptions/cpu.h: Remove CPU_MINIMUM_STACK_FRAME_SIZE. + +2005-02-15 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/new-exceptions/cpu.h (_CPU_Bitfield_Find_first_bit, + _CPU_Priority_Mask, _CPU_Priority_bits_index): Remove. + * rtems/old-exceptions/cpu.h (_CPU_Bitfield_Find_first_bit, + _CPU_Priority_Mask, _CPU_Priority_bits_index): Remove. + * rtems/score/cpu.h (_CPU_Bitfield_Find_first_bit, + _CPU_Priority_Mask, _CPU_Priority_bits_index): New. + +2005-02-15 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/new-exceptions/cpu.h (_CPU_msrs): Remove (Unused). + * rtems/old-exceptions/cpu.h (_CPU_msrs): Remove (Unused). + +2005-02-15 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/new-exceptions/cpu.h (_CPU_ISR_install_vector, + _CPU_Initialize, _CPU_Install_interrupt_stack, _CPU_Context_switch, + _CPU_Context_restore, _CPU_Context_save_fp, _CPU_Context_restore_fp, + _CPU_Fatal_error): Remove. + * rtems/old-exceptions/cpu.h (_CPU_ISR_install_vector, + _CPU_Initialize, _CPU_Install_interrupt_stack, _CPU_Context_switch, + _CPU_Context_restore, _CPU_Context_save_fp, _CPU_Context_restore_fp, + _CPU_Fatal_error): Remove. + * rtems/score/cpu.h (_CPU_ISR_install_vector, + _CPU_Initialize, _CPU_Install_interrupt_stack, _CPU_Context_switch, + _CPU_Context_restore, _CPU_Context_save_fp, _CPU_Context_restore_fp, + _CPU_Fatal_error): New. + +2005-02-15 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/old-exceptions/cpu.h (_CPU_Context_Initialize, + _CPU_Context_Restart_self, _CPU_Context_Fp_start, + _CPU_Context_Initialize_fp): Remove. + * rtems/new-exceptions/cpu.h (_CPU_Context_Initialize, + _CPU_Context_Restart_self, _CPU_Context_Fp_start, + _CPU_Context_Initialize_fp): Remove. + * rtems/score/cpu.h (_CPU_Context_Initialize, + _CPU_Context_Restart_self, _CPU_Context_Fp_start, + _CPU_Context_Initialize_fp): New. + +2005-02-15 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/old-exceptions/cpu.h (PPC_Get_timebase_register): Remove. + * rtems/powerpc/registers.h (PPC_Get_timebase_register, + PPC_Set_timebase_register): Remove. + * rtems/score/cpu.h (PPC_Get_timebase_register, + PPC_Set_timebase_register): New. + +2005-02-15 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/powerpc/registers.h (PPC_Set_decrementer, + PPC_Get_decrementer): Remove. + * rtems/old-exceptions/cpu.h (PPC_Set_decrementer): Remove. + * rtems/score/cpu.h (PPC_Set_decrementer, PPC_Get_decrementer): New. + +2005-02-15 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/old-exceptions/cpu.h (CPU_Get_timebase_low, rtems_bsp_delay, + rtems_bsp_delay_in_bus_cycles): Remove. + * rtems/powerpc/registers.h (CPU_Get_timebase_low, rtems_bsp_delay, + rtems_bsp_delay_in_bus_cycles): Remove. + * rtems/score/cpu.h (CPU_Get_timebase_low, rtems_bsp_delay, + rtems_bsp_delay_in_bus_cycles): New. + +2005-02-15 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/new-exceptions/cpu.h + (rtems_cpu_configuration_get_clicks_per_usec, + rtems_cpu_configuration_get_exceptions_in_ram): Remove. + * rtems/old-exceptions/cpu.h + (rtems_cpu_configuration_get_clicks_per_usec, + rtems_cpu_configuration_get_exceptions_in_ram): Remove. + * rtems/score/cpu.h + (rtems_cpu_configuration_get_clicks_per_usec, + rtems_cpu_configuration_get_exceptions_in_ram): New. + +2005-02-15 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/new-exceptions/cpu.h (CPU_swap_u32, CPU_swap_u16): Remove. + * rtems/old-exceptions/cpu.h (CPU_swap_u32, CPU_swap_u16): Remove. + * rtems/score/cpu.h (CPU_swap_u32, CPU_swap_u16): New. + +2005-02-15 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/old-exceptions/cpu.h: Add _CPU_MSG_GET + (old/new exception processing ABI compatibility). + * rtems/powerpc/registers.h: Use C99 fixed size types. + +2005-02-15 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/powerpc.h: Add __ALTIVEC__ support. + +2005-02-15 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/powerpc.h: Merge ppc603 and ppc603e + PPC_IRQ_*/PPC_TLB_* defines. + +2005-02-14 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/powerpc.h (mpc8260): PPC_ALIGNMENT 8. + +2005-02-14 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/powerpc.h: Remove PPC_HAS_RFCI (Unused). + +2005-02-13 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/powerpc.h: Remove PPC_HAS_EXCEPTION_PREFIX (Unused). + +2005-02-13 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/powerpc.h: Remove PPC_CACHE_ALIGN_POWER (Unused). + +2005-02-13 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/powerpc.h: Remove PPC_LOW_POWER_MODE* (Unused). + +2005-02-13 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/powerpc.h: Remove PPC_HAS_EVPR (Unused). + +2005-02-13 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/powerpc.h: Remove PPC_USE_MULTIPLE (Unused). + +2005-02-13 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/powerpc.h: Remove PPC_D_CACHE, PPC_I_CACHE defines. + +2005-02-13 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/powerpc.h: Remove PPC_MSR_* defines. + +2005-02-13 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/old-exceptions/cpu.h: Add _PPC_MSR_DISABLE_MASK. + Use _PPC_MSR_DISABLE_MASK instead of PPC_MSR_DISABLE_MASK to set up + _disable_mask. + +2005-02-12 Ralf Corsepius <ralf.corsepius@rtems.org> + + * cpu.c: New (Stub file for consistency with other ports). + * Makefile.am: Reflect changes above. + +2005-02-10 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/asm.h, rtems/old-exceptions/cpu.h, rtems/score/powerpc.h: + Remove PPC_ABI_POWEROPEN. + +2005-02-10 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/powerpc.h: Remove hard-coded PPC_HAS_FPU. + Tie PPC_HAS_FPU to _SOFT_FLOAT. + +2005-02-09 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/old-exceptions/cpu.h, rtems/score/powerpc.h: + Remove PPC_ABI_GCC27. + +2005-02-09 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/asm.h, rtems/score/powerpc.h: Remove XCOFF support. + +2005-02-08 Ralf Corsepius <ralf.corsepius@rtems.org> + + * Makefile.am: Split out preinstallation rules. + * preinstall.am: New (Split out from Makefile.am). + +2005-02-04 Ralf Corsepius <ralf.corsepius@rtems.org> + + PR 754/rtems + * rtems/asm.h: New (relocated from .). + * asm.h: Remove (moved to rtems/asm.h). + * Makefile.am: Reflect changes above. + +2004-01-28 Ralf Corsepius <ralf.corsepiu@rtems.org> + + * rtems/new-exceptions/cpu.h, rtems/old-exceptions/cpu.h, + rtems/powerpc/registers.h: New header guards. + +2004-01-28 Ralf Corsepius <ralf.corsepiu@rtems.org> + + * asm.h, rtems/score/cpu.h, rtems/score/powerpc.h, + rtems/score/ppc.h, rtems/score/types.h: New header guards. + +2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: Remove signed8, signed16, signed32, + unsigned8, unsigned16, unsigned32. + +2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/new-exceptions/cpu.h: *_swap_u32( uint32_t ). + * rtems/old-exceptions/cpu.h: *_swap_u32( uint32_t ). + +2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: #include <rtems/stdint.h>. + +2004-11-22 Joel Sherrill <joel@OARcorp.com> + + * rtems/old-exceptions/cpu.h: Make compile in assembly. + +2004-11-21 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: Use __rtems_score_types_h as preprocessor + guard. + +2004-11-21 Ralf Corsepius <ralf.corsepius@rtems.org> + + * asm.h: Add doxygen preamble. + +2004-10-02 Ralf Corsepius <ralf_corsepius@rtems.org> + + * rtems/score/cpu.h: Add doxygen preamble. + * rtems/score/powerpc.h: Add doxygen preamble. + * rtems/score/ppc.h: Add doxygen preamble. + * rtems/score/types.h: Add doxygen preamble. + +2004-10-20 Eric Norum <norume@aps.anl.gov> + + Add Kate Feng's MVME5500 BSP + * rtems/powerpc/registers.h, rtems/score/powerpc.h + +2004-09-29 Joel Sherrill <joel@OARcorp.com> + + * rtems/new-exceptions/cpu.h, rtems/old-exceptions/cpu.h: i960 + obsoleted and all references removed. + +2004-04-13 Ralf Corsepius <ralf_corsepius@rtems.org> + + * asm.h: Include rtems/score/powerpc.h instead of + rtems/score/ppc.h. + +2004-04-13 Ralf Corsepius <ralf_corsepius@rtems.org> + + * rtems/score/powerpc.h: New (Copied and renamed from rtems/score/ppc.h) + for consistency with other ports. + * rtems/score/ppc.h: Deprecation wrapper to rtems/score/powerpc.h. + * Makefile.am: Reflect changes above. + * rtems/score/cpu.h: Include rtems/score/powerpc.h instead of + rtems/score/ppc.h. + +2004-04-12 David Querbach <querbach@realtime.bc.ca> + + * asm.h, rtems/new-exceptions/cpu.h, rtems/score/ppc.h: addition of + MPC555 support as part of the addition of the SS555 BSP. + +2004-04-06 Ralf Corsepius <ralf_corsepius@rtems.org> + + * configure.ac: Remove (Merged into $(top_srcdir)/configure.ac). + * Makefile.am: Don't include multilib.am. + Reflect merging configure.ac into $(top_srcdir)/configure.ac. + +2004-04-01 Ralf Corsepius <ralf_corsepius@rtems.org> + + * Makefile.am: Install asm.h to $(includedir)/rtems. + +2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> + + * rtems/new-exceptions/cpu.h, rtems/old-exceptions/cpu.h, + rtems/powerpc/registers.h: Convert to using c99 fixed size types. + +2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org> + + * configure.ac: RTEMS_TOP([../../../..]). + +2004-01-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Move RTEMS_TOP one subdir down. + +2004-01-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Add PREINSTALL_DIRS. + +2004-01-14 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Re-add dirstamps to PREINSTALL_FILES. + Add PREINSTALL_FILES to CLEANFILES. + +2004-01-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Requires automake >= 1.8.1. + +2004-01-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Include compile.am, again. + +2004-01-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Convert to using automake compilation rules. + +2003-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Use mkdir_p. Remove dirs from PREINSTALL_FILES. + +2003-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Require automake >= 1.8, autoconf >= 2.59. + +2003-11-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Add $(dirstamp) to preinstallation rules. + +2003-11-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Remove all LIB-related rules. + +2003-11-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Don't use gmake rules for preinstallation. + +2003-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Remove RTEMS_CANONICAL_HOST. + +2003-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Remove RTEMS_CHECK_CPU. + +2003-09-26 Joel Sherrill <joel@OARcorp.com> + + * rtems/new-exceptions/cpu.h, rtems/old-exceptions/cpu.h: Obsoleting HP + PA-RISC port and removing all references. + +2003-09-04 Joel Sherrill <joel@OARcorp.com> + + * rtems/new-exceptions/cpu.h, rtems/old-exceptions/cpu.h, + rtems/powerpc/registers.h, rtems/score/ppc.h, rtems/score/types.h: + URL for license changed. + +2003-08-21 Till Straumann <strauman@slac.stanford.edu> + + PR 457/bsps + * rtems/powerpc/registers.h: Add a few definitions for the PowerPC + thermal assistance unit. + +2003-08-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Use rtems-bugs@rtems.com as bug report email address. + +2003-07-18 Till Straumann <strauman@slac.stanford.edu> + + PR 288/rtems + * rtems/new-exceptions/cpu.h: _ISR_Nest_level is now properly + maintained and does not reside in SPRG0. + +2003-03-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Remove AC_CONFIG_AUX_DIR. + +2003-02-20 Till Straumann <strauman@slac.stanford.edu> + + PR 349/bsps + * rtems/powerpc/registers.h: Add definitions for HID1 and DABR SPRs. + +2002-12-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Require autoconf-2.57 + automake-1.7.2. + * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS. + +2002-11-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Fix package name. + +2002-11-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * rtems/new-exceptions/cpu.h: Remove sections on + CPU_INLINE_ENABLE_DISPATCH and CPU_UNROLL_ENQUEUE_PRIORITY. + * rtems/old-exceptions/cpu.h: Remove sections on + CPU_INLINE_ENABLE_DISPATCH and CPU_UNROLL_ENQUEUE_PRIORITY. + * rtems/score/cpu.h: Insert sections on + CPU_INLINE_ENABLE_DISPATCH and CPU_UNROLL_ENQUEUE_PRIORITY. + +2002-10-31 Joel Sherrill <joel@OARcorp.com> + + * rtems/new-exceptions/cpu.h: Removed warnings. + + +2002-10-31 Joel Sherrill <joel@OARcorp.com> + + * rtems/new-exceptions/cpu.h: Removed warnings. + +2002-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE. + +2002-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * .cvsignore: Reformat. + Add autom4te*cache. + Remove autom4te.cache. + +2002-07-26 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Build libscorecpu.a instead of rtems-cpu.rel. + +2002-07-22 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Use .$(OBJEXT) instead of .o. + +2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: RTEMS_TOP(../../../..). + +2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Remove RTEMS_PROJECT_ROOT. + +2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Add RTEMS_PROG_CCAS + +2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). + Add AC_PROG_RANLIB. + +2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. + Use ../../../aclocal. + +2002-05-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * rtems/score/ppc.h: Remove PPC_DEBUG_MODEL. + +2001-05-14 Till Straumann <strauman@slac.stanford.edu> + + * rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add + support for the MPC74000 (AKA G4); there is no AltiVec support yet, + however. +2002-04-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * rtems/score/ppc.h: Remove rtems_multilib. + Add mpc555 (Based on comments from Sergei Organov <osv@javad.ru>). + * rtems/old-exceptions/cpu.h: Remove _CPU_Data_Cache_Block_Flush. + Remove _CPU_Data_Cache_Block_Invalidate. + +2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * asm.h: Include cpuopts.h instead of targopts.h. + * rtems/new-exceptions/cpu.h: Relocated from + libbsp/powerpc/support/new_exception_processing/rtems/score/cpu.h + * rtems/old-exceptions/cpu.h: Relocated from + c/src/lib/libbsp/powerpc/support/old_exception_processing/rtems/score/cpu.h + * rtems/powerpc/registers.h: Relocated and renamed from + libcpu/powerpc/shared/include/cpu.h. + * rtems/score/cpu.h: New. + * Makefile.am: Reflect changes above. + +2001-04-03 Joel Sherrill <joel@OARcorp.com> + + * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. + * rtems/score/ppctypes.h: Removed. + * rtems/score/types.h: New file via CVS magic. + * Makefile.am, rtems/score/cpu.h: Account for name change. + +2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: + AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). + AM_INIT_AUTOMAKE([no-define foreign 1.6]). + * Makefile.am: Remove AUTOMAKE_OPTIONS. + +2002-01-28 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Reflect changes from 2002-01-23. + +2002-01-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * rtems/Makefile.am: Removed. + * rtems/score/Makefile.am: Removed. + * configure.ac: Reflect changes above. + AC_CONFIG_SRCDIR(asm.h). + +2002-01-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * rtems/Makefile.am: New. + * rtems/.cvsignore: New. + * rtems/score/Makefile.am: New. + * rtems/score/.cvsignore: New. + * rtems/score/ppc.h: Relocated from shared/. + * rtems/score/ppctypes.h: Relocated from shared/. + * asm.h: Relocated from shared/. + * shared/Makefile.am: Removed. + * shared/asm.h: Removed. + * shared/ppc.h: Removed. + * shared/ppctypes.h: Removed. + * shared/.cvsignore: Removed. + * Makefile.am: Reflect changes above. + * configure.ac: Reflect changes above. + +2001-11-28 Joel Sherrill <joel@OARcorp.com>, + + This was tracked as PR91. + * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which + is used to specify if the port uses the standard macro for this (FALSE). + A TRUE setting indicates the port provides its own implementation. + +2001-11-14 Joel Sherrill <joel@OARcorp.com> + + * shared/ppc.h: The mpc8260 uses the new exception processing model + and thus does not need to define PPC_USE_SPRG. + +2001-11-14 Andrew Dachs <A.Dachs@SSTL.co.uk> + + * shared/ppc.h: mpc8260 has double FPU not single FPU. + +2001-11-08 Dennis Ehlin (ECS) <Dennis.Ehlin@ecs.ericsson.se> + + This modification is part of the submitted modifications necessary to + support the IBM PPC405 family. This submission was reviewed by + Thomas Doerfler <Thomas.Doerfler@imd-systems.de> who ensured it did + not negatively impact the ppc403 BSPs. The submission and tracking + process was captured as PR50. + * shared/asm.h, shared/ppc.h: Added PPC405 support. + +2001-10-22 Andy Dachs <a.dachs@sstl.co.uk> + + * shared/ppc.h: Added mpc8260 support. + +2001-10-12 Joel Sherrill <joel@OARcorp.com> + + * shared/ppctypes.h: Fixed typo. + +2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * .cvsignore: Add autom4te.cache for autoconf > 2.52. + * configure.in: Remove. + * configure.ac: New file, generated from configure.in by autoupdate. + +2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * shared/Makefile.am: Use 'PREINSTALL_FILES ='. + +2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am, rtems/score/Makefile.am: + Apply include_*HEADERS instead of H_FILES. + +2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. + +2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. + +2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. + Switch to GNU canonicalization. + +2000-10-20 Joel Sherrill <joel@OARcorp.com> + + * shared/ppc.h: For multilibs, derive PPC_HAS_FPU from _SOFT_FLOAT. + +2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Include compile.am. + +2000-08-10 Joel Sherrill <joel@OARcorp.com> + + * ChangeLog: New file. diff --git a/cpukit/score/cpu/powerpc/Makefile.am b/cpukit/score/cpu/powerpc/Makefile.am new file mode 100644 index 0000000000..a8b7b61e5b --- /dev/null +++ b/cpukit/score/cpu/powerpc/Makefile.am @@ -0,0 +1,22 @@ +## +## $Id$ +## + +include $(top_srcdir)/automake/compile.am + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = rtems/score/powerpc.h rtems/score/cpu.h \ + rtems/score/types.h + +include_rtems_powerpcdir = $(includedir)/rtems/powerpc +include_rtems_powerpc_HEADERS = rtems/powerpc/registers.h + +noinst_LIBRARIES = libscorecpu.a +libscorecpu_a_SOURCES = cpu.c +libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) + +include $(srcdir)/preinstall.am +include $(top_srcdir)/automake/local.am diff --git a/cpukit/score/cpu/powerpc/cpu.c b/cpukit/score/cpu/powerpc/cpu.c new file mode 100644 index 0000000000..108a7ce45d --- /dev/null +++ b/cpukit/score/cpu/powerpc/cpu.c @@ -0,0 +1,17 @@ +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +/* + * For now, this file is just a stub to work around + * structural deficiencies of the powerpc port. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + diff --git a/cpukit/score/cpu/powerpc/preinstall.am b/cpukit/score/cpu/powerpc/preinstall.am new file mode 100644 index 0000000000..99e3bd0aaf --- /dev/null +++ b/cpukit/score/cpu/powerpc/preinstall.am @@ -0,0 +1,50 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif + +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + +$(PROJECT_INCLUDE)/rtems/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems + @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) + +$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h + +$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score + @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + +$(PROJECT_INCLUDE)/rtems/score/powerpc.h: rtems/score/powerpc.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/powerpc.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/powerpc.h + +$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h + +$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h + +$(PROJECT_INCLUDE)/rtems/powerpc/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/powerpc + @: > $(PROJECT_INCLUDE)/rtems/powerpc/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/powerpc/$(dirstamp) + +$(PROJECT_INCLUDE)/rtems/powerpc/registers.h: rtems/powerpc/registers.h $(PROJECT_INCLUDE)/rtems/powerpc/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/powerpc/registers.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/powerpc/registers.h + diff --git a/cpukit/score/cpu/powerpc/rtems/asm.h b/cpukit/score/cpu/powerpc/rtems/asm.h new file mode 100644 index 0000000000..d54c0607e2 --- /dev/null +++ b/cpukit/score/cpu/powerpc/rtems/asm.h @@ -0,0 +1,271 @@ +/** + * @file rtems/asm.h + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + */ + +/* + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + * + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1995. + * i-cubed ltd. + * + * COPYRIGHT (c) 1994. + * On-Line Applications Research Corporation (OAR). + * + * $Id$ + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include <rtems/score/cpuopts.h> +#include <rtems/score/powerpc.h> + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +#ifndef __FLOAT_REGISTER_PREFIX__ +#define __FLOAT_REGISTER_PREFIX__ __REGISTER_PREFIX__ +#endif + +#ifndef __PROC_LABEL_PREFIX__ +#define __PROC_LABEL_PREFIX__ __USER_LABEL_PREFIX__ +#endif + +#include <rtems/concat.h> + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for procedure labels. */ + +#define PROC(x) CONCAT1 (__PROC_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* Use the right prefix for floating point registers. */ + +#define FREG(x) CONCAT1 (__FLOAT_REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ +#define r0 REG(0) +#define r1 REG(1) +#define r2 REG(2) +#define r3 REG(3) +#define r4 REG(4) +#define r5 REG(5) +#define r6 REG(6) +#define r7 REG(7) +#define r8 REG(8) +#define r9 REG(9) +#define r10 REG(10) +#define r11 REG(11) +#define r12 REG(12) +#define r13 REG(13) +#define r14 REG(14) +#define r15 REG(15) +#define r16 REG(16) +#define r17 REG(17) +#define r18 REG(18) +#define r19 REG(19) +#define r20 REG(20) +#define r21 REG(21) +#define r22 REG(22) +#define r23 REG(23) +#define r24 REG(24) +#define r25 REG(25) +#define r26 REG(26) +#define r27 REG(27) +#define r28 REG(28) +#define r29 REG(29) +#define r30 REG(30) +#define r31 REG(31) +#define f0 FREG(0) +#define f1 FREG(1) +#define f2 FREG(2) +#define f3 FREG(3) +#define f4 FREG(4) +#define f5 FREG(5) +#define f6 FREG(6) +#define f7 FREG(7) +#define f8 FREG(8) +#define f9 FREG(9) +#define f10 FREG(10) +#define f11 FREG(11) +#define f12 FREG(12) +#define f13 FREG(13) +#define f14 FREG(14) +#define f15 FREG(15) +#define f16 FREG(16) +#define f17 FREG(17) +#define f18 FREG(18) +#define f19 FREG(19) +#define f20 FREG(20) +#define f21 FREG(21) +#define f22 FREG(22) +#define f23 FREG(23) +#define f24 FREG(24) +#define f25 FREG(25) +#define f26 FREG(26) +#define f27 FREG(27) +#define f28 FREG(28) +#define f29 FREG(29) +#define f30 FREG(30) +#define f31 FREG(31) + +/* + * Some special purpose registers (SPRs). + */ +#define srr0 0x01a +#define srr1 0x01b +#define srr2 0x3de /* IBM 400 series only */ +#define srr3 0x3df /* IBM 400 series only */ +#define csrr0 58 /* Book E */ +#define csrr1 59 /* Book E */ +#define mcsrr0 570 /* e500 */ +#define mcsrr1 571 /* e500 */ +#define dsrr0 574 /* e200 */ +#define dsrr1 575 /* e200 */ + +#define sprg0 0x110 +#define sprg1 0x111 +#define sprg2 0x112 +#define sprg3 0x113 +#define sprg4 276 +#define sprg5 277 +#define sprg6 278 +#define sprg7 279 + +#define usprg0 256 + +#define dar 0x013 /* Data Address Register */ +#define dec 0x016 /* Decrementer Register */ + +#if defined(ppc403) || defined(ppc405) +/* the following SPR/DCR registers exist only in IBM 400 series */ +#define dear 0x3d5 +#define evpr 0x3d6 /* SPR: exception vector prefix register */ +#define iccr 0x3fb /* SPR: instruction cache control reg. */ +#define dccr 0x3fa /* SPR: data cache control reg. */ + +#if defined (ppc403) +#define exisr 0x040 /* DCR: external interrupt status register */ +#define exier 0x042 /* DCR: external interrupt enable register */ +#endif /* ppc403 */ +#if defined(ppc405) +#define exisr 0x0C0 /* DCR: external interrupt status register */ +#define exier 0x0C2 /* DCR: external interrupt enable register */ +#endif /* ppc405 */ + +#define br0 0x080 /* DCR: memory bank register 0 */ +#define br1 0x081 /* DCR: memory bank register 1 */ +#define br2 0x082 /* DCR: memory bank register 2 */ +#define br3 0x083 /* DCR: memory bank register 3 */ +#define br4 0x084 /* DCR: memory bank register 4 */ +#define br5 0x085 /* DCR: memory bank register 5 */ +#define br6 0x086 /* DCR: memory bank register 6 */ +#define br7 0x087 /* DCR: memory bank register 7 */ +/* end of IBM400 series register definitions */ + +#elif defined(mpc555) +/* The following registers are for the MPC5xx */ +#define eie 0x050 /* External Interrupt Enable Register */ +#define eid 0x051 /* External Interrupt Disable Register */ +#define nri 0x052 /* Non-Recoverable Interrupt Register */ + +#elif defined(mpc860) || defined(mpc821) +/* The following registers are for the MPC8x0 */ +#define der 0x095 /* Debug Enable Register */ +#define ictrl 0x09E /* Instruction Support Control Register */ +#define immr 0x27E /* Internal Memory Map Register */ +/* end of MPC8x0 registers */ +#endif + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC_VAR(sym) .globl SYM (sym) +#define EXTERN_VAR(sym) .extern SYM (sym) +#define PUBLIC_PROC(sym) .globl PROC (sym) +#define EXTERN_PROC(sym) .extern PROC (sym) + +/* Other potentially assembler specific operations */ +#if PPC_ASM == PPC_ASM_ELF +#define ALIGN(n,p) .align p +#define DESCRIPTOR(x) \ + .section .descriptors,"aw"; \ + PUBLIC_VAR (x); \ +SYM (x):; \ + .long PROC (x); \ + .long s.got; \ + .long 0 + +#define EXT_SYM_REF(x) .long x +#define EXT_PROC_REF(x) .long x + +/* + * Define macros to handle section beginning and ends. + */ + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA .data +#define END_DATA +#define BEGIN_BSS .bss +#define END_BSS +#define END + +#else +#error "PPC_ASM_TYPE is not properly defined" +#endif +#ifndef PPC_ASM +#error "PPC_ASM_TYPE is not properly defined" +#endif + + +#endif diff --git a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h new file mode 100644 index 0000000000..fa193472dd --- /dev/null +++ b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h @@ -0,0 +1,541 @@ +/* + * This file contains some powerpc MSR and registers access definitions. + * + * COPYRIGHT (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk> + * Surrey Satellite Technology Limited + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _RTEMS_POWERPC_REGISTERS_H +#define _RTEMS_POWERPC_REGISTERS_H + +/* Bit encodings for Machine State Register (MSR) */ +#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ +#define MSR_VE (1<<25) /* Alti-Vec enable (7400+) */ +#define MSR_SPE (1<<25) /* SPE enable (e500) */ +#define MSR_POW (1<<18) /* Enable Power Management */ +#define MSR_WE (1<<18) /* Wait state enable (e500) */ +#define MSR_TGPR (1<<17) /* TLB Update registers in use */ +#define MSR_CE (1<<17) /* BookE critical interrupt */ +#define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */ +#define MSR_EE (1<<15) /* External Interrupt enable */ +#define MSR_PR (1<<14) /* Supervisor/User privilege */ +#define MSR_FP (1<<13) /* Floating Point enable */ +#define MSR_ME (1<<12) /* Machine Check enable */ +#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ +#define MSR_SE (1<<10) /* Single Step */ +#define MSR_UBLE (1<<10) /* User-mode BTB lock enable (e500) */ +#define MSR_BE (1<<9) /* Branch Trace */ +#define MSR_DE (1<<9) /* BookE debug exception */ +#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ +#define MSR_E300_CE (1<<7) /* e300 critical interrupt */ +#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ +#define MSR_IR (1<<5) /* Instruction MMU enable */ +#define MSR_DR (1<<4) /* Data MMU enable */ +#define MSR_IS (1<<5) /* Instruction address space */ +#define MSR_DS (1<<4) /* Data address space */ +#define MSR_PMM (1<<2) /* Performance monitor mark */ +#define MSR_RI (1<<1) /* Recoverable Exception */ +#define MSR_LE (1<<0) /* Little-Endian enable */ + +/* Bit encodings for Hardware Implementation Register (HID0) + on PowerPC 603, 604, etc. processors (not 601). */ + +/* WARNING: HID0/HID1 are *truely* implementation dependent! + * you *cannot* rely on the same bits to be present, + * at the same place or even in the same register + * on different CPU familys. + * E.g., EMCP isHID0_DOZE is HID0_HI_BAT_EN on the + * on the 7450s. IFFT is XBSEN on 7450 and so on... + */ +#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ +#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ +#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ +#define HID0_SBCLK (1<<27) +#define HID0_TBEN (1<<26) /* 7455:this bit must be set + * and TBEN signal must be asserted + * to enable the time base and + * decrementer. + */ +#define HID0_EICE (1<<26) +#define HID0_ECLK (1<<25) +#define HID0_PAR (1<<24) +#define HID0_DOZE (1<<23) +/* this HI_BAT_EN only on 7445, 7447, 7448, 7455 & 7457 !! */ +#define HID0_7455_HIGH_BAT_EN (1<<23) + +#define HID0_NAP (1<<22) +#define HID0_SLEEP (1<<21) +#define HID0_DPM (1<<20) +#define HID0_ICE (1<<15) /* Instruction Cache Enable */ +#define HID0_DCE (1<<14) /* Data Cache Enable */ +#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ +#define HID0_DLOCK (1<<12) /* Data Cache Lock */ +#define HID0_ICFI (1<<11) /* Instruction Cache Flash Invalidate */ +#define HID0_DCI (1<<10) /* Data Cache Invalidate */ +/* this bit is XSBSEN (xtended block size enable) on 7447, 7448, 7455 and 7457 only */ +#define HID0_7455_XBSEN (1<<8) +#define HID0_SIED (1<<7) /* Serial Instruction Execution [Disable] */ +#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache [Enable] */ +/* S.K. Feng 10/03, added for MPC7455 */ +#define HID0_LRSTK (1<<4) /* Link register stack enable (7455) */ +#define HID0_FOLD (1<<3) /* Branch folding enable (7455) */ + +#define HID0_BHTE (1<<2) /* Branch History Table Enable */ +#define HID0_BTCD (1<<1) /* Branch target cache disable */ + +/* fpscr settings */ +#define FPSCR_FX (1<<31) +#define FPSCR_FEX (1<<30) + +#define _MACH_prep 1 +#define _MACH_Pmac 2 /* pmac or pmac clone (non-chrp) */ +#define _MACH_chrp 4 /* chrp machine */ +#define _MACH_mbx 8 /* Motorola MBX board */ +#define _MACH_apus 16 /* amiga with phase5 powerup */ +#define _MACH_fads 32 /* Motorola FADS board */ + +/* see residual.h for these */ +#define _PREP_Motorola 0x01 /* motorola prep */ +#define _PREP_Firm 0x02 /* firmworks prep */ +#define _PREP_IBM 0x00 /* ibm prep */ +#define _PREP_Bull 0x03 /* bull prep */ + +/* these are arbitrary */ +#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ +#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ + +#define _GLOBAL(n)\ + .globl n;\ +n: + +#define TBRU 269 /* Time base Upper/Lower (Reading) */ +#define TBRL 268 +#define TBWU 285 /* Time base Upper/Lower (Writing) */ +#define TBWL 284 +#define XER 1 +#define LR 8 +#define CTR 9 +#define HID0 1008 /* Hardware Implementation 0 */ +#define HID1 1009 /* Hardware Implementation 1 */ +#define HID2 1011 /* Hardware Implementation 2 */ +#define DABR 1013 /* Data Access Breakpoint */ +#define PVR 287 /* Processor Version */ +#define IBAT0U 528 /* Instruction BAT #0 Upper/Lower */ +#define IBAT0L 529 +#define IBAT1U 530 /* Instruction BAT #1 Upper/Lower */ +#define IBAT1L 531 +#define IBAT2U 532 /* Instruction BAT #2 Upper/Lower */ +#define IBAT2L 533 +#define IBAT3U 534 /* Instruction BAT #3 Upper/Lower */ +#define IBAT3L 535 + +/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */ +#define IBAT4U 560 /* Instruction BAT #4 Upper/Lower */ +#define IBAT4L 561 +#define IBAT5U 562 /* Instruction BAT #5 Upper/Lower */ +#define IBAT5L 563 +#define IBAT6U 564 /* Instruction BAT #6 Upper/Lower */ +#define IBAT6L 565 +#define IBAT7U 566 /* Instruction BAT #7 Upper/Lower */ +#define IBAT7L 567 + +#define DBAT0U 536 /* Data BAT #0 Upper/Lower */ +#define DBAT0L 537 +#define DBAT1U 538 /* Data BAT #1 Upper/Lower */ +#define DBAT1L 539 +#define DBAT2U 540 /* Data BAT #2 Upper/Lower */ +#define DBAT2L 541 +#define DBAT3U 542 /* Data BAT #3 Upper/Lower */ +#define DBAT3L 543 + +/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */ +#define DBAT4U 568 /* Instruction BAT #4 Upper/Lower */ +#define DBAT4L 569 +#define DBAT5U 570 /* Instruction BAT #5 Upper/Lower */ +#define DBAT5L 571 +#define DBAT6U 572 /* Instruction BAT #6 Upper/Lower */ +#define DBAT6L 573 +#define DBAT7U 574 /* Instruction BAT #7 Upper/Lower */ +#define DBAT7L 575 + +#define DMISS 976 /* TLB Lookup/Refresh registers */ +#define DCMP 977 +#define HASH1 978 +#define HASH2 979 +#define IMISS 980 +#define ICMP 981 +#define RPA 982 +#define SDR1 25 /* MMU hash base register */ +#define DAR 19 /* Data Address Register */ +#define DEAR_BOOKE 61 +#define DEAR_405 981 +#define SPR0 272 /* Supervisor Private Registers */ +#define SPRG0 272 +#define SPR1 273 +#define SPRG1 273 +#define SPR2 274 +#define SPRG2 274 +#define SPR3 275 +#define SPRG3 275 +#define SPRG4 276 +#define SPRG5 277 +#define SPRG6 278 +#define SPRG7 279 +#define USPRG0 256 +#define DSISR 18 +#define SRR0 26 /* Saved Registers (exception) */ +#define SRR1 27 +#define IABR 1010 /* Instruction Address Breakpoint */ +#define DEC 22 /* Decrementer */ +#define EAR 282 /* External Address Register */ + +#define MSSCR0 1014 /* Memory Subsystem Control Register */ + +#define L2CR 1017 /* PPC 750 and 74xx L2 control register */ + +#define L2CR_L2E (1<<31) /* enable */ +#define L2CR_L2I (1<<21) /* global invalidate */ + +/* watch out L2IO and L2DO are different between 745x and 7400/7410 */ +/* Oddly, the following L2CR bit defintions in 745x + * is different from that of 7400 and 7410. + * Though not used in 7400 and 7410, it is appeded with _745x just + * to be clarified. + */ +#define L2CR_L2IO_745x 0x100000 /* (1<<20) L2 Instruction-Only */ +#define L2CR_L2DO_745x 0x10000 /* (1<<16) L2 Data-Only */ +#define L2CR_LOCK_745x (L2CR_L2IO_745x|L2CR_L2DO_745x) +#define L2CR_L3OH0 0x00080000 /* 12:L3 output hold 0 */ + +#define L3CR 1018 /* PPC 7450/7455 L3 control register */ +#define L3CR_L3IO_745x 0x400000 /* (1<<22) L3 Instruction-Only */ +#define L3CR_L3DO_745x 0x40 /* (1<<6) L3 Data-Only */ + +#define L3CR_LOCK_745x (L3CR_L3IO_745x|L3CR_L3DO_745x) + +#define L3CR_RESERVED 0x0438003a /* Reserved bits in L3CR */ +#define L3CR_L3E 0x80000000 /* 0: L3 enable */ +#define L3CR_L3PE 0x40000000 /* 1: L3 data parity checking enable */ +#define L3CR_L3APE 0x20000000 /* 2: L3 address parity checking enable */ +#define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ +#define L3SIZ_1M 0x00000000 +#define L3SIZ_2M 0x10000000 +#define L3CR_L3CLKEN 0x08000000 /* 4: Enables the L3_CLK[0:1] signals */ +#define L3CR_L3CLK 0x03800000 /* 6-8: L3 clock ratio */ +#define L3CLK_60 0x00000000 /* core clock / 6 */ +#define L3CLK_20 0x01000000 /* / 2 */ +#define L3CLK_25 0x01800000 /* / 2.5 */ +#define L3CLK_30 0x02000000 /* / 3 */ +#define L3CLK_35 0x02800000 /* / 3.5 */ +#define L3CLK_40 0x03000000 /* / 4 */ +#define L3CLK_50 0x03800000 /* / 5 */ +#define L3CR_L3IO 0x00400000 /* 9: L3 instruction-only mode */ +#define L3CR_L3SPO 0x00040000 /* 13: L3 sample point override */ +#define L3CR_L3CKSP 0x00030000 /* 14-15: L3 clock sample point */ +#define L3CKSP_2 0x00000000 /* 2 clocks */ +#define L3CKSP_3 0x00010000 /* 3 clocks */ +#define L3CKSP_4 0x00020000 /* 4 clocks */ +#define L3CKSP_5 0x00030000 /* 5 clocks */ +#define L3CR_L3PSP 0x0000e000 /* 16-18: L3 P-clock sample point */ +#define L3PSP_0 0x00000000 /* 0 clocks */ +#define L3PSP_1 0x00002000 /* 1 clocks */ +#define L3PSP_2 0x00004000 /* 2 clocks */ +#define L3PSP_3 0x00006000 /* 3 clocks */ +#define L3PSP_4 0x00008000 /* 4 clocks */ +#define L3PSP_5 0x0000a000 /* 5 clocks */ +#define L3CR_L3REP 0x00001000 /* 19: L3 replacement algorithm (0=default, 1=alternate) */ +#define L3CR_L3HWF 0x00000800 /* 20: L3 hardware flush */ +#define L3CR_L3I 0x00000400 /* 21: L3 global invaregisters.h.orig +lidate */ +#define L3CR_L3RT 0x00000300 /* 22-23: L3 SRAM type */ +#define L3RT_MSUG2_DDR 0x00000000 /* MSUG2 DDR SRAM */ +#define L3RT_PIPELINE_LATE 0x00000100 /* Pipelined (register-register) synchronous late-write SRAM */ +#define L3RT_PB2_SRAM 0x00000300 /* PB2 SRAM */ +#define L3CR_L3NIRCA 0x00000080 /* 24: L3 non-integer ratios clock adjustment for the SRAM */ +#define L3CR_L3DO 0x00000040 /* 25: L3 data-only mode */ +#define L3CR_PMEN 0x00000004 /* 29: Private memory enable */ +#define L3CR_PMSIZ 0x00000004 /* 31: Private memory size (0=1MB, 1=2MB) */ + +#define THRM1 1020 +#define THRM2 1021 +#define THRM3 1022 +#define THRM1_TIN (1<<(31-0)) +#define THRM1_TIV (1<<(31-1)) +#define THRM1_THRES (0x7f<<(31-8)) +#define THRM1_TID (1<<(31-29)) +#define THRM1_TIE (1<<(31-30)) +#define THRM1_V (1<<(31-31)) +#define THRM3_SITV (0x1fff << (31-30)) +#define THRM3_E (1<<(31-31)) + +/* Segment Registers */ +#define PPC_SR0 0 +#define PPC_SR1 1 +#define PPC_SR2 2 +#define PPC_SR3 3 +#define PPC_SR4 4 +#define PPC_SR5 5 +#define PPC_SR6 6 +#define PPC_SR7 7 +#define PPC_SR8 8 +#define PPC_SR9 9 +#define PPC_SR10 10 +#define PPC_SR11 11 +#define PPC_SR12 12 +#define PPC_SR13 13 +#define PPC_SR14 14 +#define PPC_SR15 15 + +#define BOOKE_DECAR 54 + +#define PPC405_TSR 0x3D8 +#define BOOKE_TSR 336 +#define BOOKE_TSR_ENW (1<<31) +#define BOOKE_TSR_WIS (1<<30) +#define BOOKE_TSR_DIS (1<<27) +#define BOOKE_TSR_FIS (1<<26) + +#define PPC405_TCR 0x3DA +#define BOOKE_TCR 340 +#define BOOKE_TCR_WP(x) (((x)&3)<<30) +#define BOOKE_TCR_WP_MASK (3<<30) +#define BOOKE_TCR_WRC(x) (((x)&3)<<28) +#define BOOKE_TCR_WRC_MASK (3<<28) +#define BOOKE_TCR_WIE (1<<27) +#define BOOKE_TCR_DIE (1<<26) +#define BOOKE_TCR_FP(x) (((x)&3)<<24) +#define BOOKE_TCR_FIE (1<<23) +#define BOOKE_TCR_ARE (1<<22) +#define BOOKE_TCR_WPEXT(x) (((x)&0xf)<<17) +#define BOOKE_TCR_WPEXT_MASK (0xf<<17) +#define BOOKE_TCR_FPEXT(x) (((x)&0xf)<<13) +#define BOOKE_TCR_FPEXT_MASK (0xf<<13) + +#define BOOKE_PID 48 +#define BOOKE_PIR 286 + +/* Freescale Book E Implementation Standards (EIS): MMU Control and Status */ + +#define FSL_EIS_MAS0 624 +#define FSL_EIS_MAS0_TLBSEL (1 << (63 - 35)) +#define FSL_EIS_MAS0_ESEL(n) ((0xf & (n)) << (63 - 47)) +#define FSL_EIS_MAS0_ESEL_GET(m) (((m) >> (63 - 47)) & 0xf) +#define FSL_EIS_MAS0_NV (1 << (63 - 63)) + +#define FSL_EIS_MAS1 625 +#define FSL_EIS_MAS1_V (1 << (63 - 32)) +#define FSL_EIS_MAS1_IPROT (1 << (63 - 33)) +#define FSL_EIS_MAS1_TID(n) ((0xff & (n)) << (63 - 47)) +#define FSL_EIS_MAS1_TID_GET(n) (((n) >> (63 - 47)) & 0xfff) +#define FSL_EIS_MAS1_TS (1 << (63 - 51)) +#define FSL_EIS_MAS1_TSIZE(n) ((0xf & (n)) << (63 - 55)) +#define FSL_EIS_MAS1_TSIZE_GET(n) (((n)>>(63 - 55)) & 0xf) + +#define FSL_EIS_MAS2 626 +#define FSL_EIS_MAS2_EPN(n) ((((1 << 21) - 1)&(n)) << (63-51)) +#define FSL_EIS_MAS2_EPN_GET(n) (((n) >> (63 - 51)) & 0xfffff) +#define FSL_EIS_MAS2_EA(n) FSL_EIS_MAS2_EPN((n) >> 12) +#define FSL_EIS_MAS2_EA_GET(n) (FSL_EIS_MAS2_EPN_GET(n) << 12) +#define FSL_EIS_MAS2_X0 (1 << (63 - 57)) +#define FSL_EIS_MAS2_X1 (1 << (63 - 58)) +#define FSL_EIS_MAS2_W (1 << (63 - 59)) +#define FSL_EIS_MAS2_I (1 << (63 - 60)) +#define FSL_EIS_MAS2_M (1 << (63 - 61)) +#define FSL_EIS_MAS2_G (1 << (63 - 62)) +#define FSL_EIS_MAS2_E (1 << (63 - 63)) +#define FSL_EIS_MAS2_ATTR(x) ((x) & 0x7f) +#define FSL_EIS_MAS2_ATTR_GET(x) ((x) & 0x7f) + +#define FSL_EIS_MAS3 627 +#define FSL_EIS_MAS3_RPN(n) ((((1 << 21) - 1) & (n)) << (63-51)) +#define FSL_EIS_MAS3_RPN_GET(n) (((n)>>(63 - 51)) & 0xfffff) +#define FSL_EIS_MAS3_RA(n) FSL_EIS_MAS3_RPN((n) >> 12) +#define FSL_EIS_MAS3_RA_GET(n) (FSL_EIS_MAS3_RPN_GET(n) << 12) +#define FSL_EIS_MAS3_U0 (1 << (63 - 54)) +#define FSL_EIS_MAS3_U1 (1 << (63 - 55)) +#define FSL_EIS_MAS3_U2 (1 << (63 - 56)) +#define FSL_EIS_MAS3_U3 (1 << (63 - 57)) +#define FSL_EIS_MAS3_UX (1 << (63 - 58)) +#define FSL_EIS_MAS3_SX (1 << (63 - 59)) +#define FSL_EIS_MAS3_UW (1 << (63 - 60)) +#define FSL_EIS_MAS3_SW (1 << (63 - 61)) +#define FSL_EIS_MAS3_UR (1 << (63 - 62)) +#define FSL_EIS_MAS3_SR (1 << (63 - 63)) +#define FSL_EIS_MAS3_PERM(n) ((n) & 0x3ff) +#define FSL_EIS_MAS3_PERM_GET(n) ((n) & 0x3ff) + +#define FSL_EIS_MAS4 628 +#define FSL_EIS_MAS4_TLBSELD (1 << (63 - 35)) +#define FSL_EIS_MAS4_TIDSELD(n) ((0x3 & (n)) << (63 - 47)) +#define FSL_EIS_MAS4_TSIZED(n) ((0xf & (n)) << (63 - 55)) +#define FSL_EIS_MAS4_X0D FSL_EIS_MAS2_X0 +#define FSL_EIS_MAS4_X1D FSL_EIS_MAS2_X1 +#define FSL_EIS_MAS4_WD FSL_EIS_MAS2_W +#define FSL_EIS_MAS4_ID FSL_EIS_MAS2_I +#define FSL_EIS_MAS4_MD FSL_EIS_MAS2_M +#define FSL_EIS_MAS4_GD FSL_EIS_MAS2_G +#define FSL_EIS_MAS4_ED FSL_EIS_MAS2_E + +#define FSL_EIS_MAS5 629 + +#define FSL_EIS_MAS6 630 +#define FSL_EIS_MAS6_SPID0(n) ((0xff & (n)) << (63 - 55)) +#define FSL_EIS_MAS6_SAS (1 << (63 - 63)) + +#define FSL_EIS_MAS7 944 + +#define FSL_EIS_MMUCFG 1015 +#define FSL_EIS_MMUCSR0 1012 +#define FSL_EIS_PID0 48 +#define FSL_EIS_PID1 633 +#define FSL_EIS_PID2 634 +#define FSL_EIS_TLB0CFG 688 +#define FSL_EIS_TLB1CFG 689 + +/* Freescale Book E Implementation Standards (EIS): L1 Cache */ + +#define FSL_EIS_L1CFG0 515 +#define FSL_EIS_L1CFG1 516 +#define FSL_EIS_L1CSR0 1010 +#define FSL_EIS_L1CSR1 1011 + +/* Freescale Book E Implementation Standards (EIS): Timer */ + +#define FSL_EIS_ATBL 526 +#define FSL_EIS_ATBU 527 + +/* Freescale Book E Implementation Standards (EIS): Signal Processing Engine (SPE) */ + +#define FSL_EIS_SPEFSCR 512 + +/** + * @brief Default value for the interrupt disable mask. + * + * The interrupt disable mask is stored in the SPRG0 (= special purpose + * register 272). + */ +#define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE + +#ifndef ASM + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define _CPU_MSR_GET( _msr_value ) \ + do { \ + _msr_value = 0; \ + __asm__ volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \ + } while (0) + +#define _CPU_MSR_SET( _msr_value ) \ +{ __asm__ volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } + +static inline void ppc_interrupt_set_disable_mask( uint32_t mask ) +{ + __asm__ volatile ( + "mtspr 272, %0" + : + : "r" (mask) + ); +} + +static inline uint32_t ppc_interrupt_get_disable_mask( void ) +{ + uint32_t mask; + + __asm__ volatile ( + "mfspr %0, 272" + : "=r" (mask) + ); + + return mask; +} + +static inline uint32_t ppc_interrupt_disable( void ) +{ + uint32_t level; + uint32_t mask; + + __asm__ volatile ( + "mfmsr %0;" + "mfspr %1, 272;" + "andc %1, %0, %1;" + "mtmsr %1" + : "=r" (level), "=r" (mask) + ); + + return level; +} + +static inline void ppc_interrupt_enable( uint32_t level ) +{ + __asm__ volatile ( + "mtmsr %0" + : + : "r" (level) + ); +} + +static inline void ppc_interrupt_flash( uint32_t level ) +{ + uint32_t current_level; + + __asm__ volatile ( + "mfmsr %0;" + "mtmsr %1;" + "mtmsr %0" + : "=&r" (current_level) + : "r" (level) + ); +} + +#define _CPU_ISR_Disable( _isr_cookie ) \ + do { \ + _isr_cookie = ppc_interrupt_disable(); \ + } while (0) + +/* + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * _isr_cookie is not modified. + */ + +#define _CPU_ISR_Enable( _isr_cookie ) \ + ppc_interrupt_enable(_isr_cookie) + +/* + * This temporarily restores the interrupt to _isr_cookie before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _isr_cookie is not + * modified. + * + * NOTE: The version being used is not very optimized but it does + * not trip a problem in gcc where the disable mask does not + * get loaded. Check this for future (post 10/97 gcc versions. + */ + +#define _CPU_ISR_Flash( _isr_cookie ) \ + ppc_interrupt_flash(_isr_cookie) + +/* end of ISR handler macros */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* _RTEMS_POWERPC_REGISTERS_H */ diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/rtems/score/cpu.h new file mode 100644 index 0000000000..b076f7e87d --- /dev/null +++ b/cpukit/score/cpu/powerpc/rtems/score/cpu.h @@ -0,0 +1,979 @@ +/** + * @file rtems/score/cpu.h + */ + +/* + * COPYRIGHT (c) 1989-2007. + * On-Line Applications Research Corporation (OAR). + * + * COPYRIGHT (c) 1995 i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>. + * + * Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL). + * + * Copyright (c) 2010 embedded brains GmbH. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#include <rtems/score/types.h> +#include <rtems/score/powerpc.h> +#include <rtems/powerpc/registers.h> + +#ifndef ASM + #include <string.h> /* for memset() */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* conditional compilation parameters */ + +/* + * Should the calls to _Thread_Enable_dispatch be inlined? + * + * If TRUE, then they are inlined. + * If FALSE, then a subroutine call is made. + * + * Basically this is an example of the classic trade-off of size + * versus speed. Inlining the call (TRUE) typically increases the + * size of RTEMS while speeding up the enabling of dispatching. + * [NOTE: In general, the _Thread_Dispatch_disable_level will + * only be 0 or 1 unless you are in an interrupt handler and that + * interrupt handler invokes the executive.] When not inlined + * something calls _Thread_Enable_dispatch which in turns calls + * _Thread_Dispatch. If the enable dispatch is inlined, then + * one subroutine call is avoided entirely.] + */ + +#define CPU_INLINE_ENABLE_DISPATCH FALSE + +/* + * Should the body of the search loops in _Thread_queue_Enqueue_priority + * be unrolled one time? In unrolled each iteration of the loop examines + * two "nodes" on the chain being searched. Otherwise, only one node + * is examined per iteration. + * + * If TRUE, then the loops are unrolled. + * If FALSE, then the loops are not unrolled. + * + * The primary factor in making this decision is the cost of disabling + * and enabling interrupts (_ISR_Flash) versus the cost of rest of the + * body of the loop. On some CPUs, the flash is more expensive than + * one iteration of the loop body. In this case, it might be desirable + * to unroll the loop. It is important to note that on some CPUs, this + * code is the longest interrupt disable period in RTEMS. So it is + * necessary to strike a balance when setting this parameter. + */ + +#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE + +/* + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * 1. BSP provided + * 2. CPU dependent (if provided) + * 3. generic (if no BSP and no CPU dependent) + */ + +#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE + +/* + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + */ + +#define CPU_STACK_GROWS_UP FALSE + +/* + * The following is the variable attribute used to force alignment + * of critical RTEMS structures. On some processors it may make + * sense to have these aligned on tighter boundaries than + * the minimum requirements of the compiler in order to have as + * much of the critical data area as possible in a cache line. + * + * The placement of this macro in the declaration of the variables + * is based on the syntactically requirements of the GNU C + * "__attribute__" extension. For example with GNU C, use + * the following to force a structures to a 32 byte boundary. + * + * __attribute__ ((aligned (32))) + * + * NOTE: Currently only the Priority Bit Map table uses this feature. + * To benefit from using this, the data must be heavily + * used so it will stay in the cache and used frequently enough + * in the executive to justify turning this on. + */ + +#define CPU_STRUCTURE_ALIGNMENT \ + __attribute__ ((aligned (PPC_STRUCTURE_ALIGNMENT))) + +/* + * Define what is required to specify how the network to host conversion + * routines are handled. + */ + +#if defined(__BIG_ENDIAN__) || defined(_BIG_ENDIAN) +#define CPU_BIG_ENDIAN TRUE +#define CPU_LITTLE_ENDIAN FALSE +#else +#define CPU_BIG_ENDIAN FALSE +#define CPU_LITTLE_ENDIAN TRUE +#endif + +/* + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * If there is a FP coprocessor such as the i387 or mc68881, then + * the answer is TRUE. + * + * The macro name "PPC_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + */ + +#if ( PPC_HAS_FPU == 1 ) +#define CPU_HARDWARE_FP TRUE +#define CPU_SOFTWARE_FP FALSE +#else +#define CPU_HARDWARE_FP FALSE +#define CPU_SOFTWARE_FP FALSE +#endif + +/* + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + * + * PowerPC Note: It appears the GCC can implicitly generate FPU + * and Altivec instructions when you least expect them. So make + * all tasks floating point. + */ + +#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP + +/* + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + */ + +#define CPU_IDLE_TASK_IS_FP FALSE + +/* + * Processor defined structures required for cpukit/score. + */ + +/* + * Contexts + * + * Generally there are 2 types of context to save. + * 1. Interrupt registers to save + * 2. Task level registers to save + * + * This means we have the following 3 context items: + * 1. task level context stuff:: Context_Control + * 2. floating point task stuff:: Context_Control_fp + * 3. special interrupt level context :: Context_Control_interrupt + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + */ + +#ifndef ASM + +typedef struct { + uint32_t gpr1; /* Stack pointer for all */ + uint32_t gpr2; /* Reserved SVR4, section ptr EABI + */ + uint32_t gpr13; /* Section ptr SVR4/EABI */ + uint32_t gpr14; /* Non volatile for all */ + uint32_t gpr15; /* Non volatile for all */ + uint32_t gpr16; /* Non volatile for all */ + uint32_t gpr17; /* Non volatile for all */ + uint32_t gpr18; /* Non volatile for all */ + uint32_t gpr19; /* Non volatile for all */ + uint32_t gpr20; /* Non volatile for all */ + uint32_t gpr21; /* Non volatile for all */ + uint32_t gpr22; /* Non volatile for all */ + uint32_t gpr23; /* Non volatile for all */ + uint32_t gpr24; /* Non volatile for all */ + uint32_t gpr25; /* Non volatile for all */ + uint32_t gpr26; /* Non volatile for all */ + uint32_t gpr27; /* Non volatile for all */ + uint32_t gpr28; /* Non volatile for all */ + uint32_t gpr29; /* Non volatile for all */ + uint32_t gpr30; /* Non volatile for all */ + uint32_t gpr31; /* Non volatile for all */ + uint32_t cr; /* PART of the CR is non volatile for all */ + uint32_t pc; /* Program counter/Link register */ + uint32_t msr; /* Initial interrupt level */ +#ifdef __ALTIVEC__ + /* 12 non-volatile vector registers, cache-aligned area for vscr/vrsave + * and padding to ensure cache-alignment. + * Unfortunately, we can't verify the cache line size here + * in the cpukit but altivec support code will produce an + * error if this is ever different from 32 bytes. + * + * Note: it is the BSP/CPU-support's responsibility to + * save/restore volatile vregs across interrupts + * and exceptions. + */ + uint8_t altivec[16*12 + 32 + 32]; +#endif +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->gpr1 + +typedef struct { + /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over + * procedure calls. However, this would mean that the interrupt + * frame had to hold f0-f13, and the fpscr. And as the majority + * of tasks will not have an FP context, we will save the whole + * context here. + */ +#if (PPC_HAS_DOUBLE == 1) + double f[32]; + uint64_t fpscr; +#else + float f[32]; + uint32_t fpscr; +#endif +} Context_Control_fp; + +typedef struct CPU_Interrupt_frame { + uint32_t stacklink; /* Ensure this is a real frame (also reg1 save) */ + uint32_t calleeLr; /* link register used by callees: SVR4/EABI */ + + /* This is what is left out of the primary contexts */ + uint32_t gpr0; + uint32_t gpr2; /* play safe */ + uint32_t gpr3; + uint32_t gpr4; + uint32_t gpr5; + uint32_t gpr6; + uint32_t gpr7; + uint32_t gpr8; + uint32_t gpr9; + uint32_t gpr10; + uint32_t gpr11; + uint32_t gpr12; + uint32_t gpr13; /* Play safe */ + uint32_t gpr28; /* For internal use by the IRQ handler */ + uint32_t gpr29; /* For internal use by the IRQ handler */ + uint32_t gpr30; /* For internal use by the IRQ handler */ + uint32_t gpr31; /* For internal use by the IRQ handler */ + uint32_t cr; /* Bits of this are volatile, so no-one may save */ + uint32_t ctr; + uint32_t xer; + uint32_t lr; + uint32_t pc; + uint32_t msr; + uint32_t pad[3]; +} CPU_Interrupt_frame; + +#endif /* ASM */ + +/* + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + */ + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE + +/* + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + */ + +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/* + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + * + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. + */ + +#define CPU_ALLOCATE_INTERRUPT_STACK FALSE + +/* + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + */ + +#define CPU_ISR_PASSES_FRAME_POINTER 0 + +/* + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + * + * Note, however that compilers may use floating point registers/ + * instructions for optimization or they may save/restore FP registers + * on the stack. You must not use deferred switching in these cases + * and on the PowerPC attempting to do so will raise a "FP unavailable" + * exception. + */ +/* + * ACB Note: This could make debugging tricky.. + */ + +/* conservative setting (FALSE); probably doesn't affect performance too much */ +#define CPU_USE_DEFERRED_FP_SWITCH FALSE + +/* + * Processor defined structures required for cpukit/score. + */ + +#ifndef ASM + +/* + * This variable is optional. It is used on CPUs on which it is difficult + * to generate an "uninitialized" FP context. It is filled in by + * _CPU_Initialize and copied into the task's FP context area during + * _CPU_Context_Initialize. + */ + +/* EXTERN Context_Control_fp _CPU_Null_fp_context; */ + +#endif /* ndef ASM */ + +/* + * This defines the number of levels and the mask used to pick those + * bits out of a thread mode. + */ + +#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ +#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ + +/* + * Nothing prevents the porter from declaring more CPU specific variables. + */ + +#ifndef ASM + +SCORE_EXTERN struct { + uint32_t *Disable_level; + void *Stack; + volatile bool *Switch_necessary; + bool *Signal; + +} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT; + +#endif /* ndef ASM */ + +/* + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + */ + +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +/* + * (Optional) # of bytes for libmisc/stackchk to check + * If not specifed, then it defaults to something reasonable + * for most architectures. + */ + +#define CPU_STACK_CHECK_SIZE (128) + +/* + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + */ + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/* + * This defines the number of entries in the ISR_Vector_table managed + * by RTEMS. + */ + +#define CPU_INTERRUPT_NUMBER_OF_VECTORS (0) +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (UINT32_MAX) + +/* + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable _ISR_Nest_level. Note that + * this is not an option - RTEMS/score _relies_ on _ISR_Nest_level + * being maintained (e.g. watchdog queues). + */ + +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/* + * ISR handler macros + */ + +#define _CPU_Initialize_vectors() + +/* + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in _isr_cookie. + */ + +#ifndef ASM + +static inline uint32_t _CPU_ISR_Get_level( void ) +{ + register unsigned int msr; + _CPU_MSR_GET(msr); + if (msr & MSR_EE) return 0; + else return 1; +} + +static inline void _CPU_ISR_Set_level( uint32_t level ) +{ + register unsigned int msr; + _CPU_MSR_GET(msr); + if (!(level & CPU_MODES_INTERRUPT_MASK)) { + msr |= ppc_interrupt_get_disable_mask(); + } + else { + msr &= ~ppc_interrupt_get_disable_mask(); + } + _CPU_MSR_SET(msr); +} + +void BSP_panic(char *); + +/* Fatal Error manager macros */ + +/* + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + */ + +void _BSP_Fatal_error(unsigned int); + +#endif /* ASM */ + +#define _CPU_Fatal_halt( _error ) \ + _BSP_Fatal_error(_error) + +/* end of Fatal Error manager macros */ + +/* + * SPRG0 was previously used to make sure that the BSP fixed the PR288 bug. + * Now SPRG0 is devoted to the interrupt disable mask. + */ + +#define PPC_BSP_HAS_FIXED_PR288 ppc_this_is_now_the_interrupt_disable_mask + +/* + * Should be large enough to run all RTEMS tests. This ensures + * that a "reasonable" small application should not have any problems. + */ + +#define CPU_STACK_MINIMUM_SIZE (1024*8) + +/* + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + */ + +#define CPU_ALIGNMENT (PPC_ALIGNMENT) + +/* + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, + * then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) + +/* + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict + * enough for the partition, then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) + +/* + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT + * is strict enough for the stack, then this should be set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. + */ + +#define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) + +#ifndef ASM +/* The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to ensure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + */ + +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t swapped; + + __asm__ volatile("rlwimi %0,%1,8,24,31;" + "rlwimi %0,%1,24,16,23;" + "rlwimi %0,%1,8,8,15;" + "rlwimi %0,%1,24,0,7;" : + "=&r" ((swapped)) : "r" ((value))); + + return( swapped ); +} + +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +#endif /* ASM */ + + +#ifndef ASM +/* Context handler macros */ + +/* + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + */ + +void _CPU_Context_Initialize( + Context_Control *the_context, + uint32_t *stack_base, + uint32_t size, + uint32_t new_level, + void *entry_point, + bool is_fp +); + +/* + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. Context_Restore should work most of the time. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + */ + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/* + * The purpose of this macro is to allow the initial pointer into + * a floating point context area (used to save the floating point + * context) to be at an arbitrary place in the floating point + * context area. + * + * This is necessary because some FP units are designed to have + * their context saved as a stack which grows into lower addresses. + * Other FP units can be saved by simply moving registers into offsets + * from the base of the context area. Finally some FP units provide + * a "dump context" instruction which could fill in from high to low + * or low to high based on the whim of the CPU designers. + */ + +#define _CPU_Context_Fp_start( _base, _offset ) \ + ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) + +/* + * This routine initializes the FP context area passed to it to. + * There are a few standard ways in which to initialize the + * floating point context. The code included for this macro assumes + * that this is a CPU in which a "initial" FP context was saved into + * _CPU_Null_fp_context and it simply copies it to the destination + * context passed to it. + * + * Other models include (1) not doing anything, and (2) putting + * a "null FP status word" in the correct place in the FP context. + */ + +#define _CPU_Context_Initialize_fp( _destination ) \ + memset( *(_destination), 0, sizeof( **(_destination) ) ) + +/* end of Context handler macros */ +#endif /* ASM */ + +#ifndef ASM +/* Bitfield handler macros */ + +/* + * This routine sets _output to the bit number of the first bit + * set in _value. _value is of CPU dependent type Priority_bit_map_Control. + * This type may be either 16 or 32 bits wide although only the 16 + * least significant bits will be used. + * + * There are a number of variables in using a "find first bit" type + * instruction. + * + * (1) What happens when run on a value of zero? + * (2) Bits may be numbered from MSB to LSB or vice-versa. + * (3) The numbering may be zero or one based. + * (4) The "find first bit" instruction may search from MSB or LSB. + * + * RTEMS guarantees that (1) will never happen so it is not a concern. + * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and + * _CPU_Priority_Bits_index(). These three form a set of routines + * which must logically operate together. Bits in the _value are + * set and cleared based on masks built by _CPU_Priority_mask(). + * The basic major and minor values calculated by _Priority_Major() + * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() + * to properly range between the values returned by the "find first bit" + * instruction. This makes it possible for _Priority_Get_highest() to + * calculate the major and directly index into the minor table. + * This mapping is necessary to ensure that 0 (a high priority major/minor) + * is the first bit found. + * + * This entire "find first bit" and mapping process depends heavily + * on the manner in which a priority is broken into a major and minor + * components with the major being the 4 MSB of a priority and minor + * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest + * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next + * to the lowest priority. + * + * If your CPU does not have a "find first bit" instruction, then + * there are ways to make do without it. Here are a handful of ways + * to implement this in software: + * + * - a series of 16 bit test instructions + * - a "binary search using if's" + * - _number = 0 + * if _value > 0x00ff + * _value >>=8 + * _number = 8; + * + * if _value > 0x0000f + * _value >=8 + * _number += 4 + * + * _number += bit_set_table[ _value ] + * + * where bit_set_table[ 16 ] has values which indicate the first + * bit set + */ + +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + { \ + __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ + "1" ((_value))); \ + } + +/* end of Bitfield handler macros */ + +/* + * This routine builds the mask which corresponds to the bit fields + * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion + * for that routine. + */ + +#define _CPU_Priority_Mask( _bit_number ) \ + ( 0x80000000 >> (_bit_number) ) + +/* + * This routine translates the bit numbers returned by + * _CPU_Bitfield_Find_first_bit() into something suitable for use as + * a major or minor component of a priority. See the discussion + * for that routine. + */ + +#define _CPU_Priority_bits_index( _priority ) \ + (_priority) + +/* end of Priority handler macros */ +#endif /* ASM */ + +/* functions */ + +#ifndef ASM + +/* + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + */ + +void _CPU_Initialize(void); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + */ + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_Install_interrupt_stack + * + * This routine installs the hardware interrupt stack pointer. + * + * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + */ + +void _CPU_Install_interrupt_stack( void ); + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + */ + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/* + * _CPU_Context_restore + * + * This routine is generallu used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + * + * NOTE: May be unnecessary to reload some registers. + */ + +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; + +/* + * _CPU_Context_save_fp + * + * This routine saves the floating point context passed to it. + */ + +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); + +/* + * _CPU_Context_restore_fp + * + * This routine restores the floating point context passed to it. + */ + +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); + +/* + * _CPU_Initialize_altivec() + * + * Global altivec-related initialization. + */ +void +_CPU_Initialize_altivec(void); + +/* + * _CPU_Context_switch_altivec + * + * This routine switches the altivec contexts passed to it. + */ + +void +_CPU_Context_switch_altivec( + Context_Control *from, + Context_Control *to +); + +/* + * _CPU_Context_restore_altivec + * + * This routine restores the altivec context passed to it. + */ + +void +_CPU_Context_restore_altivec( + Context_Control *ctxt +); + +/* + * _CPU_Context_initialize_altivec + * + * This routine initializes the altivec context passed to it. + */ + +void +_CPU_Context_initialize_altivec( + Context_Control *ctxt +); + +void _CPU_Fatal_error( + uint32_t _error +); + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_CPU_H */ diff --git a/cpukit/score/cpu/powerpc/rtems/score/powerpc.h b/cpukit/score/cpu/powerpc/rtems/score/powerpc.h new file mode 100644 index 0000000000..93ab3b6499 --- /dev/null +++ b/cpukit/score/cpu/powerpc/rtems/score/powerpc.h @@ -0,0 +1,168 @@ +/** + * @file rtems/score/powerpc.h + */ + +/* + * This file contains definitions for the IBM/Motorola PowerPC + * family members. + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * MPC860 support code was added by Jay Monkman <jmonkman@frasca.com> + * MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk> + * Surrey Satellite Technology Limited + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * + * Note: + * This file is included by both C and assembler code ( -DASM ) + * + * $Id$ + */ + + +#ifndef _RTEMS_SCORE_POWERPC_H +#define _RTEMS_SCORE_POWERPC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rtems/score/types.h> + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "PowerPC" + +/* + * This file contains the information required to build + * RTEMS for the PowerPC family. + */ + +/* Generic ppc */ + +#ifdef _SOFT_FLOAT +#define CPU_MODEL_NAME "Generic (no FPU)" +#elif defined(__NO_FPRS__) || defined(__SPE__) +#define CPU_MODEL_NAME "Generic (E500/float-gprs/SPE)" +#else +#define CPU_MODEL_NAME "Generic (classic FPU)" +#endif + +#define PPC_ALIGNMENT 8 +#define PPC_STRUCTURE_ALIGNMENT 32 + +/* + * Application binary interfaces. + * + * PPC_ABI MUST be defined as one of these. + * Only big endian is currently supported. + */ + +/* + * SVR4 ABI + */ +#define PPC_ABI_SVR4 2 +/* + * Embedded ABI + */ +#define PPC_ABI_EABI 3 + +/* + * Default to the EABI used by current GNU tools + */ + +#ifndef PPC_ABI +#define PPC_ABI PPC_ABI_EABI +#endif + +#if (PPC_ABI == PPC_ABI_SVR4) || defined(__ALTIVEC__) +#define PPC_STACK_ALIGNMENT 16 +#elif (PPC_ABI == PPC_ABI_EABI) +#if 1 +/* Till.S: 2008/07/10; AFAIK, the CPU_STACK_ALIGNMENT is only + * used to align the top of the stack. We don't lose much + * if we always align TOS to 16-bytes but we then are always + * OK, even if the user tells the compiler to generate 16-byte + * alignment. + */ +#define PPC_STACK_ALIGNMENT 16 +#else +#define PPC_STACK_ALIGNMENT 8 +#endif +#else +#error "PPC_ABI is not properly defined" +#endif + +/* + * Assume PPC_HAS_FPU to be a synonym for _SOFT_FLOAT. + */ + +#if defined(_SOFT_FLOAT) || defined(__NO_FPRS__) /* e500 has unified integer/FP registers */ +#define PPC_HAS_FPU 0 +#else +#define PPC_HAS_FPU 1 +#endif + +/* + * Unless specified above, If the model has FP support, it is assumed to + * support doubles (8-byte floating point numbers). + * + * If the model does NOT have FP support, then the model does + * NOT have double length FP registers. + */ + +#if (PPC_HAS_FPU) +#define PPC_HAS_DOUBLE 1 +#else +#define PPC_HAS_DOUBLE 0 +#endif + +/* + * Assemblers. + * PPC_ASM MUST be defined as one of these. + * + * PPC_ASM_ELF: ELF assembler. Currently used for all ABIs. + * + * NOTE: Only PPC_ABI_ELF is currently fully supported. + * + * Also NOTE: cpukit doesn't need this but asm.h which is defined + * in cpukit for consistency with other ports does. + */ + +#define PPC_ASM_ELF 0 + +/* + * Default to the assembler format used by the current GNU tools. + */ +#define PPC_ASM PPC_ASM_ELF + + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_POWERPC_H */ diff --git a/cpukit/score/cpu/powerpc/rtems/score/types.h b/cpukit/score/cpu/powerpc/rtems/score/types.h new file mode 100644 index 0000000000..828a363934 --- /dev/null +++ b/cpukit/score/cpu/powerpc/rtems/score/types.h @@ -0,0 +1,59 @@ +/** + * @file rtems/score/types.h + */ + +/* + * This include file contains type definitions pertaining to the PowerPC + * processor family. + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/exec/cpu/no_cpu/no_cputypes.h: + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include <rtems/score/basedefs.h> + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ +typedef uint32_t Priority_bit_map_Control; +typedef void ppc_isr; + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif |