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-rw-r--r--cpukit/score/cpu/powerpc/include/rtems/score/cpu.h98
1 files changed, 53 insertions, 45 deletions
diff --git a/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h
index 996b6f8e60..6f2fe491e9 100644
--- a/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
/**
* @file
*
@@ -27,11 +29,28 @@
*
* Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL).
*
- * Copyright (c) 2010, 2017 embedded brains GmbH.
+ * Copyright (C) 2010, 2020 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
*
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _RTEMS_SCORE_CPU_H
@@ -227,6 +246,13 @@ typedef struct {
uint32_t isr_dispatch_disable;
uint32_t reserved_for_alignment;
#if defined(PPC_MULTILIB_ALTIVEC)
+ #if !defined(__powerpc64__)
+ uint32_t reserved_for_alignment_2[4];
+ #endif
+ uint32_t vrsave;
+ uint32_t reserved_for_alignment_3[2];
+ /* This field must take stvewx/lvewx requirements into account */
+ uint32_t vscr;
uint8_t v20[16];
uint8_t v21[16];
uint8_t v22[16];
@@ -239,7 +265,6 @@ typedef struct {
uint8_t v29[16];
uint8_t v30[16];
uint8_t v31[16];
- uint32_t vrsave;
#elif defined(__ALTIVEC__)
/*
* 12 non-volatile vector registers, cache-aligned area for vscr/vrsave
@@ -354,8 +379,16 @@ static inline ppc_context *ppc_get_context( const Context_Control *context )
#define PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE PPC_CONTEXT_GPR_OFFSET( 32 )
#ifdef PPC_MULTILIB_ALTIVEC
+ #ifdef __powerpc64__
+ #define PPC_CONTEXT_OFFSET_VRSAVE \
+ ( PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8 )
+ #else
+ #define PPC_CONTEXT_OFFSET_VRSAVE \
+ ( PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 24 )
+ #endif
+ #define PPC_CONTEXT_OFFSET_VSCR ( PPC_CONTEXT_OFFSET_VRSAVE + 12 )
#define PPC_CONTEXT_OFFSET_V( v ) \
- ( ( ( v ) - 20 ) * 16 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8)
+ ( ( ( v ) - 20 ) * 16 + PPC_CONTEXT_OFFSET_VRSAVE + 16)
#define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 )
#define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 )
#define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 )
@@ -368,9 +401,8 @@ static inline ppc_context *ppc_get_context( const Context_Control *context )
#define PPC_CONTEXT_OFFSET_V29 PPC_CONTEXT_OFFSET_V( 29 )
#define PPC_CONTEXT_OFFSET_V30 PPC_CONTEXT_OFFSET_V( 30 )
#define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 )
- #define PPC_CONTEXT_OFFSET_VRSAVE PPC_CONTEXT_OFFSET_V( 32 )
#define PPC_CONTEXT_OFFSET_F( f ) \
- ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_VRSAVE + 8 )
+ ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_V( 32 ) )
#else
#define PPC_CONTEXT_OFFSET_F( f ) \
( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8 )
@@ -400,7 +432,7 @@ static inline ppc_context *ppc_get_context( const Context_Control *context )
#if defined(PPC_MULTILIB_FPU)
#define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_F( 32 )
#elif defined(PPC_MULTILIB_ALTIVEC)
- #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_OFFSET_VRSAVE + 4)
+ #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_V( 33 )
#elif defined(__ALTIVEC__)
#define PPC_CONTEXT_VOLATILE_SIZE \
(PPC_CONTEXT_GPR_OFFSET( 32 ) + 8 \
@@ -417,8 +449,8 @@ static inline ppc_context *ppc_get_context( const Context_Control *context )
#endif
#ifndef ASM
-typedef struct {
#if (PPC_HAS_FPU == 1)
+typedef struct {
/* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
* procedure calls. However, this would mean that the interrupt
* frame had to hold f0-f13, and the fpscr. And as the majority
@@ -432,9 +464,8 @@ typedef struct {
float f[32];
uint32_t fpscr;
#endif
-#endif /* (PPC_HAS_FPU == 1) */
} Context_Control_fp;
-
+#endif /* (PPC_HAS_FPU == 1) */
#endif /* ASM */
/*
@@ -530,7 +561,9 @@ typedef struct {
* CPUs with a "floating point save context" instruction.
*/
+#if (PPC_HAS_FPU == 1)
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
+#endif
/*
* (Optional) # of bytes for libmisc/stackchk to check
@@ -576,7 +609,7 @@ typedef struct {
#ifndef ASM
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
return ( level & MSR_EE ) != 0;
}
@@ -613,20 +646,6 @@ void ppc_set_interrupt_level( uint32_t level );
#endif /* ASM */
-#define _CPU_Fatal_halt( _source, _error ) \
- do { \
- ppc_interrupt_disable(); \
- __asm__ volatile ( \
- "mr 3, %0\n" \
- "mr 4, %1\n" \
- "1:\n" \
- "b 1b\n" \
- : \
- : "r" (_source), "r" (_error) \
- : "memory" \
- ); \
- } while ( 0 )
-
/*
* Should be large enough to run all RTEMS tests. This ensures
* that a "reasonable" small application should not have any problems.
@@ -724,14 +743,6 @@ static inline CPU_Counter_ticks _CPU_Counter_read( void )
return value;
}
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
#endif /* ASM */
@@ -914,6 +925,11 @@ void _CPU_Context_switch(
Context_Control *heir
);
+RTEMS_NO_RETURN void _CPU_Context_switch_no_return(
+ Context_Control *executing,
+ Context_Control *heir
+);
+
/*
* _CPU_Context_restore
*
@@ -925,6 +941,7 @@ void _CPU_Context_switch(
RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
+#if (PPC_HAS_FPU == 1)
/*
* _CPU_Context_save_fp
*
@@ -944,6 +961,7 @@ void _CPU_Context_save_fp(
void _CPU_Context_restore_fp(
Context_Control_fp **fp_context_ptr
);
+#endif
#ifdef RTEMS_SMP
uint32_t _CPU_SMP_Initialize( void );
@@ -968,16 +986,6 @@ void _CPU_Context_restore_fp(
}
void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
-
- static inline void _CPU_SMP_Processor_event_broadcast( void )
- {
- __asm__ volatile ( "" : : : "memory" );
- }
-
- static inline void _CPU_SMP_Processor_event_receive( void )
- {
- __asm__ volatile ( "" : : : "memory" );
- }
#endif
typedef struct {
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-19 12:06:45 +0000