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-rw-r--r--cpukit/score/cpu/no_cpu/ChangeLog8
-rw-r--r--cpukit/score/cpu/no_cpu/rtems/score/cpu.h13
2 files changed, 21 insertions, 0 deletions
diff --git a/cpukit/score/cpu/no_cpu/ChangeLog b/cpukit/score/cpu/no_cpu/ChangeLog
index 3403063650..c4a42eb055 100644
--- a/cpukit/score/cpu/no_cpu/ChangeLog
+++ b/cpukit/score/cpu/no_cpu/ChangeLog
@@ -1,3 +1,11 @@
+2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com>
+
+ * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
+ parameter to indicate that the port uses the Simple Vectored
+ Interrupt model or the Programmable Interrupt Controller Model. The
+ PIC model is implemented primarily in the BSP and it is responsible
+ for all memory allocation.
+
2008-01-29 Joel Sherrill <joel.sherrill@oarcorp.com>
* rtems/score/cpu.h: Remove most doxygen warnings.
diff --git a/cpukit/score/cpu/no_cpu/rtems/score/cpu.h b/cpukit/score/cpu/no_cpu/rtems/score/cpu.h
index d97800d5ac..73d063aad1 100644
--- a/cpukit/score/cpu/no_cpu/rtems/score/cpu.h
+++ b/cpukit/score/cpu/no_cpu/rtems/score/cpu.h
@@ -120,6 +120,19 @@ extern "C" {
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
/**
+ * Does the CPU follow the simple vectored interrupt model?
+ *
+ * If TRUE, then RTEMS allocates the vector table it internally manages.
+ * If FALSE, then the BSP is assumed to allocate and manage the vector
+ * table
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+
+/**
* Does this CPU have hardware support for a dedicated interrupt stack?
*
* If TRUE, then it must be installed during initialization.