diff options
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/no_cpu/rtems/score/cpu.h | 763 |
1 files changed, 472 insertions, 291 deletions
diff --git a/cpukit/score/cpu/no_cpu/rtems/score/cpu.h b/cpukit/score/cpu/no_cpu/rtems/score/cpu.h index 0c56f78232..d5d8f8aba1 100644 --- a/cpukit/score/cpu/no_cpu/rtems/score/cpu.h +++ b/cpukit/score/cpu/no_cpu/rtems/score/cpu.h @@ -1,9 +1,22 @@ -/* cpu.h +/** @file cpu.h * * This include file contains information pertaining to the XXX * processor. * - * COPYRIGHT (c) 1989-1999. + * @note This file is part of a porting template that is intended + * to be used as the starting point when porting RTEMS to a new + * CPU family. The following needs to be done when using this as + * the starting point for a new port: + * + * + Anywhere there is an XXX, it should be replaced + * with information about the CPU family being ported to. + * + * + At the end of each comment section, there is a heading which + * says "Port Specific Information:". When porting to RTEMS, + * add CPU family specific information in this section + */ + +/* COPYRIGHT (c) 1989-2004. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -27,30 +40,30 @@ extern "C" { /* conditional compilation parameters */ -/* - * Should the calls to _Thread_Enable_dispatch be inlined? +/** + * Should the calls to @ref _Thread_Enable_dispatch be inlined? * * If TRUE, then they are inlined. * If FALSE, then a subroutine call is made. * - * Basically this is an example of the classic trade-off of size + * This conditional is an example of the classic trade-off of size * versus speed. Inlining the call (TRUE) typically increases the * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will + * + * @note In general, the @ref _Thread_Dispatch_disable_level will * only be 0 or 1 unless you are in an interrupt handler and that * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] + * something calls @ref _Thread_Enable_dispatch which in turns calls + * @ref _Thread_Dispatch. If the enable dispatch is inlined, then + * one subroutine call is avoided entirely. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_INLINE_ENABLE_DISPATCH FALSE -/* +/** * Should the body of the search loops in _Thread_queue_Enqueue_priority * be unrolled one time? In unrolled each iteration of the loop examines * two "nodes" on the chain being searched. Otherwise, only one node @@ -67,17 +80,16 @@ extern "C" { * code is the longest interrupt disable period in RTEMS. So it is * necessary to strike a balance when setting this parameter. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE -/* +/** * Does RTEMS manage a dedicated interrupt stack in software? * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. * If FALSE, nothing is done. * * If the CPU supports a dedicated interrupt stack in hardware, @@ -89,75 +101,73 @@ extern "C" { * stack of the interrupted task, and (2) have RTEMS manage a dedicated * interrupt stack. * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is * possible that both are FALSE for a particular CPU. Although it * is unclear what that would imply about the interrupt processing * procedure on that CPU. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE -/* +/** * Does this CPU have hardware support for a dedicated interrupt stack? * * If TRUE, then it must be installed during initialization. * If FALSE, then no installation is performed. * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is * possible that both are FALSE for a particular CPU. Although it * is unclear what that would imply about the interrupt processing * procedure on that CPU. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE -/* +/** * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? * * If TRUE, then the memory is allocated during initialization. * If FALSE, then the memory is allocated during initialization. * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. + * This should be TRUE is @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE + * or @ref CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_ALLOCATE_INTERRUPT_STACK TRUE -/* +/** * Does the RTEMS invoke the user's ISR with the vector number and * a pointer to the saved interrupt frame (1) or just the vector * number (0)? * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_ISR_PASSES_FRAME_POINTER 0 -/* +/** + * @def CPU_HARDWARE_FP + * * Does the CPU have hardware floating point? * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * If TRUE, then the @ref RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the @ref RTEMS_FLOATING_POINT task attribute is ignored. * * If there is a FP coprocessor such as the i387 or mc68881, then * the answer is TRUE. @@ -167,18 +177,25 @@ extern "C" { * example, it would be possible to have an i386_nofp CPU model * which set this to false to indicate that you have an i386 without * an i387 and wish to leave floating point support out of RTEMS. + */ + +/** + * @def CPU_SOFTWARE_FP + * + * Does the CPU have no hardware floating point and GCC provides a + * software floating point implementation which must be context + * switched? * - * The CPU_SOFTWARE_FP is used to indicate whether or not there + * This feature conditional is used to indicate whether or not there * is software implemented floating point that must be context * switched. The determination of whether or not this applies * is very tool specific and the state saved/restored is also * compiler specific. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #if ( NO_CPU_HAS_FPU == 1 ) #define CPU_HARDWARE_FP TRUE #else @@ -186,11 +203,11 @@ extern "C" { #endif #define CPU_SOFTWARE_FP FALSE -/* +/** * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * If TRUE, then the @ref RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the @ref RTEMS_FLOATING_POINT task attribute is followed. * * So far, the only CPUs in which this option has been used are the * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and @@ -204,19 +221,18 @@ extern "C" { * then one can not easily predict which tasks will use the FP hardware. * In this case, this option should be TRUE. * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_ALL_TASKS_ARE_FP TRUE -/* +/** * Should the IDLE task have a floating point context? * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * If TRUE, then the IDLE task is created as a @ref RTEMS_FLOATING_POINT task * and it has a floating point context which is switched in and out. * If FALSE, then the IDLE task does not have a floating point context. * @@ -224,14 +240,13 @@ extern "C" { * the IDLE task from an interrupt because the floating point context * must be saved as part of the preemption. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_IDLE_TASK_IS_FP FALSE -/* +/** * Should the saving of the floating point registers be deferred * until a context switch is made to another different floating point * task? @@ -256,19 +271,18 @@ extern "C" { * Thus in a system with only one FP task, the FP context will never * be saved or restored. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_USE_DEFERRED_FP_SWITCH TRUE -/* +/** * Does this port provide a CPU dependent IDLE task implementation? * - * If TRUE, then the routine _CPU_Thread_Idle_body + * If TRUE, then the routine @ref _CPU_Thread_Idle_body * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. + * @ref _CPU_Thread_Idle_body. * * If FALSE, then use the generic IDLE thread body if the BSP does * not provide one. @@ -279,32 +293,30 @@ extern "C" { * * The order of precedence for selecting the IDLE thread body is: * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) + * -# BSP provided + * -# CPU dependent (if provided) + * -# generic (if no BSP and no CPU dependent) * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE -/* +/** * Does the stack grow up (toward higher addresses) or down * (toward lower addresses)? * * If TRUE, then the grows upward. * If FALSE, then the grows toward smaller addresses. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_STACK_GROWS_UP TRUE -/* +/** * The following is the variable attribute used to force alignment * of critical RTEMS structures. On some processors it may make * sense to have these aligned on tighter boundaries than @@ -318,64 +330,91 @@ extern "C" { * * __attribute__ ((aligned (32))) * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. + * @note Currently only the Priority Bit Map table uses this feature. + * To benefit from using this, the data must be heavily + * used so it will stay in the cache and used frequently enough + * in the executive to justify turning this on. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_STRUCTURE_ALIGNMENT -/* +/** + * @defgroup CPUEndian Processor Dependent Endianness Support + * + * This group assists in issues related to processor endianness. + */ + +/** + * @ingroup CPUEndian * Define what is required to specify how the network to host conversion * routines are handled. * - * NO_CPU Specific Information: + * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the + * same values. + * + * @see CPU_LITTLE_ENDIAN + * + * Port Specific Information: * * XXX document implementation including references if appropriate */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE #define CPU_BIG_ENDIAN TRUE + +/** + * @ingroup CPUEndian + * Define what is required to specify how the network to host conversion + * routines are handled. + * + * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the + * same values. + * + * @see CPU_BIG_ENDIAN + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ #define CPU_LITTLE_ENDIAN FALSE -/* +/** + * @ingroup CPUInterrupt * The following defines the number of bits actually used in the * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). + * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_MODES_INTERRUPT_MASK 0x00000001 /* * Processor defined structures required for cpukit/score. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ /* may need to put some structures here. */ -/* - * Contexts +/** + * @defgroup CPUContext Processor Dependent Context Management * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save + * From the highest level viewpoint, there are 2 types of context to save. * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt + * -# Interrupt registers to save + * -# Task level registers to save + * + * Since RTEMS handles integer and floating point contexts separately, this + * means we have the following 3 context items: + * + * -# task level context stuff:: Context_Control + * -# floating point task stuff:: Context_Control_fp + * -# special interrupt level context :: CPU_Interrupt_frame * * On some processors, it is cost-effective to save only the callee * preserved registers during a task context switch. This means @@ -399,54 +438,109 @@ extern "C" { * this is enough information for RTEMS, it is probably not enough for * a debugger such as gdb. But that is another problem. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ +/** + * @ingroup CPUContext Management + * This defines the minimal set of integer and processor state registers + * that must be saved during a voluntary context switch from one thread + * to another. + */ typedef struct { + /** This field is a hint that a port will have a number of integer + * registers that need to be saved at a context switch. + */ uint32_t some_integer_register; + /** This field is a hint that a port will have a number of system + * registers that need to be saved at a context switch. + */ uint32_t some_system_register; } Context_Control; +/** + * @ingroup CPUContext Management + * This defines the complete set of floating point registers that must + * be saved during any context switch from one thread to another. + */ typedef struct { double some_float_register; } Context_Control_fp; +/** + * @ingroup CPUContext Management + * This defines the set of integer and processor state registers that must + * be saved during an interrupt. This set does not include any which are + * in @ref Context_Control. + */ typedef struct { + /** This field is a hint that a port will have a number of integer + * registers that need to be saved when an interrupt occurs or + * when a context switch occurs at the end of an ISR. + */ uint32_t special_interrupt_register; } CPU_Interrupt_frame; -/* +/** * The following table contains the information required to configure * the XXX processor specific parameters. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ typedef struct { + /** This element points to the BSP's pretasking hook. */ void (*pretasking_hook)( void ); + /** This element points to the BSP's predriver hook. */ void (*predriver_hook)( void ); + /** This element points to the BSP's postdriver hook. */ void (*postdriver_hook)( void ); + /** This element points to the BSP's optional idle task which may override + * the default one provided with RTEMS. + */ void (*idle_task)( void ); + /** If this element is TRUE, then RTEMS will zero the Executive Workspace. + * When this element is FALSE, it is assumed that the BSP or invoking + * environment has ensured that memory was cleared before RTEMS was + * invoked. + */ boolean do_zero_of_workspace; + /** This field specifies the size of the IDLE task's stack. If less than or + * equal to the minimum stack size, then the IDLE task will have the minimum + * stack size. + */ uint32_t idle_task_stack_size; + /** This field specifies the size of the interrupt stack. If less than or + * equal to the minimum stack size, then the interrupt stack will be of + * minimum stack size. + */ uint32_t interrupt_stack_size; + /** The MPCI Receive server is assumed to have a stack of at least + * minimum stack size. This field specifies the amount of extra + * stack this task will be given in bytes. + */ uint32_t extra_mpci_receive_server_stack; + /** The BSP may want to provide it's own stack allocation routines. + * In this case, the BSP will provide this stack allocation hook. + */ void * (*stack_allocate_hook)( uint32_t ); - void (*stack_free_hook)( void* ); + /** The BSP may want to provide it's own stack free routines. + * In this case, the BSP will provide this stack free hook. + */ + void (*stack_free_hook)( void *); /* end of fields required on all CPUs */ - } rtems_cpu_table; /* * Macros to access required entires in the CPU Table are in * the file rtems/system.h. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ @@ -454,256 +548,279 @@ typedef struct { /* * Macros to access NO_CPU specific additions to the CPU Table * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ /* There are no CPU specific additions to the CPU Table for this port. */ -/* +/** * This variable is optional. It is used on CPUs on which it is difficult * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. + * @ref _CPU_Initialize and copied into the task's FP context area during + * @ref _CPU_Context_Initialize. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; -/* +/** + * @defgroup CPUInterrupt Processor Dependent Interrupt Management + * * On some CPUs, RTEMS supports a software managed interrupt stack. * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers + * is performed in @ref _ISR_Handler. These variables contain pointers * to the lowest and highest addresses in the chunk of memory allocated * for the interrupt stack. Since it is unknown whether the stack * grows up or down (in general), this give the CPU dependent * code the option of picking the version it wants to use. * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. + * @note These two variables are required if the macro + * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ +/** + * @ingroup CPUInterrupt + * This variable points to the lowest physical address of the interrupt + * stack. + */ SCORE_EXTERN void *_CPU_Interrupt_stack_low; + +/** + * @ingroup CPUInterrupt + * This variable points to the lowest physical address of the interrupt + * stack. + */ SCORE_EXTERN void *_CPU_Interrupt_stack_high; -/* +/** + * @ingroup CPUInterrupt * With some compilation systems, it is difficult if not impossible to * call a high-level language routine from assembly language. This * is especially true of commercial Ada compilers and name mangling * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This + * and contains the address of the routine @ref _Thread_Dispatch. This * can make it easier to invoke that routine at the end of the interrupt * sequence (if a dispatch is necessary). * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); /* * Nothing prevents the porter from declaring more CPU specific variables. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ /* XXX: if needed, put more variables here */ -/* +/** + * @ingroup CPUContext * The size of the floating point context area. On some CPUs this * will not be a "sizeof" because the format of the floating point * area is not defined -- only the size is. This is usually on * CPUs with a "floating point save context" instruction. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) -/* +/** * Amount of extra stack (above minimum stack size) required by * MPCI receive server thread. Remember that in a multiprocessor * system this thread must exist and be able to process all directives. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 -/* - * This defines the number of entries in the ISR_Vector_table managed +/** + * @ingroup CPUInterrupt + * This defines the number of entries in the @ref _ISR_Vector_table managed * by RTEMS. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 + +/** + * @ingroup CPUInterrupt + * This defines the highest interrupt vector number for this port. + */ #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) -/* +/** + * @ingroup CPUInterrupt * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. + * level. Most ports maintain the variable @a _ISR_Nest_level. */ - #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE -/* - * Should be large enough to run all RTEMS tests. This insures +/** + * @ingroup CPUContext + * Should be large enough to run all RTEMS tests. This ensures * that a "reasonable" small application should not have any problems. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_STACK_MINIMUM_SIZE (1024*4) -/* +/** * CPU's worst alignment requirement for data types on a byte boundary. This * alignment does not take into account the requirements for the stack. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_ALIGNMENT 8 -/* +/** * This number corresponds to the byte alignment requirement for the * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is + * for the data types alignment specified by @ref CPU_ALIGNMENT. It is * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. + * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for + * the heap, then this should be set to @ref CPU_ALIGNMENT. * - * NOTE: This does not have to be a power of 2 although it should be + * @note This does not have to be a power of 2 although it should be * a multiple of 2 greater than or equal to 2. The requirement * to be a multiple of 2 is because the heap uses the least * significant field of the front and back flags to indicate * that a block is in use or free. So you do not want any odd * length blocks really putting length data in that bit. * - * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than CPU_ALIGNMENT to ensure that + * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will + * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that * elements allocated from the heap meet all restrictions. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT -/* +/** * This number corresponds to the byte alignment requirement for memory * buffers allocated by the partition manager. This alignment requirement * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. + * @ref CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is + * strict enough for the partition, then this should be set to + * @ref CPU_ALIGNMENT. * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. + * @note This does not have to be a power of 2. It does have to + * be greater or equal to than @ref CPU_ALIGNMENT. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT -/* +/** * This number corresponds to the byte alignment requirement for the * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. + * data types alignment specified by @ref CPU_ALIGNMENT. If the + * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be + * set to 0. * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. + * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define CPU_STACK_ALIGNMENT 0 /* * ISR handler macros */ -/* +/** + * @ingroup CPUInterrupt * Support routine to initialize the RTEMS vector table after it is allocated. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define _CPU_Initialize_vectors() -/* +/** + * @ingroup CPUInterrupt * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. + * level is returned in @a _isr_cookie. + * + * @param _isr_cookie (out) will contain the previous level cookie * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define _CPU_ISR_Disable( _isr_cookie ) \ { \ (_isr_cookie) = 0; /* do something to prevent warnings */ \ } -/* +/** + * @ingroup CPUInterrupt * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. + * @a _isr_cookie is not modified. + * + * @param _isr_cookie (in) contain the previous level cookie * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define _CPU_ISR_Enable( _isr_cookie ) \ { \ } -/* - * This temporarily restores the interrupt to _level before immediately +/** + * @ingroup CPUInterrupt + * This temporarily restores the interrupt to @a _isr_cookie before immediately * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. + * sections into two or more parts. The parameter @a _isr_cookie is not + * modified. + * + * @param _isr_cookie (in) contain the previous level cookie * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define _CPU_ISR_Flash( _isr_cookie ) \ { \ } -/* - * Map interrupt level in task mode onto the hardware that the CPU +/** + * @ingroup CPUInterrupt + * + * This routine and @ref _CPU_ISR_Get_level + * Map the interrupt level in task mode onto the hardware that the CPU * actually provides. Currently, interrupt levels which do not * map onto the CPU in a generic fashion are undefined. Someday, * it would be nice if these were "mapped" by the application @@ -712,24 +829,33 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); * This could be used to manage a programmable interrupt controller * via the rtems_task_mode directive. * - * The get routine usually must be implemented as a subroutine. - * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define _CPU_ISR_Set_level( new_level ) \ { \ } +/** + * @ingroup CPUInterrupt + * Return the current interrupt disable level for this task in + * the format used by the interrupt level portion of the task mode. + * + * @note This routine usually must be implemented as a subroutine. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ uint32_t _CPU_ISR_Get_level( void ); /* end of ISR handler macros */ /* Context handler macros */ -/* +/** + * @ingroup CPUContext * Initialize the context to a state suitable for starting a * task after a context restore operation. Generally, this * involves: @@ -744,16 +870,21 @@ uint32_t _CPU_ISR_Get_level( void ); * in the context. The state of the "general data" registers is * undefined at task start time. * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating + * @param _the_context (in) is the context structure to be initialized + * @param _stack_base (in) is the lowest physical address of this task's stack + * @param _size (in) is the size of this task's stack + * @param _isr (in) is the interrupt disable level + * @param _entry_point (in) is the thread's entry point. This is + * always @a _Thread_Handler + * @param _is_fp (in) is TRUE if the thread is to be a floating * point thread. This is typically only used on CPUs where the * FPU may be easily disabled by software such as on the SPARC * where the PSR contains an enable FPU bit. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ _isr, _entry_point, _is_fp ) \ { \ @@ -764,19 +895,19 @@ uint32_t _CPU_ISR_Get_level( void ); * executing task. If you are lucky, then all that is necessary * is restoring the context. Otherwise, there will need to be * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will + * case. @ref _CPU_Context_Restore should work most of the time. It will * not work if restarting self conflicts with the stack frame * assumptions of restoring a context. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define _CPU_Context_Restart_self( _the_context ) \ _CPU_Context_restore( (_the_context) ); -/* +/** + * @ingroup CPUContext * The purpose of this macro is to allow the initial pointer into * a floating point context area (used to save the floating point * context) to be at an arbitrary place in the floating point @@ -789,30 +920,35 @@ uint32_t _CPU_ISR_Get_level( void ); * a "dump context" instruction which could fill in from high to low * or low to high based on the whim of the CPU designers. * - * NO_CPU Specific Information: + * @param _base (in) is the lowest physical address of the floating point + * context area + * @param _offset (in) is the offset into the floating point area + * + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define _CPU_Context_Fp_start( _base, _offset ) \ ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) -/* +/** * This routine initializes the FP context area passed to it to. * There are a few standard ways in which to initialize the * floating point context. The code included for this macro assumes * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination + * @a _CPU_Null_fp_context and it simply copies it to the destination * context passed to it. * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. + * Other floating point context save/restore models include: + * -# not doing anything, and + * -# putting a "null FP status word" in the correct place in the FP context. * - * NO_CPU Specific Information: + * @param _destination (in) is the floating point context area + * + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define _CPU_Context_Initialize_fp( _destination ) \ { \ *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ @@ -822,16 +958,15 @@ uint32_t _CPU_ISR_Get_level( void ); /* Fatal Error manager macros */ -/* +/** * This routine copies _error into a known place -- typically a stack * location or a register, optionally disables interrupts, and * halts/stops the CPU. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #define _CPU_Fatal_halt( _error ) \ { \ } @@ -840,29 +975,55 @@ uint32_t _CPU_ISR_Get_level( void ); /* Bitfield handler macros */ -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. +/** + * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation + * + * This set of routines are used to implement fast searches for + * the most important ready task. + */ + +/** + * @ingroup CPUBitfield + * This definition is set to TRUE if the port uses the generic bitfield + * manipulation implementation. + */ +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +/** + * @ingroup CPUBitfield + * This definition is set to TRUE if the port uses the data tables provided + * by the generic bitfield manipulation implementation. + * This can occur when actually using the generic bitfield manipulation + * implementation or when implementing the same algorithm in assembly + * language for improved performance. It is unlikely that a port will use + * the data if it has a bitfield scan instruction. + */ +#define CPU_USE_GENERIC_BITFIELD_DATA TRUE + +/** + * @ingroup CPUBitfield + * This routine sets @a _output to the bit number of the first bit + * set in @a _value. @a _value is of CPU dependent type + * @a Priority_Bit_map_control. This type may be either 16 or 32 bits + * wide although only the 16 least significant bits will be used. * * There are a number of variables in using a "find first bit" type * instruction. * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. + * -# What happens when run on a value of zero? + * -# Bits may be numbered from MSB to LSB or vice-versa. + * -# The numbering may be zero or one based. + * -# The "find first bit" instruction may search from MSB or LSB. * * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines + * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and + * @ref _CPU_Priority_bits_index. These three form a set of routines * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() + * set and cleared based on masks built by @ref _CPU_Priority_Mask. + * The basic major and minor values calculated by @ref _Priority_Major + * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to + * instruction. This makes it possible for @ref _Priority_Get_highest to * calculate the major and directly index into the minor table. * This mapping is necessary to ensure that 0 (a high priority major/minor) * is the first bit found. @@ -878,51 +1039,50 @@ uint32_t _CPU_ISR_Get_level( void ); * there are ways to make do without it. Here are a handful of ways * to implement this in software: * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * +@verbatim + - a series of 16 bit test instructions + - a "binary search using if's" + - _number = 0 + if _value > 0x00ff + _value >>=8 + _number = 8; + + if _value > 0x0000f + _value >=8 + _number += 4 + + _number += bit_set_table[ _value ] +@endverbatim + * where bit_set_table[ 16 ] has values which indicate the first * bit set * - * NO_CPU Specific Information: + * @param _value (in) is the value to be scanned + * @param _output (in) is the first bit set + * + * Port Specific Information: * * XXX document implementation including references if appropriate */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ { \ (_output) = 0; /* do something to prevent warnings */ \ } - #endif /* end of Bitfield handler macros */ -/* +/** * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion + * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion * for that routine. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) #define _CPU_Priority_Mask( _bit_number ) \ @@ -930,17 +1090,19 @@ uint32_t _CPU_ISR_Get_level( void ); #endif -/* +/** + * @ingroup CPUBitfield * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as + * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as * a major or minor component of a priority. See the discussion * for that routine. * - * NO_CPU Specific Information: + * @param _priority (in) is the major or minor number to translate + * + * Port Specific Information: * * XXX document implementation including references if appropriate */ - #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) #define _CPU_Priority_bits_index( _priority ) \ @@ -952,145 +1114,155 @@ uint32_t _CPU_ISR_Get_level( void ); /* functions */ -/* - * _CPU_Initialize - * +/** * This routine performs CPU dependent initialization. * - * NO_CPU Specific Information: + * @param cpu_table (in) is the CPU Dependent Configuration Table + * @param thread_dispatch (in) is the address of @ref _Thread_Dispatch + * + * Port Specific Information: * * XXX document implementation including references if appropriate */ - void _CPU_Initialize( rtems_cpu_table *cpu_table, void (*thread_dispatch) ); -/* - * _CPU_ISR_install_raw_handler - * +/** + * @ingroup CPUInterrupt * This routine installs a "raw" interrupt handler directly into the * processor's vector table. * - * NO_CPU Specific Information: + * @param vector (in) is the vector number + * @param new_handler (in) is the raw ISR handler to install + * @param old_handler (in) is the previously installed ISR Handler + * + * Port Specific Information: * * XXX document implementation including references if appropriate */ - void _CPU_ISR_install_raw_handler( uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler ); -/* - * _CPU_ISR_install_vector - * +/** + * @ingroup CPUInterrupt * This routine installs an interrupt vector. * - * NO_CPU Specific Information: + * @param vector (in) is the vector number + * @param new_handler (in) is the RTEMS ISR handler to install + * @param old_handler (in) is the previously installed ISR Handler + * + * Port Specific Information: * * XXX document implementation including references if appropriate */ - void _CPU_ISR_install_vector( uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler ); -/* - * _CPU_Install_interrupt_stack - * +/** + * @ingroup CPUInterrupt * This routine installs the hardware interrupt stack pointer. * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK + * @note It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK * is TRUE. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - void _CPU_Install_interrupt_stack( void ); -/* - * _CPU_Thread_Idle_body - * +/** * This routine is the CPU dependent IDLE thread body. * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY + * @note It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY * is TRUE. * - * NO_CPU Specific Information: + * Port Specific Information: * * XXX document implementation including references if appropriate */ - void _CPU_Thread_Idle_body( void ); -/* - * _CPU_Context_switch - * +/** + * @ingroup CPUContext * This routine switches from the run context to the heir context. * - * NO_CPU Specific Information: + * @param run (in) points to the context of the currently executing task + * @param heir (in) points to the context of the heir task + * + * Port Specific Information: * * XXX document implementation including references if appropriate */ - void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); -/* - * _CPU_Context_restore - * +/** + * @ingroup CPUContext * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. + * efficient manner. It may simply be a label in @ref _CPU_Context_switch. * - * NOTE: May be unnecessary to reload some registers. + * @param new_context (in) points to the context to be restored. * - * NO_CPU Specific Information: + * @note May be unnecessary to reload some registers. + * + * Port Specific Information: * * XXX document implementation including references if appropriate */ - void _CPU_Context_restore( Context_Control *new_context ); -/* - * _CPU_Context_save_fp - * +/** + * @ingroup CPUContext * This routine saves the floating point context passed to it. * - * NO_CPU Specific Information: + * @param fp_context_ptr (in) is a pointer to a pointer to a floating + * point context area + * + * @return on output @a *fp_context_ptr will contain the address that + * should be used with @ref _CPU_Context_restore_fp to restore this context. + * + * Port Specific Information: * * XXX document implementation including references if appropriate */ - void _CPU_Context_save_fp( void **fp_context_ptr ); -/* - * _CPU_Context_restore_fp - * +/** + * @ingroup CPUContext * This routine restores the floating point context passed to it. * - * NO_CPU Specific Information: + * @param fp_context_ptr (in) is a pointer to a pointer to a floating + * point context area to restore + * + * @return on output @a *fp_context_ptr will contain the address that + * should be used with @ref _CPU_Context_save_fp to save this context. + * + * Port Specific Information: * * XXX document implementation including references if appropriate */ - void _CPU_Context_restore_fp( void **fp_context_ptr ); -/* The following routine swaps the endian format of an unsigned int. +/** + * @ingroup CPUEndian + * The following routine swaps the endian format of an unsigned int. * It must be static because it is referenced indirectly. * * This version will work on any processor, but if there is a better @@ -1109,11 +1281,13 @@ void _CPU_Context_restore_fp( * endianness for ALL fetches -- both code and data -- so the code * will be fetched incorrectly. * - * NO_CPU Specific Information: + * @param value (in) is the value to be swapped + * @return the value after being endian swapped + * + * Port Specific Information: * * XXX document implementation including references if appropriate */ - static inline unsigned int CPU_swap_u32( unsigned int value ) @@ -1129,6 +1303,13 @@ static inline unsigned int CPU_swap_u32( return( swapped ); } +/** + * @ingroup CPUEndian + * This routine swaps a 16 bir quantity. + * + * @param value (in) is the value to be swapped + * @return the value after being endian swapped + */ #define CPU_swap_u16( value ) \ (((value&0xff) << 8) | ((value >> 8)&0xff)) |