diff options
Diffstat (limited to 'cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h')
| -rw-r--r-- | cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h | 221 |
1 files changed, 127 insertions, 94 deletions
diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h index c067501502..9ef6f43eb9 100644 --- a/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -28,9 +30,26 @@ * COPYRIGHT (c) 1989-2008. * On-Line Applications Research Corporation (OAR). * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _RTEMS_SCORE_CPU_H @@ -535,7 +554,8 @@ extern Context_Control_fp _CPU_Null_fp_context; * @addtogroup RTEMSScoreCPUExampleContext * * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. + * that a "reasonable" small application should not have any problems. The + * size shall be a power of two. * * Port Specific Information: * @@ -618,17 +638,6 @@ extern Context_Control_fp _CPU_Null_fp_context; /** * @addtogroup RTEMSScoreCPUExampleInterrupt * - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Initialize_vectors() - -/** - * @addtogroup RTEMSScoreCPUExampleInterrupt - * * Disable all interrupts for an RTEMS critical section. The previous * level is returned in @a _isr_cookie. * @@ -687,7 +696,7 @@ extern Context_Control_fp _CPU_Null_fp_context; * @retval true Interrupts are enabled in the ISR level. * @retval false Otherwise. */ -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return false; } @@ -835,23 +844,6 @@ uint32_t _CPU_ISR_Get_level( void ); /* end of Context handler macros */ -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - /* Bitfield handler macros */ /** @@ -1054,23 +1046,47 @@ void _CPU_ISR_install_vector( void *_CPU_Thread_Idle_body( uintptr_t ignored ); /** + * @brief Performs a context switch from the executing thread to the heir + * thread. + * * @addtogroup RTEMSScoreCPUExampleContext * - * This routine switches from the run context to the heir context. + * This routine switches from the executing context to the heir context. + * + * @param[out] executing points to the context of the currently executing task. * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task + * @param[in, out] heir points to the context of the heir task. * * Port Specific Information: * * XXX document implementation including references if appropriate */ void _CPU_Context_switch( - Context_Control *run, + Context_Control *executing, Context_Control *heir ); /** + * @brief Performs a context switch from the executing thread to the heir + * thread and does not return. + * + * @addtogroup RTEMSScoreCPUExampleContext + * + * This routine shall be a strong alias to _CPU_Context_switch(). It shall be + * provided for all target architectures which support an SMP build + * configuration (RTEMS_SMP). The purpose is help to compiler to avoid + * generation of dead code in _Thread_Start_multitasking(). + * + * @param[out] executing points to the context of the currently executing task. + * + * @param[in, out] heir points to the context of the heir task. + */ +RTEMS_NO_RETURN void _CPU_Context_switch_no_return( + Context_Control *executing, + Context_Control *heir +); + +/** * @addtogroup RTEMSScoreCPUExampleContext * * This routine is generally used only to restart self in an @@ -1146,6 +1162,69 @@ typedef struct { */ void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); +#ifdef RTEMS_EXCEPTION_EXTENSIONS + /** + * @brief Resumes normal execution using the provided exception frame. + * + * This routine helps to avoid dead code in the exception handler epilogue and + * does not return. This routine may assume that the provided pointer is valid + * for resetting the exception stack. + * + * @param frame The CPU_Exception_frame describing the machine exception. + */ + RTEMS_NO_RETURN void _CPU_Exception_resume( CPU_Exception_frame *frame ); + + /** + * @brief Performs thread dispatch and resumes normal execution. + * + * This routine helps to avoid dead code in the exception handler epilogue and + * does not return. This routine may assume that the provided pointer is valid + * for resetting the exception stack. This function is expected to decrement + * the ISR nest level and thread dispatch disable level in the Per_CPU_Control + * structure. + * + * @param frame The CPU_Exception_frame describing the machine + * exception. + */ + RTEMS_NO_RETURN void _CPU_Exception_dispatch_and_resume( + CPU_Exception_frame *frame + ); + + /** + * @brief Disables thread dispatch. + * + * This must be called before calling _CPU_Exception_dispatch_and_resume + * since that function is expected to reduce the levels incremented below. + */ + void _CPU_Exception_disable_thread_dispatch( void ); + + /** + * @brief Retrieves the generic exception class of the machine exception. + * + * @param frame The CPU_Exception_frame describing the machine + * exception. + * @return The signal associated with the CPU_Exception_frame. + */ + int _CPU_Exception_frame_get_signal( CPU_Exception_frame *frame ); + + /** + * @brief Sets the execution address of the exception frame. + * + * @param frame The CPU_Exception_frame describing the machine exception. + * @param address The address at which execution should resume. + */ + void _CPU_Exception_frame_set_resume( CPU_Exception_frame *frame, void *address ); + + /** + * @brief Sets the execution address of the exception frame to the next + * instruction. + * + * @param frame The CPU_Exception_frame describing the machine + * exception. + */ + void _CPU_Exception_frame_make_resume_next_instruction( CPU_Exception_frame *frame ); +#endif + /** * @defgroup RTEMSScoreCPUExampleCPUEndian CPUEndian * @@ -1215,44 +1294,27 @@ static inline uint32_t CPU_swap_u32( typedef uint32_t CPU_Counter_ticks; /** - * @brief Returns the current CPU counter frequency in Hz. + * @brief Gets the current CPU counter frequency in Hz. * - * @return The current CPU counter frequency in Hz. + * @return Returns the current CPU counter frequency in Hz. */ uint32_t _CPU_Counter_frequency( void ); /** - * @brief Returns the current CPU counter value. + * @brief Gets the current CPU counter value. * - * A CPU counter is some free-running counter. It ticks usually with a - * frequency close to the CPU or system bus clock. The board support package - * must ensure that this function works before the RTEMS initialization. - * Otherwise invalid profiling statistics will be gathered. + * A CPU counter should be some monotonically increasing free-running counter. + * It ticks usually with a frequency close to the CPU or system bus clock. The + * counter should not be affected by power saving states so that it can be used + * for timestamps. The CPU counter should be initialized at the + * RTEMS_SYSINIT_CPU_COUNTER initialization step if necessary. If + * RTEMS_PROFILING is enabled, the CPU counter may have to work very early in + * the system initialization to avoid invalid profiling statistics. * - * @return The current CPU counter value. + * @return Returns the current CPU counter value. */ CPU_Counter_ticks _CPU_Counter_read( void ); -/** - * @brief Returns the difference between the second and first CPU counter - * value. - * - * This operation may be carried out as a modulo operation depending on the - * range of the CPU counter device. - * - * @param[in] second The second CPU counter value. - * @param[in] first The first CPU counter value. - * - * @return Returns second minus first modulo counter period. - */ -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - #ifdef RTEMS_SMP /** * @brief Performs CPU specific SMP initialization in the context of the boot @@ -1335,35 +1397,6 @@ static inline CPU_Counter_ticks _CPU_Counter_difference( void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); /** - * @brief Broadcasts a processor event. - * - * Some architectures provide a low-level synchronization primitive for - * processors in a multi-processor environment. Processors waiting for this - * event may go into a low-power state and stop generating system bus - * transactions. This function must ensure that preceding store operations - * can be observed by other processors. - * - * @see _CPU_SMP_Processor_event_receive(). - */ - static inline void _CPU_SMP_Processor_event_broadcast( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } - - /** - * @brief Receives a processor event. - * - * This function will wait for the processor event and may wait forever if no - * such event arrives. - * - * @see _CPU_SMP_Processor_event_broadcast(). - */ - static inline void _CPU_SMP_Processor_event_receive( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } - - /** * @brief Gets the is executing indicator of the thread context. * * @param[in] context The context. |