diff options
Diffstat (limited to 'cpukit/score/cpu/mips/rtems')
| -rw-r--r-- | cpukit/score/cpu/mips/rtems/asm.h | 159 | ||||
| -rw-r--r-- | cpukit/score/cpu/mips/rtems/mips/idtcpu.h | 697 | ||||
| -rw-r--r-- | cpukit/score/cpu/mips/rtems/mips/iregdef.h | 332 | ||||
| -rw-r--r-- | cpukit/score/cpu/mips/rtems/score/cpu.h | 1156 | ||||
| -rw-r--r-- | cpukit/score/cpu/mips/rtems/score/mips.h | 283 | ||||
| -rw-r--r-- | cpukit/score/cpu/mips/rtems/score/types.h | 45 |
6 files changed, 2672 insertions, 0 deletions
diff --git a/cpukit/score/cpu/mips/rtems/asm.h b/cpukit/score/cpu/mips/rtems/asm.h new file mode 100644 index 0000000000..0ef10f8baa --- /dev/null +++ b/cpukit/score/cpu/mips/rtems/asm.h @@ -0,0 +1,159 @@ +/** + * @file rtems/asm.h + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + */ + +/* + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + * + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1994-1997. + * On-Line Applications Research Corporation (OAR). + * + * $Id$ + */ +/* @(#)asm.h 03/15/96 1.1 */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include <rtems/system.h> +#include <rtems/score/cpuopts.h> +#include <rtems/score/mips.h> + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +#include <rtems/concat.h> + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .globl SYM (sym) +#define EXTERN(sym) .globl SYM (sym) + +/* + * Debugger macros for assembly language routines. Allows the + * programmer to set up the necessary stack frame info + * required by debuggers to do stack traces. + */ + +#ifndef XDS +#define FRAME(name,frm_reg,offset,ret_reg) \ + .globl name; \ + .ent name; \ +name:; \ + .frame frm_reg,offset,ret_reg +#define ENDFRAME(name) \ + .end name +#else +#define FRAME(name,frm_reg,offset,ret_reg) \ + .globl _##name;\ +_##name: +#define ENDFRAME(name) +#endif /* XDS */ + +/* + * Hardware Floating Point Registers + */ + +#define R_FP0 0 +#define R_FP1 1 +#define R_FP2 2 +#define R_FP3 3 +#define R_FP4 4 +#define R_FP5 5 +#define R_FP6 6 +#define R_FP7 7 +#define R_FP8 8 +#define R_FP9 9 +#define R_FP10 10 +#define R_FP11 11 +#define R_FP12 12 +#define R_FP13 13 +#define R_FP14 14 +#define R_FP15 15 +#define R_FP16 16 +#define R_FP17 17 +#define R_FP18 18 +#define R_FP19 19 +#define R_FP20 20 +#define R_FP21 21 +#define R_FP22 22 +#define R_FP23 23 +#define R_FP24 24 +#define R_FP25 25 +#define R_FP26 26 +#define R_FP27 27 +#define R_FP28 28 +#define R_FP29 29 +#define R_FP30 30 +#define R_FP31 31 + +#endif +/* end of include file */ + diff --git a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h new file mode 100644 index 0000000000..c8c8569f4a --- /dev/null +++ b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h @@ -0,0 +1,697 @@ +/* + +Based upon IDT provided code with the following release: + +This source code has been made available to you by IDT on an AS-IS +basis. Anyone receiving this source is licensed under IDT copyrights +to use it in any way he or she deems fit, including copying it, +modifying it, compiling it, and redistributing it either with or +without modifications. No license under IDT patents or patent +applications is to be implied by the copyright license. + +Any user of this software should understand that IDT cannot provide +technical support for this software and will not be responsible for +any consequences resulting from the use of this software. + +Any person who transfers this source code or any derivative work must +include the IDT copyright notice, this paragraph, and the preceeding +two paragraphs in the transferred software. + +COPYRIGHT IDT CORPORATION 1996 +LICENSED MATERIAL - PROGRAM PROPERTY OF IDT + + $Id$ +*/ + +/* +** idtcpu.h -- cpu related defines +*/ + +#ifndef _RTEMS_MIPS_IDTCPU_H +#define _RTEMS_MIPS_IDTCPU_H + +/* + * 950313: Ketan added Register definition for XContext reg. + * added define for WAIT instruction. + * 950421: Ketan added Register definition for Config reg (R3081) + */ + +/* +** memory configuration and mapping +*/ +#define K0BASE 0x80000000 +#define K0SIZE 0x20000000 +#define K1BASE 0xa0000000 +#define K1SIZE 0x20000000 +#define K2BASE 0xc0000000 +#define K2SIZE 0x20000000 +#if __mips == 3 +#define KSBASE 0xe0000000 +#define KSSIZE 0x20000000 +#endif + +#define KUBASE 0 +#define KUSIZE 0x80000000 + +/* +** Exception Vectors +*/ +#if __mips == 1 +#define UT_VEC K0BASE /* utlbmiss vector */ +#define DB_VEC (K0BASE+0x40) /* debug vector */ +#define E_VEC (K0BASE+0x80) /* exception vector */ +#elif __mips == 32 +#define T_VEC (K0BASE+0x000) /* tlbmiss vector */ +#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */ +#define C_VEC (K0BASE+0x100) /* cache error vector */ +#define E_VEC (K0BASE+0x180) /* exception vector */ +#elif __mips == 3 +#define T_VEC (K0BASE+0x000) /* tlbmiss vector */ +#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */ +#define C_VEC (K0BASE+0x100) /* cache error vector */ +#define E_VEC (K0BASE+0x180) /* exception vector */ +#else +#error "EXCEPTION VECTORS: unknown ISA level" +#endif +#define R_VEC (K1BASE+0x1fc00000) /* reset vector */ + +/* +** Address conversion macros +*/ +#ifdef CLANGUAGE +#define CAST(as) (as) +#else +#define CAST(as) +#endif +#define K0_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */ +#define K1_TO_K0(x) (CAST(unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */ +#define K0_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */ +#define K1_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */ +#define PHYS_TO_K0(x) (CAST(unsigned)(x)|0x80000000) /* physical to kseg0 */ +#define PHYS_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* physical to kseg1 */ + +/* +** Cache size constants +*/ +#define MINCACHE 0x200 /* 512 For 3041. */ +#define MAXCACHE 0x40000 /* 256*1024 256k */ + +#if __mips == 32 +/* R4000 configuration register definitions */ +#define CFG_CM 0x80000000 /* Master-Checker mode */ +#define CFG_ECMASK 0x70000000 /* System Clock Ratio */ +#define CFG_ECBY2 0x00000000 /* divide by 2 */ +#define CFG_ECBY3 0x10000000 /* divide by 3 */ +#define CFG_ECBY4 0x20000000 /* divide by 4 */ +#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */ +#define CFG_EPD 0x00000000 /* D */ +#define CFG_EPDDX 0x01000000 /* DDX */ +#define CFG_EPDDXX 0x02000000 /* DDXX */ +#define CFG_EPDXDX 0x03000000 /* DXDX */ +#define CFG_EPDDXXX 0x04000000 /* DDXXX */ +#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */ +#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */ +#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */ +#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */ +#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */ +#define CFG_SBSHIFT 22 +#define CFG_SB4 0x00000000 /* 4 words */ +#define CFG_SB8 0x00400000 /* 8 words */ +#define CFG_SB16 0x00800000 /* 16 words */ +#define CFG_SB32 0x00c00000 /* 32 words */ +#define CFG_SS 0x00200000 /* Split secondary cache */ +#define CFG_SW 0x00100000 /* Secondary cache port width */ +#define CFG_EWMASK 0x000c0000 /* System port width */ +#define CFG_EWSHIFT 18 +#define CFG_EW64 0x00000000 /* 64 bit */ +#define CFG_EW32 0x00010000 /* 32 bit */ +#define CFG_SC 0x00020000 /* Secondary cache absent */ +#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */ +#define CFG_BE 0x00008000 /* Big Endian */ +#define CFG_EM 0x00004000 /* ECC mode enable */ +#define CFG_EB 0x00002000 /* Block ordering */ +#define CFG_ICMASK 0x00000e00 /* Instruction cache size */ +#define CFG_ICSHIFT 9 +#define CFG_DCMASK 0x000001c0 /* Data cache size */ +#define CFG_DCSHIFT 6 +#define CFG_IB 0x00000020 /* Instruction cache block size */ +#define CFG_DB 0x00000010 /* Data cache block size */ +#define CFG_CU 0x00000008 /* Update on Store Conditional */ +#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */ + +/* + * R4000 primary cache mode + */ +#define CFG_C_UNCACHED 2 +#define CFG_C_NONCOHERENT 3 +#define CFG_C_COHERENTXCL 4 +#define CFG_C_COHERENTXCLW 5 +#define CFG_C_COHERENTUPD 6 + +/* + * R4000 cache operations (should be in assembler...?) + */ +#define Index_Invalidate_I 0x0 /* 0 0 */ +#define Index_Writeback_Inv_D 0x1 /* 0 1 */ +#define Index_Invalidate_SI 0x2 /* 0 2 */ +#define Index_Writeback_Inv_SD 0x3 /* 0 3 */ +#define Index_Load_Tag_I 0x4 /* 1 0 */ +#define Index_Load_Tag_D 0x5 /* 1 1 */ +#define Index_Load_Tag_SI 0x6 /* 1 2 */ +#define Index_Load_Tag_SD 0x7 /* 1 3 */ +#define Index_Store_Tag_I 0x8 /* 2 0 */ +#define Index_Store_Tag_D 0x9 /* 2 1 */ +#define Index_Store_Tag_SI 0xA /* 2 2 */ +#define Index_Store_Tag_SD 0xB /* 2 3 */ +#define Create_Dirty_Exc_D 0xD /* 3 1 */ +#define Create_Dirty_Exc_SD 0xF /* 3 3 */ +#define Hit_Invalidate_I 0x10 /* 4 0 */ +#define Hit_Invalidate_D 0x11 /* 4 1 */ +#define Hit_Invalidate_SI 0x12 /* 4 2 */ +#define Hit_Invalidate_SD 0x13 /* 4 3 */ +#define Hit_Writeback_Inv_D 0x15 /* 5 1 */ +#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */ +#define Fill_I 0x14 /* 5 0 */ +#define Hit_Writeback_D 0x19 /* 6 1 */ +#define Hit_Writeback_SD 0x1B /* 6 3 */ +#define Hit_Writeback_I 0x18 /* 6 0 */ +#define Hit_Set_Virtual_SI 0x1E /* 7 2 */ +#define Hit_Set_Virtual_SD 0x1F /* 7 3 */ + +/* Disabled by chris -- horrible overload of common word. +#ifndef WAIT +#define WAIT .word 0x42000020 +#endif +*/ +/* Disabled by joel -- horrible overload of common word. +#ifndef wait +#define wait .word 0x42000020 +#endif wait +*/ + +#endif + +#if __mips == 3 +/* R4000 configuration register definitions */ +#define CFG_CM 0x80000000 /* Master-Checker mode */ +#define CFG_ECMASK 0x70000000 /* System Clock Ratio */ +#define CFG_ECBY2 0x00000000 /* divide by 2 */ +#define CFG_ECBY3 0x10000000 /* divide by 3 */ +#define CFG_ECBY4 0x20000000 /* divide by 4 */ +#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */ +#define CFG_EPD 0x00000000 /* D */ +#define CFG_EPDDX 0x01000000 /* DDX */ +#define CFG_EPDDXX 0x02000000 /* DDXX */ +#define CFG_EPDXDX 0x03000000 /* DXDX */ +#define CFG_EPDDXXX 0x04000000 /* DDXXX */ +#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */ +#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */ +#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */ +#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */ +#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */ +#define CFG_SBSHIFT 22 +#define CFG_SB4 0x00000000 /* 4 words */ +#define CFG_SB8 0x00400000 /* 8 words */ +#define CFG_SB16 0x00800000 /* 16 words */ +#define CFG_SB32 0x00c00000 /* 32 words */ +#define CFG_SS 0x00200000 /* Split secondary cache */ +#define CFG_SW 0x00100000 /* Secondary cache port width */ +#define CFG_EWMASK 0x000c0000 /* System port width */ +#define CFG_EWSHIFT 18 +#define CFG_EW64 0x00000000 /* 64 bit */ +#define CFG_EW32 0x00010000 /* 32 bit */ +#define CFG_SC 0x00020000 /* Secondary cache absent */ +#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */ +#define CFG_BE 0x00008000 /* Big Endian */ +#define CFG_EM 0x00004000 /* ECC mode enable */ +#define CFG_EB 0x00002000 /* Block ordering */ +#define CFG_ICMASK 0x00000e00 /* Instruction cache size */ +#define CFG_ICSHIFT 9 +#define CFG_DCMASK 0x000001c0 /* Data cache size */ +#define CFG_DCSHIFT 6 +#define CFG_IB 0x00000020 /* Instruction cache block size */ +#define CFG_DB 0x00000010 /* Data cache block size */ +#define CFG_CU 0x00000008 /* Update on Store Conditional */ +#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */ + +/* + * R4000 primary cache mode + */ +#define CFG_C_UNCACHED 2 +#define CFG_C_NONCOHERENT 3 +#define CFG_C_COHERENTXCL 4 +#define CFG_C_COHERENTXCLW 5 +#define CFG_C_COHERENTUPD 6 + +/* + * R4000 cache operations (should be in assembler...?) + */ +#define Index_Invalidate_I 0x0 /* 0 0 */ +#define Index_Writeback_Inv_D 0x1 /* 0 1 */ +#define Index_Invalidate_SI 0x2 /* 0 2 */ +#define Index_Writeback_Inv_SD 0x3 /* 0 3 */ +#define Index_Load_Tag_I 0x4 /* 1 0 */ +#define Index_Load_Tag_D 0x5 /* 1 1 */ +#define Index_Load_Tag_SI 0x6 /* 1 2 */ +#define Index_Load_Tag_SD 0x7 /* 1 3 */ +#define Index_Store_Tag_I 0x8 /* 2 0 */ +#define Index_Store_Tag_D 0x9 /* 2 1 */ +#define Index_Store_Tag_SI 0xA /* 2 2 */ +#define Index_Store_Tag_SD 0xB /* 2 3 */ +#define Create_Dirty_Exc_D 0xD /* 3 1 */ +#define Create_Dirty_Exc_SD 0xF /* 3 3 */ +#define Hit_Invalidate_I 0x10 /* 4 0 */ +#define Hit_Invalidate_D 0x11 /* 4 1 */ +#define Hit_Invalidate_SI 0x12 /* 4 2 */ +#define Hit_Invalidate_SD 0x13 /* 4 3 */ +#define Hit_Writeback_Inv_D 0x15 /* 5 1 */ +#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */ +#define Fill_I 0x14 /* 5 0 */ +#define Hit_Writeback_D 0x19 /* 6 1 */ +#define Hit_Writeback_SD 0x1B /* 6 3 */ +#define Hit_Writeback_I 0x18 /* 6 0 */ +#define Hit_Set_Virtual_SI 0x1E /* 7 2 */ +#define Hit_Set_Virtual_SD 0x1F /* 7 3 */ + +/* Disabled by chris -- horrible overload of common word. +#ifndef WAIT +#define WAIT .word 0x42000020 +#endif +*/ +/* Disabled by joel -- horrible overload of common word. +#ifndef wait +#define wait .word 0x42000020 +#endif wait +*/ + +#endif + +/* +** TLB resource defines +*/ +#if __mips == 1 +#define N_TLB_ENTRIES 64 +#define TLB_PGSIZE 0x1000 +#define RANDBASE 8 +#define TLBLO_PFNMASK 0xfffff000 +#define TLBLO_PFNSHIFT 12 +#define TLBLO_N 0x800 /* non-cacheable */ +#define TLBLO_D 0x400 /* writeable */ +#define TLBLO_V 0x200 /* valid bit */ +#define TLBLO_G 0x100 /* global access bit */ + +#define TLBHI_VPNMASK 0xfffff000 +#define TLBHI_VPNSHIFT 12 +#define TLBHI_PIDMASK 0xfc0 +#define TLBHI_PIDSHIFT 6 +#define TLBHI_NPID 64 + +#define TLBINX_PROBE 0x80000000 +#define TLBINX_INXMASK 0x00003f00 +#define TLBINX_INXSHIFT 8 + +#define TLBRAND_RANDMASK 0x00003f00 +#define TLBRAND_RANDSHIFT 8 + +#define TLBCTXT_BASEMASK 0xffe00000 +#define TLBCTXT_BASESHIFT 21 + +#define TLBCTXT_VPNMASK 0x001ffffc +#define TLBCTXT_VPNSHIFT 2 +#endif +#if __mips == 3 +#define N_TLB_ENTRIES 48 + +#define TLBHI_VPN2MASK 0xffffe000 +#define TLBHI_PIDMASK 0x000000ff +#define TLBHI_NPID 256 + +#define TLBLO_PFNMASK 0x3fffffc0 +#define TLBLO_PFNSHIFT 6 +#define TLBLO_D 0x00000004 /* writeable */ +#define TLBLO_V 0x00000002 /* valid bit */ +#define TLBLO_G 0x00000001 /* global access bit */ +#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */ +#define TLBLO_CSHIFT 3 + +#define TLBLO_UNCACHED (CFG_C_UNCACHED<<TLBLO_CSHIFT) +#define TLBLO_NONCOHERENT (CFG_C_NONCOHERENT<<TLBLO_CSHIFT) +#define TLBLO_COHERENTXCL (CFG_C_COHERENTXCL<<TLBLO_CSHIFT) +#define TLBLO_COHERENTXCLW (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT) +#define TLBLO_COHERENTUPD (CFG_C_COHERENTUPD<<TLBLO_CSHIFT) + +#define TLBINX_PROBE 0x80000000 +#define TLBINX_INXMASK 0x0000003f + +#define TLBRAND_RANDMASK 0x0000003f + +#define TLBCTXT_BASEMASK 0xff800000 +#define TLBCTXT_BASESHIFT 23 + +#define TLBCTXT_VPN2MASK 0x007ffff0 +#define TLBCTXT_VPN2SHIFT 4 + +#define TLBPGMASK_MASK 0x01ffe000 +#endif + +#if __mips == 32 +#define N_TLB_ENTRIES 16 + +#define TLBHI_VPN2MASK 0xffffe000 +#define TLBHI_PIDMASK 0x000000ff +#define TLBHI_NPID 256 + +#define TLBLO_PFNMASK 0x3fffffc0 +#define TLBLO_PFNSHIFT 6 +#define TLBLO_D 0x00000004 /* writeable */ +#define TLBLO_V 0x00000002 /* valid bit */ +#define TLBLO_G 0x00000001 /* global access bit */ +#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */ +#define TLBLO_CSHIFT 3 + +#define TLBLO_UNCACHED (CFG_C_UNCACHED<<TLBLO_CSHIFT) +#define TLBLO_NONCOHERENT (CFG_C_NONCOHERENT<<TLBLO_CSHIFT) +#define TLBLO_COHERENTXCL (CFG_C_COHERENTXCL<<TLBLO_CSHIFT) +#define TLBLO_COHERENTXCLW (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT) +#define TLBLO_COHERENTUPD (CFG_C_COHERENTUPD<<TLBLO_CSHIFT) + +#define TLBINX_PROBE 0x80000000 +#define TLBINX_INXMASK 0x0000003f + +#define TLBRAND_RANDMASK 0x0000003f + +#define TLBCTXT_BASEMASK 0xff800000 +#define TLBCTXT_BASESHIFT 23 + +#define TLBCTXT_VPN2MASK 0x007ffff0 +#define TLBCTXT_VPN2SHIFT 4 + +#define TLBPGMASK_MASK 0x01ffe000 +#endif + +#if __mips == 1 + + +/* definitions for Debug and Cache Invalidate control (DCIC) register bits */ +#define DCIC_TR 0x80000000 /* Trap enable */ +#define DCIC_UD 0x40000000 /* User debug enable */ +#define DCIC_KD 0x20000000 /* Kernel debug enable */ +#define DCIC_TE 0x10000000 /* Trace enable */ +#define DCIC_DW 0x08000000 /* Enable data breakpoints on write */ +#define DCIC_DR 0x04000000 /* Enable data breakpoints on read */ +#define DCIC_DAE 0x02000000 /* Enable data addresss breakpoints */ +#define DCIC_PCE 0x01000000 /* Enable instruction breakpoints */ +#define DCIC_DE 0x00800000 /* Debug enable */ +#define DCIC_DL 0x00008000 /* Data cache line invalidate */ +#define DCIC_IL 0x00004000 /* Instruction cache line invalidate */ +#define DCIC_D 0x00002000 /* Data cache invalidate enable */ +#define DCIC_I 0x00001000 /* Instr. cache invalidate enable */ +#define DCIC_T 0x00000020 /* Trace, set by CPU */ +#define DCIC_W 0x00000010 /* Write reference, set by CPU */ +#define DCIC_R 0x00000008 /* Read reference, set by CPU */ +#define DCIC_DA 0x00000004 /* Data address, set by CPU */ +#define DCIC_PC 0x00000002 /* Program counter, set by CPU */ +#define DCIC_DB 0x00000001 /* Debug, set by CPU */ + + + + +#define SR_CUMASK 0xf0000000 /* coproc usable bits */ +#define SR_CU3 0x80000000 /* Coprocessor 3 usable */ +#define SR_CU2 0x40000000 /* Coprocessor 2 usable */ +#define SR_CU1 0x20000000 /* Coprocessor 1 usable */ +#define SR_CU0 0x10000000 /* Coprocessor 0 usable */ + +#define SR_BEV 0x00400000 /* use boot exception vectors */ + +/* Cache control bits */ +#define SR_TS 0x00200000 /* TLB shutdown */ +#define SR_PE 0x00100000 /* cache parity error */ +#define SR_CM 0x00080000 /* cache miss */ +#define SR_PZ 0x00040000 /* cache parity zero */ +#define SR_SWC 0x00020000 /* swap cache */ +#define SR_ISC 0x00010000 /* Isolate data cache */ + +/* +** status register interrupt masks and bits +*/ + +#define SR_IMASK 0x0000ff00 /* Interrupt mask */ +#define SR_IMASK8 0x00000000 /* mask level 8 */ +#define SR_IMASK7 0x00008000 /* mask level 7 */ +#define SR_IMASK6 0x0000c000 /* mask level 6 */ +#define SR_IMASK5 0x0000e000 /* mask level 5 */ +#define SR_IMASK4 0x0000f000 /* mask level 4 */ +#define SR_IMASK3 0x0000f800 /* mask level 3 */ +#define SR_IMASK2 0x0000fc00 /* mask level 2 */ +#define SR_IMASK1 0x0000fe00 /* mask level 1 */ +#define SR_IMASK0 0x0000ff00 /* mask level 0 */ + +#define SR_IMASKSHIFT 8 + +#define SR_IBIT8 0x00008000 /* bit level 8 */ +#define SR_IBIT7 0x00004000 /* bit level 7 */ +#define SR_IBIT6 0x00002000 /* bit level 6 */ +#define SR_IBIT5 0x00001000 /* bit level 5 */ +#define SR_IBIT4 0x00000800 /* bit level 4 */ +#define SR_IBIT3 0x00000400 /* bit level 3 */ +#define SR_IBIT2 0x00000200 /* bit level 2 */ +#define SR_IBIT1 0x00000100 /* bit level 1 */ + +#define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */ +#define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */ +#define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */ +#define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */ +#define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */ +#define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */ +#endif + +#if __mips == 3 +#define SR_CUMASK 0xf0000000 /* coproc usable bits */ +#define SR_CU3 0x80000000 /* Coprocessor 3 usable */ +#define SR_CU2 0x40000000 /* Coprocessor 2 usable */ +#define SR_CU1 0x20000000 /* Coprocessor 1 usable */ +#define SR_CU0 0x10000000 /* Coprocessor 0 usable */ + +#define SR_RP 0x08000000 /* Reduced power operation */ +#define SR_FR 0x04000000 /* Additional floating point registers */ +#define SR_RE 0x02000000 /* Reverse endian in user mode */ + +#define SR_BEV 0x00400000 /* Use boot exception vectors */ +#define SR_TS 0x00200000 /* TLB shutdown */ +#define SR_SR 0x00100000 /* Soft reset */ +#define SR_CH 0x00040000 /* Cache hit */ +#define SR_CE 0x00020000 /* Use cache ECC */ +#define SR_DE 0x00010000 /* Disable cache exceptions */ + +/* +** status register interrupt masks and bits +*/ + +#define SR_IMASK 0x0000ff00 /* Interrupt mask */ +#define SR_IMASK8 0x00000000 /* mask level 8 */ +#define SR_IMASK7 0x00008000 /* mask level 7 */ +#define SR_IMASK6 0x0000c000 /* mask level 6 */ +#define SR_IMASK5 0x0000e000 /* mask level 5 */ +#define SR_IMASK4 0x0000f000 /* mask level 4 */ +#define SR_IMASK3 0x0000f800 /* mask level 3 */ +#define SR_IMASK2 0x0000fc00 /* mask level 2 */ +#define SR_IMASK1 0x0000fe00 /* mask level 1 */ +#define SR_IMASK0 0x0000ff00 /* mask level 0 */ + +#define SR_IMASKSHIFT 8 + +#define SR_IBIT8 0x00008000 /* bit level 8 */ +#define SR_IBIT7 0x00004000 /* bit level 7 */ +#define SR_IBIT6 0x00002000 /* bit level 6 */ +#define SR_IBIT5 0x00001000 /* bit level 5 */ +#define SR_IBIT4 0x00000800 /* bit level 4 */ +#define SR_IBIT3 0x00000400 /* bit level 3 */ +#define SR_IBIT2 0x00000200 /* bit level 2 */ +#define SR_IBIT1 0x00000100 /* bit level 1 */ + +#define SR_KSMASK 0x00000018 /* Kernel mode mask */ +#define SR_KSUSER 0x00000010 /* User mode */ +#define SR_KSSUPER 0x00000008 /* Supervisor mode */ +#define SR_KSKERNEL 0x00000000 /* Kernel mode */ +#define SR_ERL 0x00000004 /* Error level */ +#define SR_EXL 0x00000002 /* Exception level */ +#define SR_IE 0x00000001 /* Interrupts enabled */ +#endif + +#if __mips == 32 +#define SR_CUMASK 0xf0000000 /* coproc usable bits */ +#define SR_CU3 0x80000000 /* Coprocessor 3 usable */ +#define SR_CU2 0x40000000 /* Coprocessor 2 usable */ +#define SR_CU1 0x20000000 /* Coprocessor 1 usable */ +#define SR_CU0 0x10000000 /* Coprocessor 0 usable */ + +#define SR_RP 0x08000000 /* Reduced power operation */ +#define SR_FR 0x04000000 /* Additional floating point registers */ +#define SR_RE 0x02000000 /* Reverse endian in user mode */ + +#define SR_BEV 0x00400000 /* Use boot exception vectors */ +#define SR_TS 0x00200000 /* TLB shutdown */ +#define SR_SR 0x00100000 /* Soft reset */ +#define SR_CH 0x00040000 /* Cache hit */ +#define SR_CE 0x00020000 /* Use cache ECC */ +#define SR_DE 0x00010000 /* Disable cache exceptions */ + +/* +** status register interrupt masks and bits +*/ + +#define SR_IMASK 0x0000ff00 /* Interrupt mask */ +#define SR_IMASK8 0x00000000 /* mask level 8 */ +#define SR_IMASK7 0x00008000 /* mask level 7 */ +#define SR_IMASK6 0x0000c000 /* mask level 6 */ +#define SR_IMASK5 0x0000e000 /* mask level 5 */ +#define SR_IMASK4 0x0000f000 /* mask level 4 */ +#define SR_IMASK3 0x0000f800 /* mask level 3 */ +#define SR_IMASK2 0x0000fc00 /* mask level 2 */ +#define SR_IMASK1 0x0000fe00 /* mask level 1 */ +#define SR_IMASK0 0x0000ff00 /* mask level 0 */ + +#define SR_IMASKSHIFT 8 + +#define SR_IBIT8 0x00008000 /* bit level 8 */ +#define SR_IBIT7 0x00004000 /* bit level 7 */ +#define SR_IBIT6 0x00002000 /* bit level 6 */ +#define SR_IBIT5 0x00001000 /* bit level 5 */ +#define SR_IBIT4 0x00000800 /* bit level 4 */ +#define SR_IBIT3 0x00000400 /* bit level 3 */ +#define SR_IBIT2 0x00000200 /* bit level 2 */ +#define SR_IBIT1 0x00000100 /* bit level 1 */ + +#define SR_KSMASK 0x00000018 /* Kernel mode mask */ +#define SR_KSUSER 0x00000010 /* User mode */ +#define SR_KSSUPER 0x00000008 /* Supervisor mode */ +#define SR_KSKERNEL 0x00000000 /* Kernel mode */ +#define SR_ERL 0x00000004 /* Error level */ +#define SR_EXL 0x00000002 /* Exception level */ +#define SR_IE 0x00000001 /* Interrupts enabled */ +#endif + +/* + * Cause Register + */ +#define CAUSE_BD 0x80000000 /* Branch delay slot */ +#define CAUSE_BT 0x40000000 /* Branch Taken */ +#define CAUSE_CEMASK 0x30000000 /* coprocessor error */ +#define CAUSE_CESHIFT 28 + + +#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */ +#define CAUSE_IPSHIFT 8 + +#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */ +#define CAUSE_EXCSHIFT 2 + +#ifndef XDS +/* +** Coprocessor 0 registers +*/ +#define C0_INX $0 /* tlb index */ +#define C0_RAND $1 /* tlb random */ +#if __mips == 1 +#define C0_TLBLO $2 /* tlb entry low */ +#endif +#if __mips == 3 +#define C0_TLBLO0 $2 /* tlb entry low 0 */ +#define C0_TLBLO1 $3 /* tlb entry low 1 */ +#endif + +#if __mips == 32 +#define C0_TLBLO0 $2 /* tlb entry low 0 */ +#define C0_TLBLO1 $3 /* tlb entry low 1 */ +#endif + + +#define C0_CTXT $4 /* tlb context */ + +#if __mips == 3 +#define C0_PAGEMASK $5 /* tlb page mask */ +#define C0_WIRED $6 /* number of wired tlb entries */ +#endif + +#if __mips == 32 +#define C0_PAGEMASK $5 /* tlb page mask */ +#define C0_WIRED $6 /* number of wired tlb entries */ +#endif + +#if __mips == 1 +#define C0_TAR $6 +#endif + +#define C0_BADVADDR $8 /* bad virtual address */ + +#if __mips == 3 +#define C0_COUNT $9 /* cycle count */ +#endif +#if __mips == 32 +#define C0_COUNT $9 /* cycle count */ +#endif + +#define C0_TLBHI $10 /* tlb entry hi */ + +#if __mips == 3 +#define C0_COMPARE $11 /* cyccle count comparator */ +#endif + +#if __mips == 32 +#define C0_COMPARE $11 /* cyccle count comparator */ +#endif + +#define C0_SR $12 /* status register */ +#define C0_CAUSE $13 /* exception cause */ +#define C0_EPC $14 /* exception pc */ +#define C0_PRID $15 /* revision identifier */ + +#if __mips == 1 +#define C0_CONFIG $3 /* configuration register R3081*/ +#endif + +#if __mips == 3 +#define C0_CONFIG $16 /* configuration register */ +#define C0_LLADDR $17 /* linked load address */ +#define C0_WATCHLO $18 /* watchpoint trap register */ +#define C0_WATCHHI $19 /* watchpoint trap register */ +#define C0_XCTXT $20 /* extended tlb context */ +#define C0_ECC $26 /* secondary cache ECC control */ +#define C0_CACHEERR $27 /* cache error status */ +#define C0_TAGLO $28 /* cache tag lo */ +#define C0_TAGHI $29 /* cache tag hi */ +#define C0_ERRPC $30 /* cache error pc */ +#endif + +#if __mips == 32 +#define C0_CONFIG $16 /* configuration register */ +#define C0_LLADDR $17 /* linked load address */ +#define C0_WATCHLO $18 /* watchpoint trap register */ +#define C0_WATCHHI $19 /* watchpoint trap register */ +#define C0_XCTXT $20 /* extended tlb context */ +#define C0_ECC $26 /* secondary cache ECC control */ +#define C0_CACHEERR $27 /* cache error status */ +#define C0_TAGLO $28 /* cache tag lo */ +#define C0_TAGHI $29 /* cache tag hi */ +#define C0_ERRPC $30 /* cache error pc */ +#endif + + +#define C1_REVISION $0 +#define C1_STATUS $31 + +#endif /* XDS */ + +#ifdef R4650 +#define IWATCH $18 +#define DWATCH $19 +#define IBASE $0 +#define IBOUND $1 +#define DBASE $2 +#define DBOUND $3 +#define CALG $17 +#endif + +#endif /* _RTEMS_MIPS_IDTCPU_H */ + diff --git a/cpukit/score/cpu/mips/rtems/mips/iregdef.h b/cpukit/score/cpu/mips/rtems/mips/iregdef.h new file mode 100644 index 0000000000..0891c3b825 --- /dev/null +++ b/cpukit/score/cpu/mips/rtems/mips/iregdef.h @@ -0,0 +1,332 @@ +/* + +Based upon IDT provided code with the following release: + +This source code has been made available to you by IDT on an AS-IS +basis. Anyone receiving this source is licensed under IDT copyrights +to use it in any way he or she deems fit, including copying it, +modifying it, compiling it, and redistributing it either with or +without modifications. No license under IDT patents or patent +applications is to be implied by the copyright license. + +Any user of this software should understand that IDT cannot provide +technical support for this software and will not be responsible for +any consequences resulting from the use of this software. + +Any person who transfers this source code or any derivative work must +include the IDT copyright notice, this paragraph, and the preceeding +two paragraphs in the transferred software. + +COPYRIGHT IDT CORPORATION 1996 +LICENSED MATERIAL - PROGRAM PROPERTY OF IDT + + $Id$ +*/ + +/* +** iregdef.h - IDT R3000 register structure header file +** +** Copyright 1989 Integrated Device Technology, Inc +** All Rights Reserved +** +*/ +#ifndef _RTEMS_MIPS_IREGDEF_H +#define _RTEMS_MIPS_IREGDEF_H + +/* + * 950313: Ketan added sreg/lreg and R_SZ for 64-bit saves + * added Register definition for XContext reg. + * Look towards end of this file. + */ +/* +** register names +*/ +#define r0 $0 +#define r1 $1 +#define r2 $2 +#define r3 $3 +#define r4 $4 +#define r5 $5 +#define r6 $6 +#define r7 $7 +#define r8 $8 +#define r9 $9 +#define r10 $10 +#define r11 $11 +#define r12 $12 +#define r13 $13 + +#define r14 $14 +#define r15 $15 +#define r16 $16 +#define r17 $17 +#define r18 $18 +#define r19 $19 +#define r20 $20 +#define r21 $21 +#define r22 $22 +#define r23 $23 +#define r24 $24 +#define r25 $25 +#define r26 $26 +#define r27 $27 +#define r28 $28 +#define r29 $29 +#define r30 $30 +#define r31 $31 + +#define fp0 $f0 +#define fp1 $f1 +#define fp2 $f2 +#define fp3 $f3 +#define fp4 $f4 +#define fp5 $f5 +#define fp6 $f6 +#define fp7 $f7 +#define fp8 $f8 +#define fp9 $f9 +#define fp10 $f10 +#define fp11 $f11 +#define fp12 $f12 +#define fp13 $f13 +#define fp14 $f14 +#define fp15 $f15 +#define fp16 $f16 +#define fp17 $f17 +#define fp18 $f18 +#define fp19 $f19 +#define fp20 $f20 +#define fp21 $f21 +#define fp22 $f22 +#define fp23 $f23 +#define fp24 $f24 +#define fp25 $f25 +#define fp26 $f26 +#define fp27 $f27 +#define fp28 $f28 +#define fp29 $f29 +#define fp30 $f30 +#define fp31 $f31 + +#define fcr0 $0 +#define fcr30 $30 +#define fcr31 $31 + +#define zero $0 /* wired zero */ +#define AT $at /* assembler temp */ +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers a0-a3 */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* caller saved t0-t9 */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 /* callee saved s0-s8 */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 /* kernel usage */ +#define k1 $27 /* kernel usage */ +#define gp $28 /* sdata pointer */ +#define sp $29 /* stack pointer */ +#define s8 $30 /* yet another saved reg for the callee */ +#define fp $30 /* frame pointer - this is being phased out by MIPS */ +#define ra $31 /* return address */ + + +/* +** relative position of registers in interrupt/exception frame +*/ +#define R_R0 0 +#define R_R1 1 +#define R_R2 2 +#define R_R3 3 +#define R_R4 4 +#define R_R5 5 +#define R_R6 6 +#define R_R7 7 +#define R_R8 8 +#define R_R9 9 +#define R_R10 10 +#define R_R11 11 +#define R_R12 12 +#define R_R13 13 +#define R_R14 14 +#define R_R15 15 +#define R_R16 16 +#define R_R17 17 +#define R_R18 18 +#define R_R19 19 +#define R_R20 20 +#define R_R21 21 +#define R_R22 22 +#define R_R23 23 +#define R_R24 24 +#define R_R25 25 +#define R_R26 26 +#define R_R27 27 +#define R_R28 28 +#define R_R29 29 +#define R_R30 30 +#define R_R31 31 + +#define R_SR 32 +#define R_MDLO 33 +#define R_MDHI 34 +#define R_BADVADDR 35 +#define R_CAUSE 36 +#define R_EPC 37 + +#define R_F0 38 +#define R_F1 39 +#define R_F2 40 +#define R_F3 41 +#define R_F4 42 +#define R_F5 43 +#define R_F6 44 +#define R_F7 45 +#define R_F8 46 +#define R_F9 47 +#define R_F10 48 +#define R_F11 49 +#define R_F12 50 +#define R_F13 41 +#define R_F14 42 +#define R_F15 43 +#define R_F16 44 +#define R_F17 45 +#define R_F18 56 +#define R_F19 57 +#define R_F20 58 +#define R_F21 59 +#define R_F22 60 +#define R_F23 61 +#define R_F24 62 +#define R_F25 63 +#define R_F26 64 +#define R_F27 65 +#define R_F28 66 +#define R_F29 67 +#define R_F30 68 +#define R_F31 69 +#define R_FCSR 70 +#define R_FEIR 71 +#define R_TLBHI 72 + +#if __mips == 1 +#define R_TLBLO 73 +#endif +#if (__mips == 3 ) || ( __mips == 32) +#define R_TLBLO0 73 +#endif + +#define R_INX 74 +#define R_RAND 75 +#define R_CTXT 76 +#define R_EXCTYPE 77 +#define R_MODE 78 +#define R_PRID 79 +#define R_TAR 80 +#if __mips == 1 +#define NREGS 81 +#endif +#if (__mips == 3 ) || ( __mips == 32) +#define R_TLBLO1 81 +#define R_PAGEMASK 82 +#define R_WIRED 83 +#define R_COUNT 84 +#define R_COMPARE 85 +#define R_CONFIG 86 +#define R_LLADDR 87 +#define R_WATCHLO 88 +#define R_WATCHHI 89 +#define R_ECC 90 +#define R_CACHEERR 91 +#define R_TAGLO 92 +#define R_TAGHI 93 +#define R_ERRPC 94 +#define R_XCTXT 95 /* Ketan added from SIM64bit */ + +#define NREGS 96 +#endif + +/* +** For those who like to think in terms of the compiler names for the regs +*/ +#define R_ZERO R_R0 +#define R_AT R_R1 +#define R_V0 R_R2 +#define R_V1 R_R3 +#define R_A0 R_R4 +#define R_A1 R_R5 +#define R_A2 R_R6 +#define R_A3 R_R7 +#define R_T0 R_R8 +#define R_T1 R_R9 +#define R_T2 R_R10 +#define R_T3 R_R11 +#define R_T4 R_R12 +#define R_T5 R_R13 +#define R_T6 R_R14 +#define R_T7 R_R15 +#define R_S0 R_R16 +#define R_S1 R_R17 +#define R_S2 R_R18 +#define R_S3 R_R19 +#define R_S4 R_R20 +#define R_S5 R_R21 +#define R_S6 R_R22 +#define R_S7 R_R23 +#define R_T8 R_R24 +#define R_T9 R_R25 +#define R_K0 R_R26 +#define R_K1 R_R27 +#define R_GP R_R28 +#define R_SP R_R29 +#define R_FP R_R30 +#define R_RA R_R31 + +/* disabled for RTEMS */ +#if 0 +/* Ketan added the following */ +#if __mips == 1 +#define sreg sw +#define lreg lw +#define rmfc0 mfc0 +#define rmtc0 mtc0 +#define R_SZ 4 +#endif /* __mips == 1 */ + +/* #ifdef __mips == 3 */ +#if __mips < 3 +#define sreg sw +#define lreg lw +#define rmfc0 mfc0 +#define rmtc0 mtc0 +#define R_SZ 4 +#else +#define sreg sd +#define lreg ld +#define rmfc0 dmfc0 +#define rmtc0 dmtc0 +#define R_SZ 8 +#endif +/* #endif __mips == 3 */ +/* Ketan till here */ +#endif + +#endif /* _RTEMS_MIPS_IREGDEF_H */ + diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h new file mode 100644 index 0000000000..8d94aba5f6 --- /dev/null +++ b/cpukit/score/cpu/mips/rtems/score/cpu.h @@ -0,0 +1,1156 @@ +/* + * Mips CPU Dependent Header File + * + * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and + * Joel Sherrill <joel@OARcorp.com>. + * + * These changes made the code conditional on standard cpp predefines, + * merged the mips1 and mips3 code sequences as much as possible, + * and moved some of the assembly code to C. Alan did much of the + * initial analysis and rework. Joel took over from there and + * wrote the JMR3904 BSP so this could be tested. Joel also + * added the new interrupt vectoring support in libcpu and + * tried to better support the various interrupt controllers. + * + * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + * COPYRIGHT (c) 1989-2006. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rtems/score/types.h> +#include <rtems/score/mips.h> + +/* conditional compilation parameters */ + +/* + * Should the calls to _Thread_Enable_dispatch be inlined? + * + * If TRUE, then they are inlined. + * If FALSE, then a subroutine call is made. + * + * Basically this is an example of the classic trade-off of size + * versus speed. Inlining the call (TRUE) typically increases the + * size of RTEMS while speeding up the enabling of dispatching. + * [NOTE: In general, the _Thread_Dispatch_disable_level will + * only be 0 or 1 unless you are in an interrupt handler and that + * interrupt handler invokes the executive.] When not inlined + * something calls _Thread_Enable_dispatch which in turns calls + * _Thread_Dispatch. If the enable dispatch is inlined, then + * one subroutine call is avoided entirely.] + */ + +#define CPU_INLINE_ENABLE_DISPATCH FALSE + +/* + * Should the body of the search loops in _Thread_queue_Enqueue_priority + * be unrolled one time? In unrolled each iteration of the loop examines + * two "nodes" on the chain being searched. Otherwise, only one node + * is examined per iteration. + * + * If TRUE, then the loops are unrolled. + * If FALSE, then the loops are not unrolled. + * + * The primary factor in making this decision is the cost of disabling + * and enabling interrupts (_ISR_Flash) versus the cost of rest of the + * body of the loop. On some CPUs, the flash is more expensive than + * one iteration of the loop body. In this case, it might be desirable + * to unroll the loop. It is important to note that on some CPUs, this + * code is the longest interrupt disable period in RTEMS. So it is + * necessary to strike a balance when setting this parameter. + */ + +#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE + +/* + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + */ + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE + +/* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * MIPS Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/* + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + */ + +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/* + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + * + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. + */ + +#define CPU_ALLOCATE_INTERRUPT_STACK FALSE + +/* + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + * + */ + +#define CPU_ISR_PASSES_FRAME_POINTER 1 + + + +/* + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * If there is a FP coprocessor such as the i387 or mc68881, then + * the answer is TRUE. + * + * The macro name "MIPS_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + */ + +#if ( MIPS_HAS_FPU == 1 ) +#define CPU_HARDWARE_FP TRUE +#else +#define CPU_HARDWARE_FP FALSE +#endif + +/* + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * So far, the only CPU in which this option has been used is the + * HP PA-RISC. The HP C compiler and gcc both implicitly use the + * floating point registers to perform integer multiplies. If + * a function which you would not think utilize the FP unit DOES, + * then one can not easily predict which tasks will use the FP hardware. + * In this case, this option should be TRUE. + * + * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + */ + +#define CPU_ALL_TASKS_ARE_FP FALSE + +/* + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + */ + +#define CPU_IDLE_TASK_IS_FP FALSE + +/* + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + */ + +#define CPU_USE_DEFERRED_FP_SWITCH TRUE + +/* + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body + * must be provided and is the default IDLE thread body instead of + * _Internal_threads_Idle_thread_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * 1. BSP provided + * 2. CPU dependent (if provided) + * 3. generic (if no BSP and no CPU dependent) + */ + +/* we can use the low power wait instruction for the IDLE thread */ +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE + +/* + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + */ + +/* our stack grows down */ +#define CPU_STACK_GROWS_UP FALSE + +/* + * The following is the variable attribute used to force alignment + * of critical RTEMS structures. On some processors it may make + * sense to have these aligned on tighter boundaries than + * the minimum requirements of the compiler in order to have as + * much of the critical data area as possible in a cache line. + * + * The placement of this macro in the declaration of the variables + * is based on the syntactically requirements of the GNU C + * "__attribute__" extension. For example with GNU C, use + * the following to force a structures to a 32 byte boundary. + * + * __attribute__ ((aligned (32))) + * + * NOTE: Currently only the Priority Bit Map table uses this feature. + * To benefit from using this, the data must be heavily + * used so it will stay in the cache and used frequently enough + * in the executive to justify turning this on. + */ + +/* our cache line size is 16 bytes */ +#if __GNUC__ +#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) +#else +#define CPU_STRUCTURE_ALIGNMENT +#endif + +/* + * Define what is required to specify how the network to host conversion + * routines are handled. + */ + +/* __MIPSEB__ or __MIPSEL__ is defined by GCC based on -EB or -EL command line options */ +#if defined(__MIPSEB__) +#define CPU_BIG_ENDIAN TRUE +#define CPU_LITTLE_ENDIAN FALSE +#elif defined(__MIPSEL__) +#define CPU_BIG_ENDIAN FALSE +#define CPU_LITTLE_ENDIAN TRUE +#else +#error "Unknown endianness" +#endif + +/* + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). + */ + +#define CPU_MODES_INTERRUPT_MASK 0x000000ff + +/* + * Processor defined structures + * + * Examples structures include the descriptor tables from the i386 + * and the processor control structure on the i960ca. + */ + +/* may need to put some structures here. */ + +/* + * Contexts + * + * Generally there are 2 types of context to save. + * 1. Interrupt registers to save + * 2. Task level registers to save + * + * This means we have the following 3 context items: + * 1. task level context stuff:: Context_Control + * 2. floating point task stuff:: Context_Control_fp + * 3. special interrupt level context :: Context_Control_interrupt + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + */ + +#ifndef ASM + +/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */ +#if (__mips == 1) || (__mips == 32) +#define __MIPS_REGISTER_TYPE uint32_t +#define __MIPS_FPU_REGISTER_TYPE uint32_t +#elif __mips == 3 +#define __MIPS_REGISTER_TYPE uint64_t +#define __MIPS_FPU_REGISTER_TYPE uint64_t +#else +#error "mips register size: unknown architecture level!!" +#endif +typedef struct { + __MIPS_REGISTER_TYPE s0; + __MIPS_REGISTER_TYPE s1; + __MIPS_REGISTER_TYPE s2; + __MIPS_REGISTER_TYPE s3; + __MIPS_REGISTER_TYPE s4; + __MIPS_REGISTER_TYPE s5; + __MIPS_REGISTER_TYPE s6; + __MIPS_REGISTER_TYPE s7; + __MIPS_REGISTER_TYPE sp; + __MIPS_REGISTER_TYPE fp; + __MIPS_REGISTER_TYPE ra; + __MIPS_REGISTER_TYPE c0_sr; + __MIPS_REGISTER_TYPE c0_epc; +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (uintptr_t) (_context)->sp + +/* WARNING: If this structure is modified, the constants in cpu.h + * must also be updated. + */ + +typedef struct { +#if ( CPU_HARDWARE_FP == TRUE ) + __MIPS_FPU_REGISTER_TYPE fp0; + __MIPS_FPU_REGISTER_TYPE fp1; + __MIPS_FPU_REGISTER_TYPE fp2; + __MIPS_FPU_REGISTER_TYPE fp3; + __MIPS_FPU_REGISTER_TYPE fp4; + __MIPS_FPU_REGISTER_TYPE fp5; + __MIPS_FPU_REGISTER_TYPE fp6; + __MIPS_FPU_REGISTER_TYPE fp7; + __MIPS_FPU_REGISTER_TYPE fp8; + __MIPS_FPU_REGISTER_TYPE fp9; + __MIPS_FPU_REGISTER_TYPE fp10; + __MIPS_FPU_REGISTER_TYPE fp11; + __MIPS_FPU_REGISTER_TYPE fp12; + __MIPS_FPU_REGISTER_TYPE fp13; + __MIPS_FPU_REGISTER_TYPE fp14; + __MIPS_FPU_REGISTER_TYPE fp15; + __MIPS_FPU_REGISTER_TYPE fp16; + __MIPS_FPU_REGISTER_TYPE fp17; + __MIPS_FPU_REGISTER_TYPE fp18; + __MIPS_FPU_REGISTER_TYPE fp19; + __MIPS_FPU_REGISTER_TYPE fp20; + __MIPS_FPU_REGISTER_TYPE fp21; + __MIPS_FPU_REGISTER_TYPE fp22; + __MIPS_FPU_REGISTER_TYPE fp23; + __MIPS_FPU_REGISTER_TYPE fp24; + __MIPS_FPU_REGISTER_TYPE fp25; + __MIPS_FPU_REGISTER_TYPE fp26; + __MIPS_FPU_REGISTER_TYPE fp27; + __MIPS_FPU_REGISTER_TYPE fp28; + __MIPS_FPU_REGISTER_TYPE fp29; + __MIPS_FPU_REGISTER_TYPE fp30; + __MIPS_FPU_REGISTER_TYPE fp31; + uint32_t fpcs; +#endif +} Context_Control_fp; + +/* + * This struct reflects the stack frame employed in ISR_Handler. Note + * that the ISR routine save some of the registers to this frame for + * all interrupts and exceptions. Other registers are saved only on + * exceptions, while others are not touched at all. The untouched + * registers are not normally disturbed by high-level language + * programs so they can be accessed when required. + * + * The registers and their ordering in this struct must directly + * correspond to the layout and ordering of * shown in iregdef.h, + * as cpu_asm.S uses those definitions to fill the stack frame. + * This struct provides access to the stack frame for C code. + * + * Similarly, this structure is used by debugger stubs and exception + * processing routines so be careful when changing the format. + * + * NOTE: The comments with this structure and cpu_asm.S should be kept + * in sync. When in doubt, look in the code to see if the + * registers you're interested in are actually treated as expected. + * The order of the first portion of this structure follows the + * order of registers expected by gdb. + */ + +typedef struct +{ + __MIPS_REGISTER_TYPE r0; /* 0 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE at; /* 1 -- saved always */ + __MIPS_REGISTER_TYPE v0; /* 2 -- saved always */ + __MIPS_REGISTER_TYPE v1; /* 3 -- saved always */ + __MIPS_REGISTER_TYPE a0; /* 4 -- saved always */ + __MIPS_REGISTER_TYPE a1; /* 5 -- saved always */ + __MIPS_REGISTER_TYPE a2; /* 6 -- saved always */ + __MIPS_REGISTER_TYPE a3; /* 7 -- saved always */ + __MIPS_REGISTER_TYPE t0; /* 8 -- saved always */ + __MIPS_REGISTER_TYPE t1; /* 9 -- saved always */ + __MIPS_REGISTER_TYPE t2; /* 10 -- saved always */ + __MIPS_REGISTER_TYPE t3; /* 11 -- saved always */ + __MIPS_REGISTER_TYPE t4; /* 12 -- saved always */ + __MIPS_REGISTER_TYPE t5; /* 13 -- saved always */ + __MIPS_REGISTER_TYPE t6; /* 14 -- saved always */ + __MIPS_REGISTER_TYPE t7; /* 15 -- saved always */ + __MIPS_REGISTER_TYPE s0; /* 16 -- saved on exceptions */ + __MIPS_REGISTER_TYPE s1; /* 17 -- saved on exceptions */ + __MIPS_REGISTER_TYPE s2; /* 18 -- saved on exceptions */ + __MIPS_REGISTER_TYPE s3; /* 19 -- saved on exceptions */ + __MIPS_REGISTER_TYPE s4; /* 20 -- saved on exceptions */ + __MIPS_REGISTER_TYPE s5; /* 21 -- saved on exceptions */ + __MIPS_REGISTER_TYPE s6; /* 22 -- saved on exceptions */ + __MIPS_REGISTER_TYPE s7; /* 23 -- saved on exceptions */ + __MIPS_REGISTER_TYPE t8; /* 24 -- saved always */ + __MIPS_REGISTER_TYPE t9; /* 25 -- saved always */ + __MIPS_REGISTER_TYPE k0; /* 26 -- NOT FILLED IN, kernel tmp reg */ + __MIPS_REGISTER_TYPE k1; /* 27 -- NOT FILLED IN, kernel tmp reg */ + __MIPS_REGISTER_TYPE gp; /* 28 -- saved always */ + __MIPS_REGISTER_TYPE sp; /* 29 -- saved on exceptions NOT RESTORED */ + __MIPS_REGISTER_TYPE fp; /* 30 -- saved always */ + __MIPS_REGISTER_TYPE ra; /* 31 -- saved always */ + __MIPS_REGISTER_TYPE c0_sr; /* 32 -- saved always, some bits are */ + /* manipulated per-thread */ + __MIPS_REGISTER_TYPE mdlo; /* 33 -- saved always */ + __MIPS_REGISTER_TYPE mdhi; /* 34 -- saved always */ + __MIPS_REGISTER_TYPE badvaddr; /* 35 -- saved on exceptions, read-only */ + __MIPS_REGISTER_TYPE cause; /* 36 -- saved on exceptions NOT restored */ + __MIPS_REGISTER_TYPE epc; /* 37 -- saved always, read-only register */ + /* but logically restored */ + __MIPS_FPU_REGISTER_TYPE f0; /* 38 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f1; /* 39 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f2; /* 40 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f3; /* 41 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f4; /* 42 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f5; /* 43 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f6; /* 44 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f7; /* 45 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f8; /* 46 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f9; /* 47 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f10; /* 48 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f11; /* 49 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f12; /* 50 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f13; /* 51 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f14; /* 52 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f15; /* 53 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f16; /* 54 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f17; /* 55 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f18; /* 56 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f19; /* 57 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f20; /* 58 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f21; /* 59 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f22; /* 60 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f23; /* 61 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f24; /* 62 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f25; /* 63 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f26; /* 64 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f27; /* 65 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f28; /* 66 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f29; /* 67 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f30; /* 68 -- saved if FP enabled */ + __MIPS_FPU_REGISTER_TYPE f31; /* 69 -- saved if FP enabled */ + __MIPS_REGISTER_TYPE fcsr; /* 70 -- saved on exceptions */ + /* (oddly not documented on MGV) */ + __MIPS_REGISTER_TYPE feir; /* 71 -- saved on exceptions */ + /* (oddly not documented on MGV) */ + + /* GDB does not seem to care about anything past this point */ + + __MIPS_REGISTER_TYPE tlbhi; /* 72 - NOT FILLED IN, doesn't exist on */ + /* all MIPS CPUs (at least MGV) */ +#if __mips == 1 + __MIPS_REGISTER_TYPE tlblo; /* 73 - NOT FILLED IN, doesn't exist on */ + /* all MIPS CPUs (at least MGV) */ +#endif +#if (__mips == 3) || (__mips == 32) + __MIPS_REGISTER_TYPE tlblo0; /* 73 - NOT FILLED IN, doesn't exist on */ + /* all MIPS CPUs (at least MGV) */ +#endif + + __MIPS_REGISTER_TYPE inx; /* 74 -- NOT FILLED IN, doesn't exist on */ + /* all MIPS CPUs (at least MGV) */ + __MIPS_REGISTER_TYPE rand; /* 75 -- NOT FILLED IN, doesn't exist on */ + /* all MIPS CPUs (at least MGV) */ + __MIPS_REGISTER_TYPE ctxt; /* 76 -- NOT FILLED IN, doesn't exist on */ + /* all MIPS CPUs (at least MGV) */ + __MIPS_REGISTER_TYPE exctype; /* 77 -- NOT FILLED IN (not enough info) */ + __MIPS_REGISTER_TYPE mode; /* 78 -- NOT FILLED IN (not enough info) */ + __MIPS_REGISTER_TYPE prid; /* 79 -- NOT FILLED IN (not need to do so) */ + __MIPS_REGISTER_TYPE tar ; /* 80 -- target address register, filled on exceptions */ + /* end of __mips == 1 so NREGS == 81 */ +#if (__mips == 3) || (__mips == 32) + __MIPS_REGISTER_TYPE tlblo1; /* 81 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE pagemask; /* 82 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE wired; /* 83 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE count; /* 84 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE compare; /* 85 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE config; /* 86 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE lladdr; /* 87 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE watchlo; /* 88 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE watchhi; /* 89 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE ecc; /* 90 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE cacheerr; /* 91 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE taglo; /* 92 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE taghi; /* 93 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE errpc; /* 94 -- NOT FILLED IN */ + __MIPS_REGISTER_TYPE xctxt; /* 95 -- NOT FILLED IN */ + /* end of __mips == 3 so NREGS == 96 */ +#endif + +} CPU_Interrupt_frame; + +/* + * This variable is optional. It is used on CPUs on which it is difficult + * to generate an "uninitialized" FP context. It is filled in by + * _CPU_Initialize and copied into the task's FP context area during + * _CPU_Context_Initialize. + */ + +SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; + +/* + * Nothing prevents the porter from declaring more CPU specific variables. + */ + +/* XXX: if needed, put more variables here */ + +/* + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + */ + +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +/* + * Amount of extra stack (above minimum stack size) required by + * system initialization thread. Remember that in a multiprocessor + * system the system intialization thread becomes the MP server thread. + */ + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/* + * This defines the number of entries in the ISR_Vector_table managed + * by RTEMS. + */ + +extern unsigned int mips_interrupt_number_of_vectors; +#define CPU_INTERRUPT_NUMBER_OF_VECTORS (mips_interrupt_number_of_vectors) +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) + +/* + * Should be large enough to run all RTEMS tests. This ensures + * that a "reasonable" small application should not have any problems. + */ + +#define CPU_STACK_MINIMUM_SIZE (8 * 1024) + +/* + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + */ + +#define CPU_ALIGNMENT 8 + +/* + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, + * then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict + * enough for the partition, then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT + * is strict enough for the stack, then this should be set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. + */ + +#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT + +/* + * ISR handler macros + */ + +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + */ + +#define _CPU_Initialize_vectors() + +/* + * Declare the function that is present in the shared libcpu directory, + * that returns the processor dependent interrupt mask. + */ + +uint32_t mips_interrupt_mask( void ); + +/* + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in _level. + */ + +#define _CPU_ISR_Disable( _level ) \ + do { \ + unsigned int _scratch; \ + mips_get_sr( _scratch ); \ + mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \ + _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \ + } while(0) + +/* + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * _level is not modified. + */ + +#define _CPU_ISR_Enable( _level ) \ + do { \ + unsigned int _scratch; \ + mips_get_sr( _scratch ); \ + mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \ + } while(0) + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _level is not + * modified. + */ + +#define _CPU_ISR_Flash( _xlevel ) \ + do { \ + unsigned int _scratch2 = _xlevel; \ + _CPU_ISR_Enable( _scratch2 ); \ + _CPU_ISR_Disable( _scratch2 ); \ + _xlevel = _scratch2; \ + } while(0) + +/* + * Map interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + * This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + * + * On the MIPS, 0 is all on. Non-zero is all off. This only + * manipulates the IEC. + */ + +uint32_t _CPU_ISR_Get_level( void ); /* in cpu.c */ + +void _CPU_ISR_Set_level( uint32_t ); /* in cpu.c */ + +/* end of ISR handler macros */ + +/* Context handler macros */ + +/* + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * NOTE: This is_fp parameter is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + * + * The per-thread status register holds the interrupt enable, FP enable + * and global interrupt enable for that thread. It means each thread can + * enable its own set of interrupts. If interrupts are disabled, RTEMS + * can still dispatch via blocking calls. This is the function of the + * "Interrupt Level", and on the MIPS, it controls the IEC bit and all + * the hardware interrupts as defined in the SR. Software ints + * are automatically enabled for all threads, as they will only occur under + * program control anyhow. Besides, the interrupt level parm is only 8 bits, + * and controlling the software ints plus the others would require 9. + * + * If the Interrupt Level is 0, all ints are on. Otherwise, the + * Interrupt Level should supply a bit pattern to impose on the SR + * interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6 + * apply to the SR register Intr bits from bit 10 thru bit 15. Bit 7 of + * the Interrupt Level parameter is unused at this time. + * + * These are the only per-thread SR bits, the others are maintained + * globally & explicitly preserved by the Context Switch code in cpu_asm.s + */ + + +#if (__mips == 3) || (__mips == 32) +#define _INTON SR_IE +#if __mips_fpr==64 +#define _EXTRABITS SR_FR +#else +#define _EXTRABITS 0 +#endif /* __mips_fpr==64 */ +#endif /* __mips == 3 */ +#if __mips == 1 +#define _INTON SR_IEC +#define _EXTRABITS 0 /* make sure we're in user mode on MIPS1 processors */ +#endif /* __mips == 1 */ + + +void _CPU_Context_Initialize( + Context_Control *the_context, + uintptr_t *stack_base, + uint32_t size, + uint32_t new_level, + void *entry_point, + bool is_fp +); + + +/* + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. Context_Restore should work most of the time. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + */ + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/* + * The purpose of this macro is to allow the initial pointer into + * A floating point context area (used to save the floating point + * context) to be at an arbitrary place in the floating point + * context area. + * + * This is necessary because some FP units are designed to have + * their context saved as a stack which grows into lower addresses. + * Other FP units can be saved by simply moving registers into offsets + * from the base of the context area. Finally some FP units provide + * a "dump context" instruction which could fill in from high to low + * or low to high based on the whim of the CPU designers. + */ + +#define _CPU_Context_Fp_start( _base, _offset ) \ + ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) + +/* + * This routine initializes the FP context area passed to it to. + * There are a few standard ways in which to initialize the + * floating point context. The code included for this macro assumes + * that this is a CPU in which a "initial" FP context was saved into + * _CPU_Null_fp_context and it simply copies it to the destination + * context passed to it. + * + * Other models include (1) not doing anything, and (2) putting + * a "null FP status word" in the correct place in the FP context. + */ + +#if ( CPU_HARDWARE_FP == TRUE ) +#define _CPU_Context_Initialize_fp( _destination ) \ + { \ + *(*(_destination)) = _CPU_Null_fp_context; \ + } +#endif + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/* + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + */ + +#define _CPU_Fatal_halt( _error ) \ + do { \ + unsigned int _level; \ + _CPU_ISR_Disable(_level); \ + loop: goto loop; \ + } while (0) + + +extern void mips_break( int error ); + +/* Bitfield handler macros */ + +/* + * This routine sets _output to the bit number of the first bit + * set in _value. _value is of CPU dependent type Priority_bit_map_Control. + * This type may be either 16 or 32 bits wide although only the 16 + * least significant bits will be used. + * + * There are a number of variables in using a "find first bit" type + * instruction. + * + * (1) What happens when run on a value of zero? + * (2) Bits may be numbered from MSB to LSB or vice-versa. + * (3) The numbering may be zero or one based. + * (4) The "find first bit" instruction may search from MSB or LSB. + * + * RTEMS guarantees that (1) will never happen so it is not a concern. + * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and + * _CPU_Priority_bits_index(). These three form a set of routines + * which must logically operate together. Bits in the _value are + * set and cleared based on masks built by _CPU_Priority_mask(). + * The basic major and minor values calculated by _Priority_Major() + * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() + * to properly range between the values returned by the "find first bit" + * instruction. This makes it possible for _Priority_Get_highest() to + * calculate the major and directly index into the minor table. + * This mapping is necessary to ensure that 0 (a high priority major/minor) + * is the first bit found. + * + * This entire "find first bit" and mapping process depends heavily + * on the manner in which a priority is broken into a major and minor + * components with the major being the 4 MSB of a priority and minor + * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest + * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next + * to the lowest priority. + * + * If your CPU does not have a "find first bit" instruction, then + * there are ways to make do without it. Here are a handful of ways + * to implement this in software: + * + * - a series of 16 bit test instructions + * - a "binary search using if's" + * - _number = 0 + * if _value > 0x00ff + * _value >>=8 + * _number = 8; + * + * if _value > 0x0000f + * _value >=8 + * _number += 4 + * + * _number += bit_set_table[ _value ] + * + * where bit_set_table[ 16 ] has values which indicate the first + * bit set + */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE +#define CPU_USE_GENERIC_BITFIELD_DATA TRUE + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + { \ + (_output) = 0; /* do something to prevent warnings */ \ + } + +#endif + +/* end of Bitfield handler macros */ + +/* + * This routine builds the mask which corresponds to the bit fields + * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion + * for that routine. + */ + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Priority_Mask( _bit_number ) \ + ( 1 << (_bit_number) ) + +#endif + +/* + * This routine translates the bit numbers returned by + * _CPU_Bitfield_Find_first_bit() into something suitable for use as + * a major or minor component of a priority. See the discussion + * for that routine. + */ + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Priority_bits_index( _priority ) \ + (_priority) + +#endif + +/* end of Priority handler macros */ + +/* functions */ + +/* + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + */ + +void _CPU_Initialize(void); + +/* + * _CPU_ISR_install_raw_handler + * + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + */ + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + */ + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_Install_interrupt_stack + * + * This routine installs the hardware interrupt stack pointer. + * + * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + */ + +void _CPU_Install_interrupt_stack( void ); + +/* + * _CPU_Internal_threads_Idle_thread_body + * + * This routine is the CPU dependent IDLE thread body. + * + * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + */ + +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + */ + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/* + * _CPU_Context_restore + * + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + * + * NOTE: May be unnecessary to reload some registers. + */ + +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; + +/* + * _CPU_Context_save_fp + * + * This routine saves the floating point context passed to it. + */ + +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); + +/* + * _CPU_Context_restore_fp + * + * This routine restores the floating point context passed to it. + */ + +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); + +/* The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to ensure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + */ + +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return( swapped ); +} + +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + + +#endif + + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/mips/rtems/score/mips.h b/cpukit/score/cpu/mips/rtems/score/mips.h new file mode 100644 index 0000000000..8c4f3ae0f4 --- /dev/null +++ b/cpukit/score/cpu/mips/rtems/score/mips.h @@ -0,0 +1,283 @@ +/** + * @file rtems/score/mips.h + */ + +/* + * COPYRIGHT (c) 1989-2001. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _RTEMS_SCORE_MIPS_H +#define _RTEMS_SCORE_MIPS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ASM +#include <rtems/mips/idtcpu.h> +#endif + +/* + * SR bits that enable/disable interrupts + * + * NOTE: XXX what about SR_ERL? + */ + +#if (__mips == 3) || (__mips == 32) +#ifdef ASM +#define SR_INTERRUPT_ENABLE_BITS 0x01 +#else +#define SR_INTERRUPT_ENABLE_BITS SR_IE +#endif + +#elif __mips == 1 +#define SR_INTERRUPT_ENABLE_BITS SR_IEC + +#else +#error "mips interrupt enable bits: unknown architecture level!" +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the "no cpu" + * family when executing in protected mode. It does + * this by setting variables to indicate which implementation + * dependent features are present in a particular member + * of the family. + */ + +#if defined(__mips_soft_float) +#define MIPS_HAS_FPU 0 +#else +#define MIPS_HAS_FPU 1 +#endif + + +#if (__mips == 1) +#define CPU_MODEL_NAME "ISA Level 1 or 2" +#elif (__mips == 3) || (__mips == 32) +#if defined(__mips64) +#define CPU_MODEL_NAME "ISA Level 4" +#else +#define CPU_MODEL_NAME "ISA Level 3" +#endif +#else +#error "Unknown MIPS ISA level" +#endif + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "MIPS" + +/* + * RTEMS Vector numbers for exception conditions. This is a direct + * map to the causes. + */ + +#define MIPS_EXCEPTION_BASE 0 + +#define MIPS_EXCEPTION_INT MIPS_EXCEPTION_BASE+0 +#define MIPS_EXCEPTION_MOD MIPS_EXCEPTION_BASE+1 +#define MIPS_EXCEPTION_TLBL MIPS_EXCEPTION_BASE+2 +#define MIPS_EXCEPTION_TLBS MIPS_EXCEPTION_BASE+3 +#define MIPS_EXCEPTION_ADEL MIPS_EXCEPTION_BASE+4 +#define MIPS_EXCEPTION_ADES MIPS_EXCEPTION_BASE+5 +#define MIPS_EXCEPTION_IBE MIPS_EXCEPTION_BASE+6 +#define MIPS_EXCEPTION_DBE MIPS_EXCEPTION_BASE+7 +#define MIPS_EXCEPTION_SYSCALL MIPS_EXCEPTION_BASE+8 +#define MIPS_EXCEPTION_BREAK MIPS_EXCEPTION_BASE+9 +#define MIPS_EXCEPTION_RI MIPS_EXCEPTION_BASE+10 +#define MIPS_EXCEPTION_CPU MIPS_EXCEPTION_BASE+11 +#define MIPS_EXCEPTION_OVERFLOW MIPS_EXCEPTION_BASE+12 +#define MIPS_EXCEPTION_TRAP MIPS_EXCEPTION_BASE+13 +#define MIPS_EXCEPTION_VCEI MIPS_EXCEPTION_BASE+14 +/* FPE only on mips2 and higher */ +#define MIPS_EXCEPTION_FPE MIPS_EXCEPTION_BASE+15 +#define MIPS_EXCEPTION_C2E MIPS_EXCEPTION_BASE+16 +/* 17-22 reserved */ +#define MIPS_EXCEPTION_WATCH MIPS_EXCEPTION_BASE+23 +/* 24-30 reserved */ +#define MIPS_EXCEPTION_VCED MIPS_EXCEPTION_BASE+31 + +#define MIPS_INTERRUPT_BASE MIPS_EXCEPTION_BASE+32 + +/* + * Some macros to access registers + */ + +#define mips_get_sr( _x ) \ + do { \ + __asm__ volatile( "mfc0 %0, $12; nop" : "=r" (_x) : ); \ + } while (0) + +#define mips_set_sr( _x ) \ + do { \ + register unsigned int __x = (_x); \ + __asm__ volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \ + } while (0) + + +/* + * Access the Cause register + */ + +#define mips_get_cause( _x ) \ + do { \ + __asm__ volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \ + } while (0) + + +#define mips_set_cause( _x ) \ + do { \ + register unsigned int __x = (_x); \ + __asm__ volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \ + } while (0) + + + + +/* + * Access the Debug Cache Invalidate Control register + */ + +#define mips_get_dcic( _x ) \ + do { \ + __asm__ volatile( "mfc0 %0, $7; nop" : "=r" (_x) : ); \ + } while (0) + + +#define mips_set_dcic( _x ) \ + do { \ + register unsigned int __x = (_x); \ + __asm__ volatile( "mtc0 %0, $7; nop" : : "r" (__x) ); \ + } while (0) + + + + +/* + * Access the Breakpoint Program Counter & Mask registers + * (_x for BPC, _y for mask) + */ + +#define mips_get_bpcrm( _x, _y ) \ + do { \ + __asm__ volatile( "mfc0 %0, $3; nop" : "=r" (_x) : ); \ + __asm__ volatile( "mfc0 %0, $11; nop" : "=r" (_y) : ); \ + } while (0) + + +#define mips_set_bpcrm( _x, _y ) \ + do { \ + register unsigned int __x = (_x); \ + register unsigned int __y = (_y); \ + __asm__ volatile( "mtc0 %0, $11; nop" : : "r" (__y) ); \ + __asm__ volatile( "mtc0 %0, $3; nop" : : "r" (__x) ); \ + } while (0) + + + + + + +/* + * Access the Breakpoint Data Address & Mask registers + * (_x for BDA, _y for mask) + */ + +#define mips_get_bdarm( _x, _y ) \ + do { \ + __asm__ volatile( "mfc0 %0, $5; nop" : "=r" (_x) : ); \ + __asm__ volatile( "mfc0 %0, $9; nop" : "=r" (_y) : ); \ + } while (0) + + +#define mips_set_bdarm( _x, _y ) \ + do { \ + register unsigned int __x = (_x); \ + register unsigned int __y = (_y); \ + __asm__ volatile( "mtc0 %0, $9; nop" : : "r" (__y) ); \ + __asm__ volatile( "mtc0 %0, $5; nop" : : "r" (__x) ); \ + } while (0) + + + + + + + +/* + * Access FCR31 + */ + +#if ( MIPS_HAS_FPU == 1 ) + +#define mips_get_fcr31( _x ) \ + do { \ + __asm__ volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \ + } while(0) + + +#define mips_set_fcr31( _x ) \ + do { \ + register unsigned int __x = (_x); \ + __asm__ volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \ + } while(0) + +#else + +#define mips_get_fcr31( _x ) +#define mips_set_fcr31( _x ) + +#endif + +/* + * Manipulate interrupt mask + * + * mips_unmask_interrupt( _mask) + * enables interrupts - mask is positioned so it only needs to be or'ed + * into the status reg. This also does some other things !!!! Caution + * should be used if invoking this while in the middle of a debugging + * session where the client may have nested interrupts. + * + * mips_mask_interrupt( _mask ) + * disable the interrupt - mask is the complement of the bits to be + * cleared - i.e. to clear ext int 5 the mask would be - 0xffff7fff + * + * + * NOTE: mips_mask_interrupt() used to be disable_int(). + * mips_unmask_interrupt() used to be enable_int(). + * + */ + +#define mips_enable_in_interrupt_mask( _mask ) \ + do { \ + unsigned int _sr; \ + mips_get_sr( _sr ); \ + _sr |= (_mask); \ + mips_set_sr( _sr ); \ + } while (0) + +#define mips_disable_in_interrupt_mask( _mask ) \ + do { \ + unsigned int _sr; \ + mips_get_sr( _sr ); \ + _sr &= ~(_mask); \ + mips_set_sr( _sr ); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_MIPS_H */ +/* end of include file */ diff --git a/cpukit/score/cpu/mips/rtems/score/types.h b/cpukit/score/cpu/mips/rtems/score/types.h new file mode 100644 index 0000000000..67b253bcf8 --- /dev/null +++ b/cpukit/score/cpu/mips/rtems/score/types.h @@ -0,0 +1,45 @@ +/** + * @file rtems/score/types.h + */ + +/* + * This include file contains type definitions pertaining to the MIPS + * processor family. + * + * COPYRIGHT (c) 1989-2001. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ +/* @(#)mipstypes.h 08/20/96 1.4 */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include <rtems/score/basedefs.h> + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +typedef uint16_t Priority_bit_map_Control; +typedef void mips_isr; +typedef void ( *mips_isr_entry )( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif |