diff options
Diffstat (limited to '')
-rw-r--r-- | cpukit/score/cpu/mips/rtems/asm.h | 26 | ||||
-rw-r--r-- | cpukit/score/cpu/mips/rtems/mips/idtcpu.h | 30 | ||||
-rw-r--r-- | cpukit/score/cpu/mips/rtems/mips/iregdef.h | 16 | ||||
-rw-r--r-- | cpukit/score/cpu/mips/rtems/score/cpu.h | 11 | ||||
-rw-r--r-- | cpukit/score/cpu/mips/rtems/score/mips.h | 45 |
5 files changed, 70 insertions, 58 deletions
diff --git a/cpukit/score/cpu/mips/rtems/asm.h b/cpukit/score/cpu/mips/rtems/asm.h index edabbe8fcc..060be295bf 100644 --- a/cpukit/score/cpu/mips/rtems/asm.h +++ b/cpukit/score/cpu/mips/rtems/asm.h @@ -24,8 +24,8 @@ */ /* @(#)asm.h 03/15/96 1.1 */ -#ifndef __MIPS64ORION_ASM_h -#define __MIPS64ORION_ASM_h +#ifndef __NO_CPU_ASM_h +#define __NO_CPU_ASM_h /* * Indicate we are in an assembly file and get the basic CPU definitions. @@ -96,7 +96,27 @@ #define PUBLIC(sym) .globl SYM (sym) #define EXTERN(sym) .globl SYM (sym) +/* + * Debugger macros for assembly language routines. Allows the + * programmer to set up the necessary stack frame info + * required by debuggers to do stack traces. + */ + +#ifndef XDS +#define FRAME(name,frm_reg,offset,ret_reg) \ + .globl name; \ + .ent name; \ +name:; \ + .frame frm_reg,offset,ret_reg +#define ENDFRAME(name) \ + .end name +#else +#define FRAME(name,frm_reg,offset,ret_reg) \ + .globl _##name;\ +_##name: +#define ENDFRAME(name) +#endif XDS + #endif /* end of include file */ - diff --git a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h index f921e85ef6..cfb2fe626a 100644 --- a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h +++ b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h @@ -45,7 +45,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define K1SIZE 0x20000000 #define K2BASE 0xc0000000 #define K2SIZE 0x20000000 -#if defined(CPU_R4000) +#if __mips == 3 #define KSBASE 0xe0000000 #define KSSIZE 0x20000000 #endif @@ -56,11 +56,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT /* ** Exception Vectors */ -#if defined(CPU_R3000) +#if __mips == 1 #define UT_VEC K0BASE /* utlbmiss vector */ #define E_VEC (K0BASE+0x80) /* exception vevtor */ #endif -#if defined(CPU_R4000) +#if __mips == 3 #define T_VEC (K0BASE+0x000) /* tlbmiss vector */ #define X_VEC (K0BASE+0x080) /* xtlbmiss vector */ #define C_VEC (K0BASE+0x100) /* cache error vector */ @@ -89,7 +89,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define MINCACHE 0x200 /* 512 For 3041. */ #define MAXCACHE 0x40000 /* 256*1024 256k */ -#if defined(CPU_R4000) +#if __mips == 3 /* R4000 configuration register definitions */ #define CFG_CM 0x80000000 /* Master-Checker mode */ #define CFG_ECMASK 0x70000000 /* System Clock Ratio */ @@ -184,7 +184,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT /* ** TLB resource defines */ -#if defined(CPU_R3000) +#if __mips == 1 #define N_TLB_ENTRIES 64 #define TLB_PGSIZE 0x1000 #define RANDBASE 8 @@ -214,7 +214,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define TLBCTXT_VPNMASK 0x001ffffc #define TLBCTXT_VPNSHIFT 2 #endif -#if defined(CPU_R4000) +#if __mips == 3 #define N_TLB_ENTRIES 48 #define TLBHI_VPN2MASK 0xffffe000 @@ -249,7 +249,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define TLBPGMASK_MASK 0x01ffe000 #endif -#if defined(CPU_R3000) +#if __mips == 1 #define SR_CUMASK 0xf0000000 /* coproc usable bits */ #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ #define SR_CU2 0x40000000 /* Coprocessor 2 usable */ @@ -300,7 +300,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */ #endif -#if defined(CPU_R4000) +#if __mips == 3 #define SR_CUMASK 0xf0000000 /* coproc usable bits */ #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ #define SR_CU2 0x40000000 /* Coprocessor 2 usable */ @@ -375,30 +375,30 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT */ #define C0_INX $0 /* tlb index */ #define C0_RAND $1 /* tlb random */ -#if defined(CPU_R3000) +#if __mips == 1 #define C0_TLBLO $2 /* tlb entry low */ #endif -#if defined(CPU_R4000) +#if __mips == 3 #define C0_TLBLO0 $2 /* tlb entry low 0 */ #define C0_TLBLO1 $3 /* tlb entry low 1 */ #endif #define C0_CTXT $4 /* tlb context */ -#if defined(CPU_R4000) +#if __mips == 3 #define C0_PAGEMASK $5 /* tlb page mask */ #define C0_WIRED $6 /* number of wired tlb entries */ #endif #define C0_BADVADDR $8 /* bad virtual address */ -#if defined(CPU_R4000) +#if __mips == 3 #define C0_COUNT $9 /* cycle count */ #endif #define C0_TLBHI $10 /* tlb entry hi */ -#if defined(CPU_R4000) +#if __mips == 3 #define C0_COMPARE $11 /* cyccle count comparator */ #endif @@ -407,11 +407,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define C0_EPC $14 /* exception pc */ #define C0_PRID $15 /* revision identifier */ -#if defined(CPU_R3000) +#if __mips == 1 #define C0_CONFIG $3 /* configuration register R3081*/ #endif -#if defined(CPU_R4000) +#if __mips == 3 #define C0_CONFIG $16 /* configuration register */ #define C0_LLADDR $17 /* linked load address */ #define C0_WATCHLO $18 /* watchpoint trap register */ diff --git a/cpukit/score/cpu/mips/rtems/mips/iregdef.h b/cpukit/score/cpu/mips/rtems/mips/iregdef.h index f0953da852..ca50207a3b 100644 --- a/cpukit/score/cpu/mips/rtems/mips/iregdef.h +++ b/cpukit/score/cpu/mips/rtems/mips/iregdef.h @@ -221,10 +221,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define R_SR 67 #define R_CAUSE 68 #define R_TLBHI 69 -#if defined(CPU_R3000) +#if __mips == 1 #define R_TLBLO 70 #endif -#if defined(CPU_R4000) +#if __mips == 3 #define R_TLBLO0 70 #endif #define R_BADVADDR 71 @@ -236,10 +236,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define R_PRID 77 #define R_FCSR 78 #define R_FEIR 79 -#if defined(CPU_R3000) +#if __mips == 1 #define NREGS 80 #endif -#if defined(CPU_R4000) +#if __mips == 3 #define R_TLBLO1 80 #define R_PAGEMASK 81 #define R_WIRED 82 @@ -296,15 +296,15 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define R_RA R_R31 /* Ketan added the following */ -#ifdef CPU_R3000 +#ifdef __mips == 1 #define sreg sw #define lreg lw #define rmfc0 mfc0 #define rmtc0 mtc0 #define R_SZ 4 -#endif CPU_R3000 +#endif /* __mips == 1 */ -#ifdef CPU_R4000 +/* #ifdef __mips == 3 */ #if __mips < 3 #define sreg sw #define lreg lw @@ -318,7 +318,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #define rmtc0 dmtc0 #define R_SZ 8 #endif -#endif CPU_R4000 +/* #endif __mips == 3 */ /* Ketan till here */ #endif /* __IREGDEF_H__ */ diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h index 35d936ec7e..7527ddecdf 100644 --- a/cpukit/score/cpu/mips/rtems/score/cpu.h +++ b/cpukit/score/cpu/mips/rtems/score/cpu.h @@ -18,7 +18,7 @@ * Transition Networks makes no representations about the suitability * of this software for any purpose. * - * Derived from source copyrighted as follows: + * Derived from c/src/exec/score/cpu/no_cpu/cpu.h: * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). @@ -93,7 +93,7 @@ extern void mips_fatal_error ( int error ); /* * Does RTEMS manage a dedicated interrupt stack in software? * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. * If FALSE, nothing is done. * * If the CPU supports a dedicated interrupt stack in hardware, @@ -162,19 +162,18 @@ extern void mips_fatal_error ( int error ); * If there is a FP coprocessor such as the i387 or mc68881, then * the answer is TRUE. * - * The macro name "MIPS64ORION_HAS_FPU" should be made CPU specific. + * The macro name "MIPS_HAS_FPU" should be made CPU specific. * It indicates whether or not this CPU model has FP support. For * example, it would be possible to have an i386_nofp CPU model * which set this to false to indicate that you have an i386 without * an i387 and wish to leave floating point support out of RTEMS. */ -#if ( MIPS64ORION_HAS_FPU == 1 ) +#if ( MIPS_HAS_FPU == 1 ) #define CPU_HARDWARE_FP TRUE #else #define CPU_HARDWARE_FP FALSE #endif -#define CPU_SOFTWARE_FP FALSE /* * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? @@ -444,7 +443,7 @@ typedef struct { */ /* - * Macros to access MIPS64ORION specific additions to the CPU Table + * Macros to access MIPS specific additions to the CPU Table */ #define rtems_cpu_configuration_get_clicks_per_microsecond() \ diff --git a/cpukit/score/cpu/mips/rtems/score/mips.h b/cpukit/score/cpu/mips/rtems/score/mips.h index 2ec96da0a4..90e959bd47 100644 --- a/cpukit/score/cpu/mips/rtems/score/mips.h +++ b/cpukit/score/cpu/mips/rtems/score/mips.h @@ -15,7 +15,7 @@ * Transition Networks makes no representations about the suitability * of this software for any purpose. * - * Derived from source copyrighted as follows: + * Derived from c/src/exec/score/cpu/no_cpu/no_cpu.h: * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). @@ -28,8 +28,8 @@ */ /* @(#)mips64orion.h 08/29/96 1.3 */ -#ifndef _INCLUDE_MIPS64ORION_h -#define _INCLUDE_MIPS64ORION_h +#ifndef _INCLUDE_MIPS_h +#define _INCLUDE_MIPS_h #ifdef __cplusplus extern "C" { @@ -44,40 +44,33 @@ extern "C" { * of the family. */ -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" -#define MIPS64ORION_HAS_FPU 1 - -#elif defined(R4650) - -#define CPU_MODEL_NAME "R4650" -#define MIPS64ORION_HAS_FPU 1 - -#elif defined(R4600) - -#define CPU_MODEL_NAME "R4600" -#define MIPS64ORION_HAS_FPU 1 +#if defined(__mips_soft_float) +#define MIPS_HAS_FPU 0 +#else +#define MIPS_HAS_FPU 1 +#endif +#if (__mips == 1) +#define CPU_MODEL_NAME "ISA Level 1 or 2" +#elif (__mips == 3) +#if defined(__mips64) +#define CPU_MODEL_NAME "ISA Level 4" #else - -#error "Unsupported CPU Model" - +#define CPU_MODEL_NAME "ISA Level 3" +#endif +#else +#error "Unknown MIPS ISA level" #endif /* * Define the name of the CPU family. */ -#define CPU_NAME "MIPS R46xxx" +#define CPU_NAME "MIPS" #ifdef __cplusplus } #endif -#endif /* ! _INCLUDE_MIPS64ORION_h */ +#endif /* ! _INCLUDE_MIPS_h */ /* end of include file */ |