diff options
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/mips/rtems/score/cpu.h | 11 | ||||
| -rw-r--r-- | cpukit/score/cpu/mips/rtems/score/mips.h | 45 |
2 files changed, 24 insertions, 32 deletions
diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h index 35d936ec7e..7527ddecdf 100644 --- a/cpukit/score/cpu/mips/rtems/score/cpu.h +++ b/cpukit/score/cpu/mips/rtems/score/cpu.h @@ -18,7 +18,7 @@ * Transition Networks makes no representations about the suitability * of this software for any purpose. * - * Derived from source copyrighted as follows: + * Derived from c/src/exec/score/cpu/no_cpu/cpu.h: * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). @@ -93,7 +93,7 @@ extern void mips_fatal_error ( int error ); /* * Does RTEMS manage a dedicated interrupt stack in software? * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. + * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. * If FALSE, nothing is done. * * If the CPU supports a dedicated interrupt stack in hardware, @@ -162,19 +162,18 @@ extern void mips_fatal_error ( int error ); * If there is a FP coprocessor such as the i387 or mc68881, then * the answer is TRUE. * - * The macro name "MIPS64ORION_HAS_FPU" should be made CPU specific. + * The macro name "MIPS_HAS_FPU" should be made CPU specific. * It indicates whether or not this CPU model has FP support. For * example, it would be possible to have an i386_nofp CPU model * which set this to false to indicate that you have an i386 without * an i387 and wish to leave floating point support out of RTEMS. */ -#if ( MIPS64ORION_HAS_FPU == 1 ) +#if ( MIPS_HAS_FPU == 1 ) #define CPU_HARDWARE_FP TRUE #else #define CPU_HARDWARE_FP FALSE #endif -#define CPU_SOFTWARE_FP FALSE /* * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? @@ -444,7 +443,7 @@ typedef struct { */ /* - * Macros to access MIPS64ORION specific additions to the CPU Table + * Macros to access MIPS specific additions to the CPU Table */ #define rtems_cpu_configuration_get_clicks_per_microsecond() \ diff --git a/cpukit/score/cpu/mips/rtems/score/mips.h b/cpukit/score/cpu/mips/rtems/score/mips.h index 2ec96da0a4..90e959bd47 100644 --- a/cpukit/score/cpu/mips/rtems/score/mips.h +++ b/cpukit/score/cpu/mips/rtems/score/mips.h @@ -15,7 +15,7 @@ * Transition Networks makes no representations about the suitability * of this software for any purpose. * - * Derived from source copyrighted as follows: + * Derived from c/src/exec/score/cpu/no_cpu/no_cpu.h: * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). @@ -28,8 +28,8 @@ */ /* @(#)mips64orion.h 08/29/96 1.3 */ -#ifndef _INCLUDE_MIPS64ORION_h -#define _INCLUDE_MIPS64ORION_h +#ifndef _INCLUDE_MIPS_h +#define _INCLUDE_MIPS_h #ifdef __cplusplus extern "C" { @@ -44,40 +44,33 @@ extern "C" { * of the family. */ -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" -#define MIPS64ORION_HAS_FPU 1 - -#elif defined(R4650) - -#define CPU_MODEL_NAME "R4650" -#define MIPS64ORION_HAS_FPU 1 - -#elif defined(R4600) - -#define CPU_MODEL_NAME "R4600" -#define MIPS64ORION_HAS_FPU 1 +#if defined(__mips_soft_float) +#define MIPS_HAS_FPU 0 +#else +#define MIPS_HAS_FPU 1 +#endif +#if (__mips == 1) +#define CPU_MODEL_NAME "ISA Level 1 or 2" +#elif (__mips == 3) +#if defined(__mips64) +#define CPU_MODEL_NAME "ISA Level 4" #else - -#error "Unsupported CPU Model" - +#define CPU_MODEL_NAME "ISA Level 3" +#endif +#else +#error "Unknown MIPS ISA level" #endif /* * Define the name of the CPU family. */ -#define CPU_NAME "MIPS R46xxx" +#define CPU_NAME "MIPS" #ifdef __cplusplus } #endif -#endif /* ! _INCLUDE_MIPS64ORION_h */ +#endif /* ! _INCLUDE_MIPS_h */ /* end of include file */ |