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-rw-r--r--cpukit/score/cpu/mips/rtems/score/cpu.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h
index 4e1eba1ca6..3fe0b8d022 100644
--- a/cpukit/score/cpu/mips/rtems/score/cpu.h
+++ b/cpukit/score/cpu/mips/rtems/score/cpu.h
@@ -699,6 +699,11 @@ uint32_t mips_interrupt_mask( void );
_xlevel = _scratch2; \
} while(0)
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & SR_INTERRUPT_ENABLE_BITS ) != 0;
+}
+
/*
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not