diff options
Diffstat (limited to 'cpukit/score/cpu/microblaze/cpu.c')
| -rw-r--r-- | cpukit/score/cpu/microblaze/cpu.c | 192 |
1 files changed, 56 insertions, 136 deletions
diff --git a/cpukit/score/cpu/microblaze/cpu.c b/cpukit/score/cpu/microblaze/cpu.c index ca4a3ec2f6..de8fbfbba1 100644 --- a/cpukit/score/cpu/microblaze/cpu.c +++ b/cpukit/score/cpu/microblaze/cpu.c @@ -1,7 +1,16 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPUMicroBlaze + * + * @brief MicroBlaze architecture support implementation + */ + /* - * Copyright (c) 2015, Hesham Almatary - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). + * Copyright (c) 2015, Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -9,8 +18,8 @@ * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE @@ -29,31 +38,12 @@ #include "config.h" #endif -#include <rtems/system.h> #include <rtems/score/isr.h> +#include <rtems/score/tls.h> #include <rtems/score/wkspace.h> -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: NONE - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Initialize(void) +void _CPU_Initialize( void ) { - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ } void _CPU_Context_Initialize( @@ -66,136 +56,66 @@ void _CPU_Context_Initialize( void *tls_area ) { - uint32_t stack = ((uint32_t) stack_area_begin); + uint32_t stack = (uint32_t) stack_area_begin; uint32_t stack_high = stack + stack_area_size; - memset(context, 0, sizeof(*context)); + memset( context, 0, sizeof(*context) ) ; - context->r[0] = stack_high; - context->r[3] = (uint32_t) entry_point; -} - -/*PAGE - * - * _CPU_ISR_Get_level - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ + context->r1 = stack_high - 64; + context->r15 = (uint32_t) entry_point; -uint32_t _CPU_ISR_Get_level( void ) -{ - /* - * This routine returns the current interrupt level. - */ + uint32_t msr; + _CPU_MSR_GET( msr ); + context->rmsr = msr; - return 0; + if ( tls_area != NULL ) { + _TLS_TCB_at_area_begin_initialize( tls_area ); + } } -/*PAGE - * - * _CPU_ISR_install_raw_handler - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -) +void _CPU_Exception_frame_print( const CPU_Exception_frame *ctx ) { - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ } -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -) +void _CPU_ISR_Set_level( uint32_t level ) { - *old_handler = _ISR_Vector_table[ vector ]; + uint32_t microblaze_switch_reg; - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ + _CPU_MSR_GET( microblaze_switch_reg ); - _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); + if ( level == 0 ) { + microblaze_switch_reg |= (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); + } else { + microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); + } - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; + _CPU_MSR_SET( microblaze_switch_reg ); } -/*PAGE - * - * _CPU_Install_interrupt_stack - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Install_interrupt_stack( void ) +uint32_t _CPU_ISR_Get_level( void ) { + uint32_t level; + + _CPU_MSR_GET( level ); + + /* This is unique. The MSR register contains an interrupt enable flag where + * most other architectures have an interrupt disable flag. */ + return ( level & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE) ) == 0; } -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ +void _CPU_ISR_install_vector( + uint32_t vector, + CPU_ISR_handler new_handler, + CPU_ISR_handler *old_handler +) +{ + *old_handler = _ISR_Vector_table[ vector ]; + _ISR_Vector_table[ vector ] = new_handler; +} void *_CPU_Thread_Idle_body( uintptr_t ignored ) { - - for( ; ; ) - /* insert your "halt" instruction here */ ; - return NULL; + while ( true ) { + __asm__ volatile ( "sleep" ); + } } |