diff options
Diffstat (limited to 'cpukit/score/cpu/bfin')
| -rw-r--r-- | cpukit/score/cpu/bfin/.cvsignore | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/bfin/ChangeLog | 232 | ||||
| -rw-r--r-- | cpukit/score/cpu/bfin/Makefile.am | 22 | ||||
| -rw-r--r-- | cpukit/score/cpu/bfin/cpu.c | 214 | ||||
| -rw-r--r-- | cpukit/score/cpu/bfin/cpu_asm.S | 582 | ||||
| -rw-r--r-- | cpukit/score/cpu/bfin/preinstall.am | 58 | ||||
| -rw-r--r-- | cpukit/score/cpu/bfin/rtems/asm.h | 125 | ||||
| -rw-r--r-- | cpukit/score/cpu/bfin/rtems/bfin/bf533.h | 394 | ||||
| -rw-r--r-- | cpukit/score/cpu/bfin/rtems/bfin/bfin.h | 85 | ||||
| -rw-r--r-- | cpukit/score/cpu/bfin/rtems/score/bfin.h | 65 | ||||
| -rw-r--r-- | cpukit/score/cpu/bfin/rtems/score/cpu.h | 1264 | ||||
| -rw-r--r-- | cpukit/score/cpu/bfin/rtems/score/cpu_asm.h | 27 | ||||
| -rw-r--r-- | cpukit/score/cpu/bfin/rtems/score/types.h | 45 |
13 files changed, 3115 insertions, 0 deletions
diff --git a/cpukit/score/cpu/bfin/.cvsignore b/cpukit/score/cpu/bfin/.cvsignore new file mode 100644 index 0000000000..282522db03 --- /dev/null +++ b/cpukit/score/cpu/bfin/.cvsignore @@ -0,0 +1,2 @@ +Makefile +Makefile.in diff --git a/cpukit/score/cpu/bfin/ChangeLog b/cpukit/score/cpu/bfin/ChangeLog new file mode 100644 index 0000000000..91b1514a05 --- /dev/null +++ b/cpukit/score/cpu/bfin/ChangeLog @@ -0,0 +1,232 @@ +2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/score/cpu.h: + Use "__asm__" instead of "asm" for improved c99-compliance. + +2010-10-21 Joel Sherrill <joel.sherrill@oarcorp.com> + + * rtems/score/cpu.h: Add RTEMS_COMPILER_NO_RETURN_ATTRIBUTE to + _CPU_Context_restore() because it does not return. Telling GCC this + avoids generation of dead code. + +2010-07-29 Gedare Bloom <giddyup44@yahoo.com> + + PR 1635/cpukit + * rtems/score/cpu.h, rtems/score/types.h: Refactoring of priority + handling, to isolate the bitmap implementation of priorities in the + supercore so that priority management is a little more modular. This + change is in anticipation of scheduler implementations that can + select how they manage tracking priority levels / finding the highest + priority ready task. Note that most of the changes here are simple + renaming, to clarify the use of the bitmap-based priority management. + +2010-07-27 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/score/cpu.h: Assembler compatibility fixes. + +2010-07-16 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/score/cpu.h: Include <rtems/score/types.h> first. + * rtems/score/types.h: Use <rtems/score/basedefs.h> header file. + +2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com> + + PR 1573/cpukit + * cpu_asm.S, rtems/score/cpu.h: Add a per cpu data structure which + contains the information required by RTEMS for each CPU core. This + encapsulates information such as thread executing, heir, idle and + dispatch needed. + +2010-06-16 Joel Sherrill <joel.sherrilL@OARcorp.com> + + * cpu_asm.S: Use SYM macro to be consistent with other ports. + +2010-04-20 Allan Hessenflow <allanh@kallisti.com> + + * cpu_asm.S: L0-L3 were part of the interrupt context, but as + Mike Frysinger noted they were not being zeroed before calling + the C handlers. A patch that corrects this, as well as improving + some of the push/pop order to avoid stalls. + +2010-04-17 Allan Hessenflow <allanh@kallisti.com> + + * cpu.c, cpu_asm.S, rtems/score/cpu.h: Fine tune registers saved in the + context. The sp and imask registers need to be saved. Also allocated + 12 bytes on the stack at thread entry as the abi requires that. + +2010-04-17 Mike Frysinger <vapier.adi@gmail.com> + + * cpu.c: Blackfin ABI requires L registers to be 0 upon function entry. + +2010-03-27 Joel Sherrill <joel.sherrill@oarcorp.com> + + * Makefile.am: Remove unused file. + * irq.c: Removed. + +2009-05-25 Allan Hessenflow <allanh@kallisti.com> + + PR 1417/cpukit + * rtems/score/cpu.h: corrected _CPU_ISR_Flash implementation, added + core synchronization after all cli/sti. + +2009-03-12 Joel Sherrill <joel.sherrill@OARcorp.com> + + PR 1385/cpukit + * cpu_asm.S: When the type rtems_boolean was switched to the C99 bool, + the size changed from 4 bytes to 1 byte. The interrupt dispatching + code accesses two boolean variables for scheduling purposes and the + assembly implementations of this code did not get updated. + +2009-02-12 Joel Sherrill <joel.sherrill@oarcorp.com> + + * cpu.c, rtems/score/cpu.h: Change prototype of IDLE thread to + consistently return void * and take a uintptr_t argument. + +2009-02-11 Joel Sherrill <joel.sherrill@oarcorp.com> + + * cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and + passing address of _Thread_Dispatch to _CPU_Initialize. Clean up + comments. + +2008-09-11 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: Do not define boolean, single_precision, + double_precision unless RTEMS_DEPRECATED_TYPES is given. + +2008-09-08 Joel Sherrill <joel.sherrill@oarcorp.com> + + * cpu.c: Remove extraneous spaces. + +2008-09-05 Ralf Corsépius <ralf.corsepius@rtems.org> + + * cpu.c, rtems/score/cpu.h: Convert to "bool". + +2008-08-21 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: Include stdbool.h. + Use bool as base-type for boolean. + +2008-08-15 Joel Sherrill <joel.sherrill@OARcorp.com> + + * ChangeLog: Add correct entry. + +2008-08-13 Allan Hessenflow <allanh@kallisti.com> + + * cpu.c, cpu_asm.S, irq.c, rtems/score/cpu.h, + rtems/score/cpu_asm.h: reworked interrupt handling to fix + context switching. + +2008-07-31 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Correct prototype of Idle threads. + +2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting + parameter to indicate that the port uses the Simple Vectored + Interrupt model or the Programmable Interrupt Controller Model. The + PIC model is implemented primarily in the BSP and it is responsible + for all memory allocation. + +2007-12-20 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Use correct register name. + +2007-12-17 Joel Sherrill <joel.sherrill@oarcorp.com> + + * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility. + +2007-12-17 Joel Sherrill <joel.sherrill@OARcorp.com> + + * cpu.c, irq.c, rtems/score/cpu_asm.h: Sweep to make sure grep for + COPYRIGHT passes. + +2007-12-04 Joel Sherrill <joel.sherrill@OARcorp.com> + + * cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU + Table to Configuration Table. Eliminate CPU Table from all ports. + Delete references to CPU Table in all forms. + +2007-12-03 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Moved most of the remaining CPU Table fields to + the Configuration Table. This included pretasking_hook, + predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace, + extra_mpci_receive_server_stack, stack_allocate_hook, and + stack_free_hook. As a side-effect of this effort some multiprocessing + code was made conditional and some style clean up occurred. + +2007-09-10 Alain Schaefer <alani@easc.ch> + + * cpu_asm.S: Fix two problems: + - CC bit has been clobbered and was not correctly restored + - bfin hardware does not allow to read instructions from the L1 + + +2007-09-10 Alain Schaefer <alani@easc.ch> + + * rtems/bfin/bf533.h: Add more definitions. + +2007-05-31 Alain Schaefer <alani@easc.ch> + + * rtems/score/cpu.h: Modifiy inline assembly language + constraints to use a data register as the CTL/STI + instructions requires. This is not only more correct, + it avoids GCC PR31787. + +2007-05-24 Alain Schaefer <alani@easc.ch> + + * rtems/score/cpu.h: Fix incorrect interrupt mask. + +2007-04-17 Joel Sherrill <joel@OARcorp.com> + + * rtems/bfin/bf533.h: Fix warnings about constants being too large. + +2007-04-17 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/score/cpu.h: + Use Context_Control_fp* instead of void* for fp_contexts. + Eliminate evil casts. + +2006-11-17 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: Remove unsigned64, signed64. + +2006-11-09 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/bfin/bf533.h, rtems/bfin/bfin.h: Remove stray whitespaces. + * rtems/score/bfin.h: Use __BFIN__ instead of BFIN. + +2006-11-08 Ralf Corsépius <ralf.corsepius@rtems.org> + + * cpu_asm.S: Re-add HI, LO. + +2006-11-08 Ralf Corsépius <ralf.corsepius@rtems.org> + + * irq.c: Add missing newline. + * rtems/score/cpu.h: Eliminate hidden backspaces. + +2006-10-24 Joel Sherrill <joel@OARcorp.com> + + * rtems/bfin/bfin.h: Eliminate hi, lo, HI, LO, and MK_BMSK. + +2006-10-24 Alain Schaefer <alani@easc.ch> + + * Makefile.am, cpu.c, cpu_asm.S, preinstall.am, rtems/score/bfin.h: + Clean up rtems/score/bfin.h removing parts that are not needed by + RTEMS CPUkit to bfin specific .h files. + * rtems/bfin/bf533.h, rtems/bfin/bfin.h: New files. + +2006-10-23 Joel Sherrill <joel@OARcorp.com> + + * cpu.c, rtems/score/cpu.h: Use the default IDLE thread body. + +2006-10-23 Joel Sherrill <joel@OARcorp.com> + + * .cvsignore, ChangeLog, Makefile.am, cpu.c, cpu_asm.S, irq.c, + preinstall.am, rtems/asm.h, rtems/score/bfin.h, rtems/score/cpu.h, + rtems/score/cpu_asm.h, rtems/score/types.h: New files. + +2006-10-20 Alain Schaefer <alani@easc.ch> + + * all files : Initial version diff --git a/cpukit/score/cpu/bfin/Makefile.am b/cpukit/score/cpu/bfin/Makefile.am new file mode 100644 index 0000000000..4eebfcc7c6 --- /dev/null +++ b/cpukit/score/cpu/bfin/Makefile.am @@ -0,0 +1,22 @@ +## +## $Id$ +## + +include $(top_srcdir)/automake/compile.am + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = rtems/asm.h + +include_rtems_bfindir = $(includedir)/rtems/bfin +include_rtems_bfin_HEADERS = rtems/bfin/bfin.h rtems/bfin/bf533.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/bfin.h \ + rtems/score/cpu_asm.h rtems/score/types.h + +noinst_LIBRARIES = libscorecpu.a +libscorecpu_a_SOURCES = cpu.c cpu_asm.S +libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) + +include $(srcdir)/preinstall.am +include $(top_srcdir)/automake/local.am diff --git a/cpukit/score/cpu/bfin/cpu.c b/cpukit/score/cpu/bfin/cpu.c new file mode 100644 index 0000000000..f342e75e44 --- /dev/null +++ b/cpukit/score/cpu/bfin/cpu.c @@ -0,0 +1,214 @@ +/* Blackfin CPU Dependent Source + * + * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. + * written by Alain Schaefer <alain.schaefer@easc.ch> + * and Antonio Giovanini <antonio@atos.com.br> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/system.h> +#include <rtems/score/isr.h> +#include <rtems/score/wkspace.h> +#include <rtems/score/bfin.h> +#include <rtems/bfin/bfin.h> + +/* _CPU_Initialize + * + * This routine performs processor dependent initialization. + * + * INPUT PARAMETERS: NONE + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + + +extern void _ISR15_Handler(void); +extern void _CPU_Emulation_handler(void); +extern void _CPU_Reset_handler(void); +extern void _CPU_NMI_handler(void); +extern void _CPU_Exception_handler(void); +extern void _CPU_Unhandled_Interrupt_handler(void); + +void _CPU_Initialize(void) +{ + /* + * If there is not an easy way to initialize the FP context + * during Context_Initialize, then it is usually easier to + * save an "uninitialized" FP context here and copy it to + * the task's during Context_Initialize. + */ + + /* FP context initialization support goes here */ + + + + proc_ptr ignored; + +#if 0 + /* occassionally useful debug stuff */ + int i; + _CPU_ISR_install_raw_handler(0, _CPU_Emulation_handler, &ignored); + _CPU_ISR_install_raw_handler(1, _CPU_Reset_handler, &ignored); + _CPU_ISR_install_raw_handler(2, _CPU_NMI_handler, &ignored); + _CPU_ISR_install_raw_handler(3, _CPU_Exception_handler, &ignored); + for (i = 5; i < 15; i++) + _CPU_ISR_install_raw_handler(i, _CPU_Unhandled_Interrupt_handler, &ignored); +#endif + + /* install handler that will be used to call _Thread_Dispatch */ + _CPU_ISR_install_raw_handler( 15, _ISR15_Handler, &ignored ); + /* enable self nesting */ + __asm__ __volatile__ ("syscfg = %0" : : "d" (0x00000004)); +} + + + + +/*PAGE + * + * _CPU_ISR_Get_level + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +uint32_t _CPU_ISR_Get_level( void ) +{ + /* + * This routine returns the current interrupt level. + */ + + register uint32_t _tmpimask; + + /*read from the IMASK registers*/ + + _tmpimask = *((uint32_t*)IMASK); + + return (_tmpimask & 0xffe0) ? 0 : 1; +} + +/*PAGE + * + * _CPU_ISR_install_raw_handler + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + proc_ptr *interrupt_table = NULL; + /* + * This is where we install the interrupt handler into the "raw" interrupt + * table used by the CPU to dispatch interrupt handlers. + */ + + /* base of vector table on blackfin architecture */ + interrupt_table = (void*)0xFFE02000; + + *old_handler = interrupt_table[ vector ]; + interrupt_table[ vector ] = new_handler; + +} + +/*PAGE + * + * _CPU_ISR_install_vector + * + * This kernel routine installs the RTEMS handler for the + * specified vector. + * + * Input parameters: + * vector - interrupt vector number + * old_handler - former ISR for this vector number + * new_handler - replacement ISR for this vector number + * + * Output parameters: NONE + * + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + proc_ptr ignored; + + *old_handler = _ISR_Vector_table[ vector ]; + + /* + * We put the actual user ISR address in '_ISR_vector_table'. This will + * be used by the _ISR_Handler so the user gets control. + */ + + _ISR_Vector_table[ vector ] = new_handler; + + _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); +} + +#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) +void *_CPU_Thread_Idle_body(uint32_t ignored) +{ + while (1) { + __asm__ __volatile__("ssync; idle; ssync"); + } +} +#endif + +/* + * Copied from the arm port. + */ +void _CPU_Context_Initialize( + Context_Control *the_context, + uint32_t *stack_base, + uint32_t size, + uint32_t new_level, + void *entry_point, + bool is_fp +) +{ + uint32_t stack_high; /* highest "stack aligned" address */ + stack_high = ((uint32_t)(stack_base) + size); + + /* blackfin abi requires caller to reserve 12 bytes on stack */ + the_context->register_sp = stack_high - 12; + the_context->register_rets = (uint32_t) entry_point; + the_context->imask = new_level ? 0 : 0xffff; +} + + + +/*PAGE + * + * _CPU_Install_interrupt_stack + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +void _CPU_Install_interrupt_stack( void ) +{ +} diff --git a/cpukit/score/cpu/bfin/cpu_asm.S b/cpukit/score/cpu/bfin/cpu_asm.S new file mode 100644 index 0000000000..7944550a3c --- /dev/null +++ b/cpukit/score/cpu/bfin/cpu_asm.S @@ -0,0 +1,582 @@ +/* cpu_asm.S + * + * This file contains the basic algorithms for all assembly code used + * in the Blackfin port of RTEMS. These algorithms must be implemented + * in assembly language + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * Based on earlier version: + * + * Copyright (c) 2006 by Atos Automacao Industrial Ltda. + * written by Alain Schaefer <alain.schaefer@easc.ch> + * and Antonio Giovanini <antonio@atos.com.br> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/asm.h> +#include <rtems/score/cpu_asm.h> +#include <rtems/score/bfin.h> +#include <rtems/bfin/bfin.h> +#include <rtems/score/percpu.h> + +#define LO(con32) ((con32) & 0xFFFF) +#define HI(con32) (((con32) >> 16) & 0xFFFF) + + +#if 0 +/* some debug routines */ + .globl SYM(_CPU_write_char); +SYM(_CPU_write_char): + p0.h = 0xffc0; + p0.l = 0x0400; +txWaitLoop: + r1 = w[p0 + 0x14]; + cc = bittst(r1, 5); + if !cc jump txWaitLoop; + w[p0 + 0x00] = r0; + rts; + + .globl SYM(_CPU_write_crlf); +SYM(_CPU_write_crlf): + r0 = '\r'; + [--sp] = rets; + call SYM(_CPU_write_char); + rets = [sp++]; + r0 = '\n'; + jump SYM(_CPU_write_char); + +SYM(_CPU_write_space): + r0 = ' '; + jump SYM(_CPU_write_char); + + .globl SYM(_CPU_write_nybble); +SYM(_CPU_write_nybble:) + r1 = 0x0f; + r0 = r0 & r1; + r0 += '0'; + r1 = '9'; + cc = r0 <= r1; + if cc jump SYM(_CPU_write_char); + r0 += 'a' - '0' - 10; + jump SYM(_CPU_write_char); + + .globl SYM(_CPU_write_byte); +SYM(_CPU_write_byte): + [--sp] = r0; + [--sp] = rets; + r0 >>= 4; + call SYM(_CPU_write_nybble); + rets = [sp++]; + r0 = [sp++]; + jump SYM(_CPU_write_nybble); + +SYM(_CPU_write_chawmp): + [--sp] = r0; + [--sp] = rets; + r0 >>= 8; + call SYM(_CPU_write_byte); + rets = [sp++]; + r0 = [sp++]; + jump SYM(_CPU_write_byte); + +SYM(_CPU_write_gawble): + [--sp] = r0; + [--sp] = rets; + r0 >>= 16; + call SYM(_CPU_write_chawmp); + rets = [sp++]; + r0 = [sp++]; + jump SYM(_CPU_write_chawmp); + +SYM(_CPU_dump_registers): + [--sp] = rets; + [--sp] = r0; + [--sp] = r1; + [--sp] = p0; + r0 = [sp + 8]; + call SYM(_CPU_write_gawble); + call SYM(_CPU_write_space); + r0 = [sp + 4]; + call SYM(_CPU_write_gawble); + call SYM(_CPU_write_space); + r0 = r2; + call SYM(_CPU_write_gawble); + call SYM(_CPU_write_space); + r0 = r3; + call SYM(_CPU_write_gawble); + call SYM(_CPU_write_space); + r0 = r4; + call SYM(_CPU_write_gawble); + call SYM(_CPU_write_space); + r0 = r5; + call SYM(_CPU_write_gawble); + call SYM(_CPU_write_space); + r0 = r6; + call SYM(_CPU_write_gawble); + call SYM(_CPU_write_space); + r0 = r7; + call SYM(_CPU_write_gawble); + call SYM(_CPU_write_crlf); + r0 = [sp]; + call SYM(_CPU_write_gawble); + call SYM(_CPU_write_space); + r0 = p1; + call SYM(_CPU_write_gawble); + call SYM(_CPU_write_space); + r0 = p2; + call SYM(_CPU_write_gawble); + call SYM(_CPU_write_space); + r0 = p3; + call SYM(_CPU_write_gawble); + call SYM(_CPU_write_space); + r0 = p4; + call SYM(_CPU_write_gawble); + call SYM(_CPU_write_space); + r0 = p5; + call SYM(_CPU_write_gawble); + call SYM(_CPU_write_space); + r0 = fp; + call SYM(_CPU_write_gawble); + call SYM(_CPU_write_space); + r0 = sp; + r0 += 16; + call SYM(_CPU_write_gawble); + call SYM(_CPU_write_crlf); + + p0 = [sp++]; + r1 = [sp++]; + r0 = [sp++]; + rets = [sp++]; + rts; + + .globl SYM(_CPU_Exception_handler); +SYM(_CPU_Exception_handler): + usp = sp; + sp.h = 0xffb0; + sp.l = 0x1000; + [--sp] = (r7:0,p5:0); + + r0 = 'x'; + call SYM(_CPU_write_char); + jump hcf; + + + .globl SYM(_CPU_Emulation_handler); +SYM(_CPU_Emulation_handler): + usp = sp; + sp.h = 0xffb0; + sp.l = 0x1000; + [--sp] = (r7:0,p5:0); + + r0 = 'e'; + call SYM(_CPU_write_char); + jump hcf; + + .globl SYM(_CPU_Reset_handler); +SYM(_CPU_Reset_handler): + usp = sp; + sp.h = 0xffb0; + sp.l = 0x1000; + [--sp] = (r7:0,p5:0); + + r0 = 'r'; + call SYM(_CPU_write_char); + jump hcf; + + .globl SYM(_CPU_NMI_handler); +SYM(_CPU_NMI_handler): + usp = sp; + sp.h = 0xffb0; + sp.l = 0x1000; + [--sp] = (r7:0,p5:0); + + r0 = 'n'; + call SYM(_CPU_write_char); + jump hcf; + + .globl SYM(_CPU_Unhandled_Interrupt_handler); +SYM(_CPU_Unhandled_Interrupt_handler): + usp = sp; + sp.h = 0xffb0; + sp.l = 0x1000; + [--sp] = (r7:0,p5:0); + + call SYM(_CPU_write_crlf); + r0 = 'i'; + call SYM(_CPU_write_char); + p0.h = HI(IPEND); + p0.l = LO(IPEND); + r0 = [p0]; + call SYM(_CPU_write_chawmp); + jump hcf; + +hcf: + idle; + jump hcf; + +#endif + + +/* _CPU_Context_switch + * + * This routine performs a normal non-FP context switch. + * + * bfin Specific Information: + * + * For now we simply save all registers. + * + */ + +/* make sure this sequence stays in sync with the definition for + Context_Control in rtems/score/cpu.h */ + .globl SYM(_CPU_Context_switch) +SYM(_CPU_Context_switch): + /* Start saving context R0 = current, R1=heir */ + p0 = r0; + [p0++] = r4; + [p0++] = r5; + [p0++] = r6; + [p0++] = r7; + + /* save pointer registers */ + [p0++] = p3; + [p0++] = p4; + [p0++] = p5; + [p0++] = fp; + [p0++] = sp; + + /* save rets */ + r0 = rets; + [p0++] = r0; + + /* save IMASK */ + p1.h = HI(IMASK); + p1.l = LO(IMASK); + r0 = [p1]; + [p0++] = r0; + + p0 = r1; +restore: + /* restore data registers */ + r4 = [p0++]; + r5 = [p0++]; + r6 = [p0++]; + r7 = [p0++]; + + /* restore pointer registers */ + p3 = [p0++]; + p4 = [p0++]; + p5 = [p0++]; + fp = [p0++]; + sp = [p0++]; + + /* restore rets */ + r0 = [p0++]; + rets = r0; + + /* restore IMASK */ + r0 = [p0++]; + p1.h = HI(IMASK); + p1.l = LO(IMASK); + [p1] = r0; + + rts; + + +/* + * _CPU_Context_restore + * + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + * + * NOTE: May be unnecessary to reload some registers. + * + * Blackfin Specific Information: + * + * none + * + */ + .globl SYM(_CPU_Context_restore) +SYM(_CPU_Context_restore): + p0 = r0; + jump restore; + + + .globl SYM(_ISR_Handler) +SYM(_ISR_Handler): + .extern SYM(_Thread_Dispatch_disable_level) + /* all interrupts are disabled at this point */ + /* the following few items are pushed onto the task stack for at + most one interrupt; nested interrupts will be using the interrupt + stack for everything. */ + [--sp] = astat; + [--sp] = p1; + [--sp] = p0; + [--sp] = r1; + [--sp] = r0; + p0.h = ISR_NEST_LEVEL; + p0.l = ISR_NEST_LEVEL; + r0 = [p0]; + r0 += 1; + [p0] = r0; + cc = r0 <= 1 (iu); + if !cc jump noStackSwitch; + /* setup interrupt stack */ + r0 = sp; + p0.h = INTERRUPT_STACK_HIGH; + p0.l = INTERRUPT_STACK_HIGH; + sp = [p0]; + [--sp] = r0; +noStackSwitch: + /* disable thread dispatch */ + p0.h = SYM(_Thread_Dispatch_disable_level); + p0.l = SYM(_Thread_Dispatch_disable_level); + r0 = [p0]; + r0 += 1; + [p0] = r0; + + [--sp] = reti; /* interrupts are now enabled */ + + /* figure out what vector we are */ + p0.h = HI(IPEND); + p0.l = LO(IPEND); + r1 = [p0]; + /* we should only get here for events that require RTI to return */ + r1 = r1 >> 5; + r0 = 4; + /* at least one bit must be set, so this loop will exit */ +vectorIDLoop: + r0 += 1; + r1 = rot r1 by -1; + if !cc jump vectorIDLoop; + + [--sp] = r2; + p0.h = SYM(_ISR_Vector_table); + p0.l = SYM(_ISR_Vector_table); + r2 = [p0]; + r1 = r0 << 2; + r1 = r1 + r2; + p0 = r1; + p0 = [p0]; + cc = p0 == 0; + if cc jump noHandler; + + /* r2, r0, r1, p0, p1, astat are already saved */ + [--sp] = a1.x; + [--sp] = a1.w; + [--sp] = a0.x; + [--sp] = a0.w; + [--sp] = r3; + [--sp] = p3; + [--sp] = p2; + [--sp] = lc1; + [--sp] = lc0; + [--sp] = lt1; + [--sp] = lt0; + [--sp] = lb1; + [--sp] = lb0; + [--sp] = i3; + [--sp] = i2; + [--sp] = i1; + [--sp] = i0; + [--sp] = m3; + [--sp] = m2; + [--sp] = m1; + [--sp] = m0; + [--sp] = l3; + [--sp] = l2; + [--sp] = l1; + [--sp] = l0; + [--sp] = b3; + [--sp] = b2; + [--sp] = b1; + [--sp] = b0; + [--sp] = rets; + /* call user isr; r0 = vector number, r1 = frame pointer */ + r1 = fp; /* is this really what should be passed here? */ + r2 = 0; + l0 = r2; + l1 = r2; + l2 = r2; + l3 = r2; + sp += -12; /* bizarre abi... */ + call (p0); + sp += 12; + rets = [sp++]; + b0 = [sp++]; + b1 = [sp++]; + b2 = [sp++]; + b3 = [sp++]; + l0 = [sp++]; + l1 = [sp++]; + l2 = [sp++]; + l3 = [sp++]; + m0 = [sp++]; + m1 = [sp++]; + m2 = [sp++]; + m3 = [sp++]; + i0 = [sp++]; + i1 = [sp++]; + i2 = [sp++]; + i3 = [sp++]; + lb0 = [sp++]; + lb1 = [sp++]; + lt0 = [sp++]; + lt1 = [sp++]; + lc0 = [sp++]; + lc1 = [sp++]; + p2 = [sp++]; + p3 = [sp++]; + r3 = [sp++]; + a0.w = [sp++]; + a0.x = [sp++]; + a1.w = [sp++]; + a1.x = [sp++]; + +noHandler: + r2 = [sp++]; + /* this disables interrupts again */ + reti = [sp++]; + + p0.h = ISR_NEST_LEVEL; + p0.l = ISR_NEST_LEVEL; + r0 = [p0]; + r0 += -1; + [p0] = r0; + cc = r0 == 0; + if !cc jump noStackRestore; + sp = [sp]; +noStackRestore: + + /* check this stuff to ensure context_switch_necessary and + isr_signals_to_thread_executing are being handled appropriately. */ + p0.h = SYM(_Thread_Dispatch_disable_level); + p0.l = SYM(_Thread_Dispatch_disable_level); + r0 = [p0]; + r0 += -1; + [p0] = r0; + cc = r0 == 0; + if !cc jump noDispatch + + /* do thread dispatch if necessary */ + p0.h = DISPATCH_NEEDED; + p0.l = DISPATCH_NEEDED; + r0 = B[p0] (Z); + cc = r0 == 0; + if cc jump noDispatch +doDispatch: + r0 = 0; + B[p0] = r0; + raise 15; +noDispatch: + r0 = [sp++]; + r1 = [sp++]; + p0 = [sp++]; + p1 = [sp++]; + astat = [sp++]; + rti + + +/* the approach here is for the main interrupt handler, when a dispatch is + wanted, to do a "raise 15". when the main interrupt handler does its + "rti", the "raise 15" takes effect and we end up here. we can now + safely call _Thread_Dispatch, and do an "rti" to get back to the + original interrupted function. this does require self-nesting to be + enabled; the maximum nest depth is the number of tasks. */ + .global SYM(_ISR15_Handler) +SYM(_ISR15_Handler): + [--sp] = reti; + [--sp] = rets; + [--sp] = astat; + [--sp] = a1.x; + [--sp] = a1.w; + [--sp] = a0.x; + [--sp] = a0.w; + [--sp] = r3; + [--sp] = r2; + [--sp] = r1; + [--sp] = r0; + [--sp] = p3; + [--sp] = p2; + [--sp] = p1; + [--sp] = p0; + [--sp] = lc1; + [--sp] = lc0; + [--sp] = lt1; + [--sp] = lt0; + [--sp] = lb1; + [--sp] = lb0; + [--sp] = i3; + [--sp] = i2; + [--sp] = i1; + [--sp] = i0; + [--sp] = m3; + [--sp] = m2; + [--sp] = m1; + [--sp] = m0; + [--sp] = l3; + [--sp] = l2; + [--sp] = l1; + [--sp] = l0; + [--sp] = b3; + [--sp] = b2; + [--sp] = b1; + [--sp] = b0; + r2 = 0; + l0 = r2; + l1 = r2; + l2 = r2; + l3 = r2; + sp += -12; /* bizarre abi... */ + call SYM(_Thread_Dispatch); + sp += 12; + b0 = [sp++]; + b1 = [sp++]; + b2 = [sp++]; + b3 = [sp++]; + l0 = [sp++]; + l1 = [sp++]; + l2 = [sp++]; + l3 = [sp++]; + m0 = [sp++]; + m1 = [sp++]; + m2 = [sp++]; + m3 = [sp++]; + i0 = [sp++]; + i1 = [sp++]; + i2 = [sp++]; + i3 = [sp++]; + lb0 = [sp++]; + lb1 = [sp++]; + lt0 = [sp++]; + lt1 = [sp++]; + lc0 = [sp++]; + lc1 = [sp++]; + p0 = [sp++]; + p1 = [sp++]; + p2 = [sp++]; + p3 = [sp++]; + r0 = [sp++]; + r1 = [sp++]; + r2 = [sp++]; + r3 = [sp++]; + a0.w = [sp++]; + a0.x = [sp++]; + a1.w = [sp++]; + a1.x = [sp++]; + astat = [sp++]; + rets = [sp++]; + reti = [sp++]; + rti; + diff --git a/cpukit/score/cpu/bfin/preinstall.am b/cpukit/score/cpu/bfin/preinstall.am new file mode 100644 index 0000000000..10a77a59d9 --- /dev/null +++ b/cpukit/score/cpu/bfin/preinstall.am @@ -0,0 +1,58 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif + +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + +$(PROJECT_INCLUDE)/rtems/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems + @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) + +$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h + +$(PROJECT_INCLUDE)/rtems/bfin/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/bfin + @: > $(PROJECT_INCLUDE)/rtems/bfin/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/bfin/$(dirstamp) + +$(PROJECT_INCLUDE)/rtems/bfin/bfin.h: rtems/bfin/bfin.h $(PROJECT_INCLUDE)/rtems/bfin/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/bfin/bfin.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/bfin/bfin.h + +$(PROJECT_INCLUDE)/rtems/bfin/bf533.h: rtems/bfin/bf533.h $(PROJECT_INCLUDE)/rtems/bfin/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/bfin/bf533.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/bfin/bf533.h + +$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score + @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + +$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h + +$(PROJECT_INCLUDE)/rtems/score/bfin.h: rtems/score/bfin.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/bfin.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/bfin.h + +$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h + +$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h + diff --git a/cpukit/score/cpu/bfin/rtems/asm.h b/cpukit/score/cpu/bfin/rtems/asm.h new file mode 100644 index 0000000000..bca3141cb9 --- /dev/null +++ b/cpukit/score/cpu/bfin/rtems/asm.h @@ -0,0 +1,125 @@ +/** + * @file rtems/asm.h + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + */ + +/* + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + * + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1994-2006. + * On-Line Applications Research Corporation (OAR). + * + * $Id$ + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include <rtems/score/cpuopts.h> +#include <rtems/score/bfin.h> + +#ifndef __USER_LABEL_PREFIX__ +/** + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + * + * This symbol is prefixed to all C program symbols. + */ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +/** + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + * + * This symbol is prefixed to all register names. + */ +#define __REGISTER_PREFIX__ +#endif + +#include <rtems/concat.h> + +/** Use the right prefix for global labels. */ +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/** Use the right prefix for registers. */ +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +/** This macro is used to denote the beginning of a code declaration. */ +#define BEGIN_CODE_DCL .text +/** This macro is used to denote the end of a code declaration. */ +#define END_CODE_DCL +/** This macro is used to denote the beginning of a data declaration section. */ +#define BEGIN_DATA_DCL .data +/** This macro is used to denote the end of a data declaration section. */ +#define END_DATA_DCL +/** This macro is used to denote the beginning of a code section. */ +#define BEGIN_CODE .text +/** This macro is used to denote the end of a code section. */ +#define END_CODE +/** This macro is used to denote the beginning of a data section. */ +#define BEGIN_DATA +/** This macro is used to denote the end of a data section. */ +#define END_DATA +/** This macro is used to denote the beginning of the + * unitialized data section. + */ +#define BEGIN_BSS +/** This macro is used to denote the end of the unitialized data section. */ +#define END_BSS +/** This macro is used to denote the end of the assembly file. */ +#define END + +/** + * This macro is used to declare a public global symbol. + * + * @note This must be tailored for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ +#define PUBLIC(sym) .globl SYM (sym) + +/** + * This macro is used to prototype a public global symbol. + * + * @note This must be tailored for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ +#define EXTERN(sym) .globl SYM (sym) + +#endif diff --git a/cpukit/score/cpu/bfin/rtems/bfin/bf533.h b/cpukit/score/cpu/bfin/rtems/bfin/bf533.h new file mode 100644 index 0000000000..4a66bc5a38 --- /dev/null +++ b/cpukit/score/cpu/bfin/rtems/bfin/bf533.h @@ -0,0 +1,394 @@ +/* bfin.h + * + * This file defines basic MMR for the Blackfin 531/532/533 CPU. + * The MMR have been taken from the ADSP-BF533 Blackfin Processor + * Hardware Reference from Analog Devices. Mentioned Chapters + * refer to this Documentation. + * + * The Blackfins MMRs are divided into core MMRs (0xFFE0 0000–0xFFFF FFFF) + * and System MMRs (0xFFC0 0000–0xFFE0 0000). The core MMRs are defined + * in bfin.h which is included. + * + * COPYRIGHT (c) 2006. + * Atos Automacao Industrial LTDA. + * modified by Alain Schaefer <alain.schaefer@easc.ch> + * and Antonio Giovanini <antonio@atos.com.br> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + * + */ + +#ifndef _RTEMS_BFIN_533_H +#define _RTEMS_BFIN_533_H + +#include <rtems/bfin/bfin.h> + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Clock and System Control Chapter 8 */ +#define PLL_CTL 0xFFC00000L +#define PLL_DIV 0xFFC00004L +#define VR_CTL 0xFFC00008L +#define PLL_STAT 0xFFC0000CL +#define PLL_LOCKCNT 0xFFC00010L +#define SWRST 0xFFC00100L +#define SYSCR 0xFFC00104L + +/* SPI Controller Chapter 10 */ +#define SPI_CTL 0xFFC00500L +#define SPI_FLG 0xFFC00504L +#define SPI_STAT 0xFFC00508L +#define SPI_TDBR 0xFFC0050CL +#define SPI_RDBR 0xFFC00510L +#define SPI_BAUD 0xFFC00514L +#define SPI_SHADOW 0xFFC00518L + +/* SPORT0 Controller */ +#define SPORT0_TCR1 0xFFC00800L +#define SPORT0_TCR2 0xFFC00804L +#define SPORT0_TCLKDIV 0xFFC00808L +#define SPORT0_TFSDIV 0xFFC0080CL +#define SPORT0_TX 0xFFC00810L +#define SPORT0_RX 0xFFC00818L +#define SPORT0_RCR1 0xFFC00820L +#define SPORT0_RCR2 0xFFC00824L +#define SPORT0_RCLKDIV 0xFFC00828L +#define SPORT0_RFSDIV 0xFFC0082CL +#define SPORT0_STAT 0xFFC00830L +#define SPORT0_CHNL 0xFFC00834L +#define SPORT0_MCMC1 0xFFC00838L +#define SPORT0_MCMC2 0xFFC0083CL +#define SPORT0_MTCS0 0xFFC00840L +#define SPORT0_MTCS1 0xFFC00844L +#define SPORT0_MTCS2 0xFFC00848L +#define SPORT0_MTCS3 0xFFC0084CL +#define SPORT0_MRCS0 0xFFC00850L +#define SPORT0_MRCS1 0xFFC00854L +#define SPORT0_MRCS2 0xFFC00858L +#define SPORT0_MRCS3 0xFFC0085CL + +/* Parallel Peripheral Interface (PPI) Chapter 11 */ + +#define PPI_CONTROL 0xFFC01000L +#define PPI_STATUS 0xFFC01004L +#define PPI_COUNT 0xFFC01008L +#define PPI_DELAY 0xFFC0100CL +#define PPI_FRAME 0xFFC01010L + +/********* PPI MASKS ***********/ +/* PPI_CONTROL Masks */ +#define PORT_EN 0x00000001 +#define PORT_DIR 0x00000002 +#define XFR_TYPE 0x0000000C +#define PORT_CFG 0x00000030 +#define FLD_SEL 0x00000040 +#define PACK_EN 0x00000080 +#define DMA32 0x00000100 +#define SKIP_EN 0x00000200 +#define SKIP_EO 0x00000400 +#define DLENGTH 0x00003800 +#define DLEN_8 0x0 +#define DLEN(x) (((x-9) & 0x07) << 11) +#define POL 0x0000C000 + +/* PPI_STATUS Masks */ +#define FLD 0x00000400 +#define FT_ERR 0x00000800 +#define OVR 0x00001000 +#define UNDR 0x00002000 +#define ERR_DET 0x00004000 +#define ERR_NCOR 0x00008000 + +/* SPORT1 Controller Chapter 12 */ +#define SPORT1_TCR1 0xFFC00900L +#define SPORT1_TCR2 0xFFC00904L +#define SPORT1_TCLKDIV 0xFFC00908L +#define SPORT1_TFSDIV 0xFFC0090CL +#define SPORT1_TX 0xFFC00910L +#define SPORT1_RX 0xFFC00918L +#define SPORT1_RCR1 0xFFC00920L +#define SPORT1_RCR2 0xFFC00924L +#define SPORT1_RCLKDIV 0xFFC00928L +#define SPORT1_RFSDIV 0xFFC0092CL +#define SPORT1_STAT 0xFFC00930L +#define SPORT1_CHNL 0xFFC00934L +#define SPORT1_MCMC1 0xFFC00938L +#define SPORT1_MCMC2 0xFFC0093CL +#define SPORT1_MTCS0 0xFFC00940L +#define SPORT1_MTCS1 0xFFC00944L +#define SPORT1_MTCS2 0xFFC00948L +#define SPORT1_MTCS3 0xFFC0094CL +#define SPORT1_MRCS0 0xFFC00950L +#define SPORT1_MRCS1 0xFFC00954L +#define SPORT1_MRCS2 0xFFC00958L +#define SPORT1_MRCS3 0xFFC0095CL + +/* SPORTx_TCR1 Masks */ +#define TSPEN 0x0001 +#define ITCLK 0x0002 +#define TDTYPE 0x000C +#define TLSBIT 0x0010 +#define ITFS 0x0200 +#define TFSR 0x0400 +#define DITFS 0x0800 +#define LTFS 0x1000 +#define LATFS 0x2000 +#define TCKFE 0x4000 + +/* SPORTx_TCR2 Masks */ +#define SLEN 0x001F +#define TXSE 0x0100 +#define TSFSE 0x0200 +#define TRFST 0x0400 + +/* SPORTx_RCR1 Masks */ +#define RSPEN 0x0001 +#define IRCLK 0x0002 +#define RDTYPE 0x000C +#define RULAW 0x0008 +#define RALAW 0x000C +#define RLSBIT 0x0010 +#define IRFS 0x0200 +#define RFSR 0x0400 +#define LRFS 0x1000 +#define LARFS 0x2000 +#define RCKFE 0x4000 + +/* SPORTx_RCR2 Masks */ +#define SLEN 0x001F +#define RXSE 0x0100 +#define RSFSE 0x0200 +#define RRFST 0x0400 + +/* SPORTx_STAT Masks */ +#define RXNE 0x0001 +#define RUVF 0x0002 +#define ROVF 0x0004 +#define TXF 0x0008 +#define TUVF 0x0010 +#define TOVF 0x0020 +#define TXHRE 0x0040 + +/* SPORTx_MCMC1 Masks */ +#define WSIZE 0x0000F000 +#define WOFF 0x000003FF + +/* SPORTx_MCMC2 Masks */ +#define MCCRM 0x00000003 +#define MCDTXPE 0x00000004 +#define MCDRXPE 0x00000008 +#define MCMEN 0x00000010 +#define FSDR 0x00000080 +#define MFD 0x0000F000 + +/* UART Controller Chapter 13 */ +#define UART_THR 0xFFC00400L +#define UART_RBR 0xFFC00400L +#define UART_DLL 0xFFC00400L +#define UART_IER 0xFFC00404L +#define UART_DLH 0xFFC00404L +#define UART_IIR 0xFFC00408L +#define UART_LCR 0xFFC0040CL +#define UART_MCR 0xFFC00410L +#define UART_LSR 0xFFC00414L +#define UART_SCR 0xFFC0041CL +#define UART_GCTL 0xFFC00424L + +/* + * UART CONTROLLER MASKS + */ + +/* UART_LCR */ +#define DLAB 0x80 +#define SB 0x40 +#define STP 0x20 +#define EPS 0x10 +#define PEN 0x08 +#define STB 0x04 +#define WLS(x) ((x-5) & 0x03) + +#define DLAB_P 0x07 +#define SB_P 0x06 +#define STP_P 0x05 +#define EPS_P 0x04 +#define PEN_P 0x03 +#define STB_P 0x02 +#define WLS_P1 0x01 +#define WLS_P0 0x00 + +/* UART_MCR */ +#define LOOP_ENA 0x10 +#define LOOP_ENA_P 0x04 + +/* UART_LSR */ +#define TEMT 0x40 +#define THRE 0x20 +#define BI 0x10 +#define FE 0x08 +#define PE 0x04 +#define OE 0x02 +#define DR 0x01 + +#define TEMP_P 0x06 +#define THRE_P 0x05 +#define BI_P 0x04 +#define FE_P 0x03 +#define PE_P 0x02 +#define OE_P 0x01 +#define DR_P 0x00 + +/* UART_IER */ +#define ELSI 0x04 +#define ETBEI 0x02 +#define ERBFI 0x01 + +#define ELSI_P 0x02 +#define ETBEI_P 0x01 +#define ERBFI_P 0x00 + +/* UART_IIR */ +#define STATUS(x) ((x << 1) & 0x06) +#define NINT 0x01 +#define STATUS_P1 0x02 +#define STATUS_P0 0x01 +#define NINT_P 0x00 + +/* UART_GCTL */ +#define FFE 0x20 +#define FPE 0x10 +#define RPOLC 0x08 +#define TPOLC 0x04 +#define IREN 0x02 +#define UCEN 0x01 + +#define FFE_P 0x05 +#define FPE_P 0x04 +#define RPOLC_P 0x03 +#define TPOLC_P 0x02 +#define IREN_P 0x01 +#define UCEN_P 0x00 + +/* General Purpose IO Chapter 14*/ +#define FIO_FLAG_D 0xFFC00700L +#define FIO_FLAG_C 0xFFC00704L +#define FIO_FLAG_S 0xFFC00708L +#define FIO_FLAG_T 0xFFC0070CL +#define FIO_MASKA_D 0xFFC00710L +#define FIO_MASKA_C 0xFFC00714L +#define FIO_MASKA_S 0xFFC00718L +#define FIO_MASKA_T 0xFFC0071CL +#define FIO_MASKB_D 0xFFC00720L +#define FIO_MASKB_C 0xFFC00724L +#define FIO_MASKB_S 0xFFC00728L +#define FIO_MASKB_T 0xFFC0072CL +#define FIO_DIR 0xFFC00730L +#define FIO_POLAR 0xFFC00734L +#define FIO_EDGE 0xFFC00738L +#define FIO_BOTH 0xFFC0073CL +#define FIO_INEN 0xFFC00740L + +/* General Purpose IO Masks */ +#define PF0 0x0001 +#define PF1 0x0002 +#define PF2 0x0004 +#define PF3 0x0008 +#define PF4 0x0010 +#define PF5 0x0020 +#define PF6 0x0040 +#define PF7 0x0080 +#define PF8 0x0100 +#define PF9 0x0200 +#define PF10 0x0400 +#define PF11 0x0800 +#define PF12 0x1000 +#define PF13 0x2000 +#define PF14 0x4000 +#define PF15 0x8000 + + +/* TIMER 0, 1, 2 Chapter 15 */ +#define TIMER0_CONFIG 0xFFC00600L +#define TIMER0_COUNTER 0xFFC00604L +#define TIMER0_PERIOD 0xFFC00608L +#define TIMER0_WIDTH 0xFFC0060CL + +#define TIMER1_CONFIG 0xFFC00610L +#define TIMER1_COUNTER 0xFFC00614L +#define TIMER1_PERIOD 0xFFC00618L +#define TIMER1_WIDTH 0xFFC0061CL + +#define TIMER2_CONFIG 0xFFC00620L +#define TIMER2_COUNTER 0xFFC00624L +#define TIMER2_PERIOD 0xFFC00628L +#define TIMER2_WIDTH 0xFFC0062CL + +#define TIMER_ENABLE 0xFFC00640L +#define TIMER_DISABLE 0xFFC00644L +#define TIMER_STATUS 0xFFC00648L + +/* Real Time Clock Chapter 16 */ +#define RTC_STAT 0xFFC00300L +#define RTC_ICTL 0xFFC00304L +#define RTC_ISTAT 0xFFC00308L +#define RTC_SWCNT 0xFFC0030CL +#define RTC_ALARM 0xFFC00310L +#define RTC_FAST 0xFFC00314L +#define RTC_PREN 0xFFC00314L + +/* RTC_FAST Mask (RTC_PREN Mask) */ +#define ENABLE_PRESCALE 0x00000001 +#define PREN 0x00000001 + +/* Asynchronous Memory Controller EBUI, Chapter 17*/ +#define EBIU_AMGCTL 0xFFC00A00L +#define EBIU_AMBCTL0 0xFFC00A04L +#define EBIU_AMBCTL1 0xFFC00A08L + +/* SDRAM Controller External Bus Interface Unit */ + +#define EBIU_SDGCTL 0xFFC00A10L +#define EBIU_SDBCTL 0xFFC00A14L +#define EBIU_SDRRC 0xFFC00A18L +#define EBIU_SDSTAT 0xFFC00A1CL + + + + +/* DCPLB_DATA and ICPLB_DATA Registers */ +/*** Bit Positions */ +#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ +#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */ +#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */ +/*** Masks */ +#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ +#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */ +#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */ +#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ +#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ +#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ +#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ +#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ +#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */ +/*** ICPLB_DATA only */ +#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */ +/*** DCPLB_DATA only */ +#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */ +#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */ +#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ +#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */ + /* 1= allocate cache lines on write-through writes. */ +#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ + + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_BFIN_H */ diff --git a/cpukit/score/cpu/bfin/rtems/bfin/bfin.h b/cpukit/score/cpu/bfin/rtems/bfin/bfin.h new file mode 100644 index 0000000000..2645648bed --- /dev/null +++ b/cpukit/score/cpu/bfin/rtems/bfin/bfin.h @@ -0,0 +1,85 @@ +/* bfin.h + * + * This file defines Macros for MMR register common to all Blackfin + * Processors. + * + * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. + * modified by Alain Schaefer <alain.schaefer@easc.ch> + * and Antonio Giovanini <antonio@atos.com.br> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + * + */ + +#ifndef _RTEMS_BFIN_BFIN_H +#define _RTEMS_BFIN_BFIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Scratchpad SRAM */ + +#define SCRATCH 0xFFB00000 +#define SCRATCH_SIZE 0x1000 +#define SCRATCH_TOP 0xFFB00ffc + + +/* System Interrupt Controller Chapter 4*/ +#define SIC_RVECT 0xFFC00108 +#define SIC_IMASK 0xFFC0010C +#define SIC_IAR0 0xFFC00110 +#define SIC_IAR1 0xFFC00114 +#define SIC_IAR2 0xFFC00118 +#define SIC_ISR 0xFFC00120 +#define SIC_IWR 0xFFC00124 + +/* Event Vector Table Chapter 4 */ + +#define EVT0 0xFFE02000 +#define EVT1 0xFFE02004 +#define EVT2 0xFFE02008 +#define EVT3 0xFFE0200C +#define EVT4 0xFFE02010 +#define EVT5 0xFFE02014 +#define EVT6 0xFFE02018 +#define EVT7 0xFFE0201C +#define EVT8 0xFFE02020 +#define EVT9 0xFFE02024 +#define EVT10 0xFFE02028 +#define EVT11 0xFFE0202C +#define EVT12 0xFFE02030 +#define EVT13 0xFFE02034 +#define EVT14 0xFFE02038 +#define EVT15 0xFFE0203C +#define IMASK 0xFFE02104 +#define IPEND 0xFFE02108 +#define ILAT 0xFFE0210C +#define IPRIO 0xFFE02110 + + +#define TCNTL 0xFFE03000 +#define TPERIOD 0xFFE03004 +#define TSCALE 0xFFE03008 +#define TCOUNT 0xFFE0300C + +/* Masks for Timer Control */ +#define TMPWR 0x00000001 +#define TMREN 0x00000002 +#define TAUTORLD 0x00000004 +#define TINT 0x00000008 + +/* Event Bit Positions */ +#define EVT_IVTMR_P 0x00000006 + +#define EVT_IVTMR (1 << EVT_IVTMR_P) + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_BFIN_H */ diff --git a/cpukit/score/cpu/bfin/rtems/score/bfin.h b/cpukit/score/cpu/bfin/rtems/score/bfin.h new file mode 100644 index 0000000000..7568205ae7 --- /dev/null +++ b/cpukit/score/cpu/bfin/rtems/score/bfin.h @@ -0,0 +1,65 @@ +/* bfin.h + * + * This file sets up basic CPU dependency settings based on + * compiler settings. For example, it can determine if + * floating point is available. This particular implementation + * is specified to the Blackfin port. + * + * + * COPYRIGHT (c) 1989-2006. + * On-Line Applications Research Corporation (OAR). + * modified by Alain Schaefer <alain.schaefer@easc.ch> + * and Antonio Giovanini <antonio@atos.com.br> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + * + */ + +#ifndef _RTEMS_SCORE_BFIN_H +#define _RTEMS_SCORE_BFIN_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* + * This file contains the information required to build + * RTEMS for a particular member of the Blackfin family. + * It does this by setting variables to indicate which + * implementation dependent features are present in a particular + * member of the family. + * + * This is a good place to list all the known CPU models + * that this port supports and which RTEMS CPU model they correspond + * to. + */ + +/* + * Figure out all CPU Model Feature Flags based upon compiler + * predefines. + */ +#if defined(__BFIN__) +#define CPU_MODEL_NAME "BF533" +#define BF_HAS_FPU 0 +#else + +#error "Unsupported CPU Model" + +#endif + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "BFIN" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_BFIN_H */ diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h b/cpukit/score/cpu/bfin/rtems/score/cpu.h new file mode 100644 index 0000000000..9974212018 --- /dev/null +++ b/cpukit/score/cpu/bfin/rtems/score/cpu.h @@ -0,0 +1,1264 @@ +/** + * @file rtems/score/cpu.h + */ + +/* + * This include file contains information pertaining to the Blackfin + * processor. + * + * COPYRIGHT (c) 1989-2006. + * On-Line Applications Research Corporation (OAR). + * adapted to Blackfin by Alain Schaefer <alain.schaefer@easc.ch> + * and Antonio Giovanini <antonio@atos.com.br> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rtems/score/types.h> +#include <rtems/score/bfin.h> + +/* conditional compilation parameters */ + +/** + * Should the calls to @ref _Thread_Enable_dispatch be inlined? + * + * If TRUE, then they are inlined. + * If FALSE, then a subroutine call is made. + * + * This conditional is an example of the classic trade-off of size + * versus speed. Inlining the call (TRUE) typically increases the + * size of RTEMS while speeding up the enabling of dispatching. + * + * @note In general, the @ref _Thread_Dispatch_disable_level will + * only be 0 or 1 unless you are in an interrupt handler and that + * interrupt handler invokes the executive.] When not inlined + * something calls @ref _Thread_Enable_dispatch which in turns calls + * @ref _Thread_Dispatch. If the enable dispatch is inlined, then + * one subroutine call is avoided entirely. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_INLINE_ENABLE_DISPATCH FALSE + +/** + * Should the body of the search loops in _Thread_queue_Enqueue_priority + * be unrolled one time? In unrolled each iteration of the loop examines + * two "nodes" on the chain being searched. Otherwise, only one node + * is examined per iteration. + * + * If TRUE, then the loops are unrolled. + * If FALSE, then the loops are not unrolled. + * + * The primary factor in making this decision is the cost of disabling + * and enabling interrupts (_ISR_Flash) versus the cost of rest of the + * body of the loop. On some CPUs, the flash is more expensive than + * one iteration of the loop body. In this case, it might be desirable + * to unroll the loop. It is important to note that on some CPUs, this + * code is the longest interrupt disable period in RTEMS. So it is + * necessary to strike a balance when setting this parameter. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE + +/** + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE + +/* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * BFIN Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/* + * Does the CPU follow the simple vectored interrupt model? + * + * If TRUE, then RTEMS allocates the vector table it internally manages. + * If FALSE, then the BSP is assumed to allocate and manage the vector + * table + * + * BFIN Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +/** + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/** + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + * + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ALLOCATE_INTERRUPT_STACK TRUE + +/** + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ISR_PASSES_FRAME_POINTER 1 + +/** + * @def CPU_HARDWARE_FP + * + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * If there is a FP coprocessor such as the i387 or mc68881, then + * the answer is TRUE. + * + * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + */ + +/** + * @def CPU_SOFTWARE_FP + * + * Does the CPU have no hardware floating point and GCC provides a + * software floating point implementation which must be context + * switched? + * + * This feature conditional is used to indicate whether or not there + * is software implemented floating point that must be context + * switched. The determination of whether or not this applies + * is very tool specific and the state saved/restored is also + * compiler specific. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#if ( BLACKFIN_CPU_HAS_FPU == 1 ) +#define CPU_HARDWARE_FP TRUE +#else +#define CPU_HARDWARE_FP FALSE +#endif +#define CPU_SOFTWARE_FP FALSE + +/** + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * So far, the only CPUs in which this option has been used are the + * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and + * gcc both implicitly used the floating point registers to perform + * integer multiplies. Similarly, the PowerPC port of gcc has been + * seen to allocate floating point local variables and touch the FPU + * even when the flow through a subroutine (like vfprintf()) might + * not use floating point formats. + * + * If a function which you would not think utilize the FP unit DOES, + * then one can not easily predict which tasks will use the FP hardware. + * In this case, this option should be TRUE. + * + * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ALL_TASKS_ARE_FP FALSE + +/** + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_IDLE_TASK_IS_FP FALSE + +/** + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_USE_DEFERRED_FP_SWITCH TRUE + +/** + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine @ref _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * @ref _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * -# BSP provided + * -# CPU dependent (if provided) + * -# generic (if no BSP and no CPU dependent) + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE + +/** + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_STACK_GROWS_UP FALSE + +/** + * The following is the variable attribute used to force alignment + * of critical RTEMS structures. On some processors it may make + * sense to have these aligned on tighter boundaries than + * the minimum requirements of the compiler in order to have as + * much of the critical data area as possible in a cache line. + * + * The placement of this macro in the declaration of the variables + * is based on the syntactically requirements of the GNU C + * "__attribute__" extension. For example with GNU C, use + * the following to force a structures to a 32 byte boundary. + * + * __attribute__ ((aligned (32))) + * + * @note Currently only the Priority Bit Map table uses this feature. + * To benefit from using this, the data must be heavily + * used so it will stay in the cache and used frequently enough + * in the executive to justify turning this on. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_STRUCTURE_ALIGNMENT + +/** + * @defgroup CPUEndian Processor Dependent Endianness Support + * + * This group assists in issues related to processor endianness. + */ + +/** + * @ingroup CPUEndian + * Define what is required to specify how the network to host conversion + * routines are handled. + * + * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the + * same values. + * + * @see CPU_LITTLE_ENDIAN + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_BIG_ENDIAN FALSE + +/** + * @ingroup CPUEndian + * Define what is required to specify how the network to host conversion + * routines are handled. + * + * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the + * same values. + * + * @see CPU_BIG_ENDIAN + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_LITTLE_ENDIAN TRUE + +/** + * @ingroup CPUInterrupt + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_MODES_INTERRUPT_MASK 0x00000001 + +/* + * Processor defined structures required for cpukit/score. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ + +/* may need to put some structures here. */ + +/** + * @defgroup CPUContext Processor Dependent Context Management + * + * From the highest level viewpoint, there are 2 types of context to save. + * + * -# Interrupt registers to save + * -# Task level registers to save + * + * Since RTEMS handles integer and floating point contexts separately, this + * means we have the following 3 context items: + * + * -# task level context stuff:: Context_Control + * -# floating point task stuff:: Context_Control_fp + * -# special interrupt level context :: CPU_Interrupt_frame + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ + +#ifndef ASM + +/** + * @ingroup CPUContext Management + * This defines the minimal set of integer and processor state registers + * that must be saved during a voluntary context switch from one thread + * to another. + */ + +/* make sure this stays in sync with the assembly function + __CPU_Context_switch in cpu_asm.S */ +typedef struct { + uint32_t register_r4; + uint32_t register_r5; + uint32_t register_r6; + uint32_t register_r7; + + uint32_t register_p3; + uint32_t register_p4; + uint32_t register_p5; + uint32_t register_fp; + uint32_t register_sp; + + uint32_t register_rets; + + uint32_t imask; +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->register_sp + +/** + * @ingroup CPUContext Management + * This defines the complete set of floating point registers that must + * be saved during any context switch from one thread to another. + */ +typedef struct { + /* FPU registers are listed here */ + /* Blackfin has no Floating Point */ +} Context_Control_fp; + +/** + * @ingroup CPUContext Management + * This defines the set of integer and processor state registers that must + * be saved during an interrupt. This set does not include any which are + * in @ref Context_Control. + */ +typedef struct { + /** This field is a hint that a port will have a number of integer + * registers that need to be saved when an interrupt occurs or + * when a context switch occurs at the end of an ISR. + */ + /*uint32_t special_interrupt_register;*/ +} CPU_Interrupt_frame; + +/** + * This variable is optional. It is used on CPUs on which it is difficult + * to generate an "uninitialized" FP context. It is filled in by + * @ref _CPU_Initialize and copied into the task's FP context area during + * @ref _CPU_Context_Initialize. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; + +/** + * @defgroup CPUInterrupt Processor Dependent Interrupt Management + * + * On some CPUs, RTEMS supports a software managed interrupt stack. + * This stack is allocated by the Interrupt Manager and the switch + * is performed in @ref _ISR_Handler. These variables contain pointers + * to the lowest and highest addresses in the chunk of memory allocated + * for the interrupt stack. Since it is unknown whether the stack + * grows up or down (in general), this give the CPU dependent + * code the option of picking the version it wants to use. + * + * @note These two variables are required if the macro + * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ + +/* + * Nothing prevents the porter from declaring more CPU specific variables. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ + +/* XXX: if needed, put more variables here */ + +/** + * @ingroup CPUContext + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +#endif /* ASM */ + +/** + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/** + * @ingroup CPUInterrupt + * This defines the number of entries in the @ref _ISR_Vector_table managed + * by RTEMS. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 16 + +/** + * @ingroup CPUInterrupt + * This defines the highest interrupt vector number for this port. + */ +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) + +/** + * @ingroup CPUInterrupt + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable @a _ISR_Nest_level. + */ +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/** + * @ingroup CPUContext + * Should be large enough to run all RTEMS tests. This ensures + * that a "reasonable" small application should not have any problems. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_STACK_MINIMUM_SIZE (1024*4) + +/** + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_ALIGNMENT 8 + +/** + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by @ref CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for + * the heap, then this should be set to @ref CPU_ALIGNMENT. + * + * @note This does not have to be a power of 2 although it should be + * a multiple of 2 greater than or equal to 2. The requirement + * to be a multiple of 2 is because the heap uses the least + * significant field of the front and back flags to indicate + * that a block is in use or free. So you do not want any odd + * length blocks really putting length data in that bit. + * + * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will + * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that + * elements allocated from the heap meet all restrictions. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/** + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * @ref CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is + * strict enough for the partition, then this should be set to + * @ref CPU_ALIGNMENT. + * + * @note This does not have to be a power of 2. It does have to + * be greater or equal to than @ref CPU_ALIGNMENT. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/** + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by @ref CPU_ALIGNMENT. If the + * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be + * set to 0. + * + * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define CPU_STACK_ALIGNMENT 0 + +/* + * ISR handler macros + */ + +/** + * @ingroup CPUInterrupt + * Support routine to initialize the RTEMS vector table after it is allocated. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Initialize_vectors() + +/** + * @ingroup CPUInterrupt + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in @a _isr_cookie. + * + * @param[out] _isr_cookie will contain the previous level cookie + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Disable( _level ) \ + { \ + __asm__ volatile ("cli %0; csync \n" : "=d" (_level) ); \ + } + + +/** + * @ingroup CPUInterrupt + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * @a _isr_cookie is not modified. + * + * @param[in] _isr_cookie contain the previous level cookie + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Enable( _level ) { \ + __asm__ __volatile__ ("sti %0; csync \n" : : "d" (_level) ); \ + } + +/** + * @ingroup CPUInterrupt + * This temporarily restores the interrupt to @a _isr_cookie before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter @a _isr_cookie is not + * modified. + * + * @param[in] _isr_cookie contain the previous level cookie + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Flash( _level ) { \ + __asm__ __volatile__ ("sti %0; csync; cli r0; csync" \ + : : "d"(_level) : "R0" ); \ + } + +/** + * @ingroup CPUInterrupt + * + * This routine and @ref _CPU_ISR_Get_level + * Map the interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + * This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_ISR_Set_level( _new_level ) \ + { \ + __asm__ __volatile__ ( "sti %0; csync" : : "d"(_new_level ? 0 : 0xffff) ); \ + } + +#ifndef ASM + +/** + * @ingroup CPUInterrupt + * Return the current interrupt disable level for this task in + * the format used by the interrupt level portion of the task mode. + * + * @note This routine usually must be implemented as a subroutine. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* Context handler macros */ + +/** + * @ingroup CPUContext + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * @param[in] _the_context is the context structure to be initialized + * @param[in] _stack_base is the lowest physical address of this task's stack + * @param[in] _size is the size of this task's stack + * @param[in] _isr is the interrupt disable level + * @param[in] _entry_point is the thread's entry point. This is + * always @a _Thread_Handler + * @param[in] _is_fp is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + * + * Port Specific Information: + * + * See implementation in cpu.c + */ +void _CPU_Context_Initialize( + Context_Control *the_context, + uint32_t *stack_base, + uint32_t size, + uint32_t new_level, + void *entry_point, + bool is_fp +); + +/** + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. For many ports, simply adding a label to the restore path + * of @ref _CPU_Context_switch will work. On other ports, it may be + * possibly to load a few arguments and jump to the restore path. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/** + * @ingroup CPUContext + * The purpose of this macro is to allow the initial pointer into + * a floating point context area (used to save the floating point + * context) to be at an arbitrary place in the floating point + * context area. + * + * This is necessary because some FP units are designed to have + * their context saved as a stack which grows into lower addresses. + * Other FP units can be saved by simply moving registers into offsets + * from the base of the context area. Finally some FP units provide + * a "dump context" instruction which could fill in from high to low + * or low to high based on the whim of the CPU designers. + * + * @param[in] _base is the lowest physical address of the floating point + * context area + * @param[in] _offset is the offset into the floating point area + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Context_Fp_start( _base, _offset ) \ + ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) + +/** + * This routine initializes the FP context area passed to it to. + * There are a few standard ways in which to initialize the + * floating point context. The code included for this macro assumes + * that this is a CPU in which a "initial" FP context was saved into + * @a _CPU_Null_fp_context and it simply copies it to the destination + * context passed to it. + * + * Other floating point context save/restore models include: + * -# not doing anything, and + * -# putting a "null FP status word" in the correct place in the FP context. + * + * @param[in] _destination is the floating point context area + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Context_Initialize_fp( _destination ) \ + { \ + *(*(_destination)) = _CPU_Null_fp_context; \ + } + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/** + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#define _CPU_Fatal_halt( _error ) \ + { \ + __asm__ volatile ( "cli R1; \ + R1 = %0; \ + _halt: \ + idle; \ + jump _halt;"\ + : : "r" (_error) ); \ + } + +/* end of Fatal Error manager macros */ + +/* Bitfield handler macros */ + +/** + * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation + * + * This set of routines are used to implement fast searches for + * the most important ready task. + */ + +/** + * @ingroup CPUBitfield + * This definition is set to TRUE if the port uses the generic bitfield + * manipulation implementation. + */ +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +/** + * @ingroup CPUBitfield + * This definition is set to TRUE if the port uses the data tables provided + * by the generic bitfield manipulation implementation. + * This can occur when actually using the generic bitfield manipulation + * implementation or when implementing the same algorithm in assembly + * language for improved performance. It is unlikely that a port will use + * the data if it has a bitfield scan instruction. + */ +#define CPU_USE_GENERIC_BITFIELD_DATA TRUE + +/** + * @ingroup CPUBitfield + * This routine sets @a _output to the bit number of the first bit + * set in @a _value. @a _value is of CPU dependent type + * @a Priority_bit_map_Control. This type may be either 16 or 32 bits + * wide although only the 16 least significant bits will be used. + * + * There are a number of variables in using a "find first bit" type + * instruction. + * + * -# What happens when run on a value of zero? + * -# Bits may be numbered from MSB to LSB or vice-versa. + * -# The numbering may be zero or one based. + * -# The "find first bit" instruction may search from MSB or LSB. + * + * RTEMS guarantees that (1) will never happen so it is not a concern. + * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and + * @ref _CPU_Priority_bits_index. These three form a set of routines + * which must logically operate together. Bits in the _value are + * set and cleared based on masks built by @ref _CPU_Priority_Mask. + * The basic major and minor values calculated by @ref _Priority_Major + * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index + * to properly range between the values returned by the "find first bit" + * instruction. This makes it possible for @ref _Priority_Get_highest to + * calculate the major and directly index into the minor table. + * This mapping is necessary to ensure that 0 (a high priority major/minor) + * is the first bit found. + * + * This entire "find first bit" and mapping process depends heavily + * on the manner in which a priority is broken into a major and minor + * components with the major being the 4 MSB of a priority and minor + * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest + * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next + * to the lowest priority. + * + * If your CPU does not have a "find first bit" instruction, then + * there are ways to make do without it. Here are a handful of ways + * to implement this in software: + * +@verbatim + - a series of 16 bit test instructions + - a "binary search using if's" + - _number = 0 + if _value > 0x00ff + _value >>=8 + _number = 8; + + if _value > 0x0000f + _value >=8 + _number += 4 + + _number += bit_set_table[ _value ] +@endverbatim + + * where bit_set_table[ 16 ] has values which indicate the first + * bit set + * + * @param[in] _value is the value to be scanned + * @param[in] _output is the first bit set + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + { \ + __asm__ ("bit(1);"): + (_output) = 0; /* do something to prevent warnings */ \ + } +#endif + +/* end of Bitfield handler macros */ + +/** + * This routine builds the mask which corresponds to the bit fields + * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion + * for that routine. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Priority_Mask( _bit_number ) \ + ( 1 << (_bit_number) ) + +#endif + +/** + * @ingroup CPUBitfield + * This routine translates the bit numbers returned by + * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as + * a major or minor component of a priority. See the discussion + * for that routine. + * + * @param[in] _priority is the major or minor number to translate + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Priority_bits_index( _priority ) \ + (_priority) + +#endif + +/* end of Priority handler macros */ + +/* functions */ + +/** + * This routine performs CPU dependent initialization. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Initialize(void); + +/** + * @ingroup CPUInterrupt + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + * + * @param[in] vector is the vector number + * @param[in] new_handler is the raw ISR handler to install + * @param[in] old_handler is the previously installed ISR Handler + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/** + * @ingroup CPUInterrupt + * This routine installs an interrupt vector. + * + * @param[in] vector is the vector number + * @param[in] new_handler is the RTEMS ISR handler to install + * @param[in] old_handler is the previously installed ISR Handler + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/** + * @ingroup CPUInterrupt + * This routine installs the hardware interrupt stack pointer. + * + * @note It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Install_interrupt_stack( void ); + +/** + * This routine is the CPU dependent IDLE thread body. + * + * @note It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +/** + * @ingroup CPUContext + * This routine switches from the run context to the heir context. + * + * @param[in] run points to the context of the currently executing task + * @param[in] heir points to the context of the heir task + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/** + * @ingroup CPUContext + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in @ref _CPU_Context_switch. + * + * @param[in] new_context points to the context to be restored. + * + * @note May be unnecessary to reload some registers. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; + +/** + * @ingroup CPUContext + * This routine saves the floating point context passed to it. + * + * @param[in] fp_context_ptr is a pointer to a pointer to a floating + * point context area + * + * @return on output @a *fp_context_ptr will contain the address that + * should be used with @ref _CPU_Context_restore_fp to restore this context. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); + +/** + * @ingroup CPUContext + * This routine restores the floating point context passed to it. + * + * @param[in] fp_context_ptr is a pointer to a pointer to a floating + * point context area to restore + * + * @return on output @a *fp_context_ptr will contain the address that + * should be used with @ref _CPU_Context_save_fp to save this context. + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); + +/** + * @ingroup CPUEndian + * The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to ensure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + * + * @param[in] value is the value to be swapped + * @return the value after being endian swapped + * + * Port Specific Information: + * + * XXX document implementation including references if appropriate + */ +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return( swapped ); +} + +/** + * @ingroup CPUEndian + * This routine swaps a 16 bir quantity. + * + * @param[in] value is the value to be swapped + * @return the value after being endian swapped + */ +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h b/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h new file mode 100644 index 0000000000..a4c7be9a5e --- /dev/null +++ b/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h @@ -0,0 +1,27 @@ +/** + * @file rtems/score/cpu_asm.h + */ + +/* + * Defines a couple of Macros used in cpu_asm.S + * + * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. + * written by Alain Schaefer <alain.schaefer@easc.ch> + * and Antonio Giovanini <antonio@atos.com.br> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + * + */ + +#ifndef _RTEMS_SCORE_CPU_ASM_H +#define _RTEMS_SCORE_CPU_ASM_H + + + +#endif + +/* end of file */ diff --git a/cpukit/score/cpu/bfin/rtems/score/types.h b/cpukit/score/cpu/bfin/rtems/score/types.h new file mode 100644 index 0000000000..bf833974ed --- /dev/null +++ b/cpukit/score/cpu/bfin/rtems/score/types.h @@ -0,0 +1,45 @@ +/* + * This include file contains type definitions pertaining to the + * Blackfin processor family. + * + * COPYRIGHT (c) 1989-2006. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include <rtems/score/basedefs.h> + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +/** This defines the type for a priority bit map entry. */ +typedef uint16_t Priority_bit_map_Control; + +/** This defines the return type for an ISR entry point. */ +typedef void blackfin_isr; + +/** This defines the prototype for an ISR entry point. */ +typedef blackfin_isr ( *blackfin_isr_entry )( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif |