diff options
Diffstat (limited to 'cpukit/score/cpu/arm')
| -rw-r--r-- | cpukit/score/cpu/arm/.cvsignore | 2 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/ChangeLog | 655 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/Makefile.am | 22 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/arm_exc_abort.S | 135 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/arm_exc_handler_high.c | 121 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/arm_exc_handler_low.S | 164 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/arm_exc_interrupt.S | 177 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/cpu.c | 125 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/cpu_asm.S | 80 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/preinstall.am | 45 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/rtems/asm.h | 178 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/rtems/score/arm.h | 98 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/rtems/score/cpu.h | 495 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/rtems/score/cpu_asm.h | 41 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/rtems/score/types.h | 55 |
15 files changed, 2393 insertions, 0 deletions
diff --git a/cpukit/score/cpu/arm/.cvsignore b/cpukit/score/cpu/arm/.cvsignore new file mode 100644 index 0000000000..282522db03 --- /dev/null +++ b/cpukit/score/cpu/arm/.cvsignore @@ -0,0 +1,2 @@ +Makefile +Makefile.in diff --git a/cpukit/score/cpu/arm/ChangeLog b/cpukit/score/cpu/arm/ChangeLog new file mode 100644 index 0000000000..7edf0ce295 --- /dev/null +++ b/cpukit/score/cpu/arm/ChangeLog @@ -0,0 +1,655 @@ +2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org> + + * cpu.c, rtems/score/cpu.h: + Use "__asm__" instead of "asm" for improved c99-compliance. + +2010-11-23 Gedare Bloom <giddyup44@yahoo.com> + + PR 1719/cpukit + * arm_exc_abort.S: Avoid "bx" instruction to support ARMv4 and below. + +2010-11-22 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/score/cpu.h: Set alignment requirements according to AAPCS. + +2010-07-29 Gedare Bloom <giddyup44@yahoo.com> + + PR 1635/cpukit + * rtems/score/types.h: Refactoring of priority handling, to isolate the + bitmap implementation of priorities in the supercore so that priority + management is a little more modular. This change is in anticipation + of scheduler implementations that can select how they manage tracking + priority levels / finding the highest priority ready task. Note that + most of the changes here are simple renaming, to clarify the use of + the bitmap-based priority management. + +2010-07-16 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/score/cpu.h: Include <rtems/score/types.h> first. + * rtems/score/types.h: Use <rtems/score/basedefs.h> header file. + +2010-07-06 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/score/cpu.h: Removed CPU_ENABLE_C_ISR_DISPATCH_IMPLEMENTATION + define. + +2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com> + + PR 1573/cpukit + * arm_exc_interrupt.S: Add a per cpu data structure which contains the + information required by RTEMS for each CPU core. This encapsulates + information such as thread executing, heir, idle and dispatch needed. + +2010-05-10 Joel Sherrill <joel.sherrilL@OARcorp.com> + + * rtems/score/arm.h: Make it a warning not error that the FPU multilib + is not supported yet. + +2010-04-08 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * arm_exc_abort.S, arm_exc_handler_high.c, arm_exc_handler_low.S, + arm_exc_interrupt.S, cpu.c, cpu_asm.S, rtems/asm.h, rtems/score/arm.h, + rtems/score/cpu.h, rtems/score/cpu_asm.h, rtems/score/types.h: + Documentation. + +2010-04-07 Joel Sherrill <joel.sherrill@oarcorp.com> + + * arm_exc_abort.S: Fix warnings about TRUE/FALSE not defined. + +2010-03-27 Joel Sherrill <joel.sherrill@oarcorp.com> + + * arm_exc_abort.S, arm_exc_handler_high.c, arm_exc_handler_low.S, + arm_exc_interrupt.S, cpu.c, cpu_asm.S: Add include of config.h + +2010-01-12 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * arm_exc_abort.S: New file. + * Makefile.am: Update for new file. + * arm_exc_interrupt.S, cpu.c, rtems/asm.h, rtems/score/cpu.h: Changed + macros which switch from and to THUMB mode. Added a default prefetch + and data abort handler which reports the complete processor context. + Added PSR defines. + +2009-12-15 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/score/arm.h: Recognize ARMv5TEJ. + * arm_exc_interrupt.S: The previous implementation was broken. In + case of a nested interrupt the link register of the INT mode was not + properly restored. This lead to a major rewrite. Interrupt + processing is now done in SVC mode. + +2009-10-01 Joel Sherrill <joel.sherrill@oarcorp.com> + + * rtems/score/arm.h: Recognize ARMv7A. + +2009-10-01 Joel Sherrill <joel.sherrill@oarcorp.com> + + * rtems/score/arm.h: Recognize ARMv6J as needed by arm1136 variants. + +2009-09-15 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/score/cpu.h: Fix for inline asm in _CPU_Fatal_halt(). + * rtems/asm.h: Added macro to define ARM functions. + * cpu_asm.S, arm_exc_handler_low.S: Use macro from above. + +2009-08-19 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Mark _CPU_Context_restore() as noreturn so the + compiler will not generate code thinking it returns. + +2009-07-15 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * arm_exc_handler_high.c, arm_exc_handler_low.S, arm_exc_interrupt.S: + New files. + * Makefile.am: Update. + * rtems/score/cpu.h: Removed all generic comments. Changed inline + assembler of interrupt support functions. Removed operating system + support for fast interrupts (FIQ). Overall cleanup. + * cpu.c: Changed type of arm_cpu_mode to uint32_t to match the type in + _CPU_Context_Initialize(). Moved exception handler code into + 'arm_exc_handler_high.c'. _CPU_ISR_install_vector() writes now only + if necessary. + * cpu_asm.S: Moved exception handler code into 'arm_exc_handler_low.S'. + * rtems/score/types.h: Removed superfluous defines. + * ChangeLog, thumb_isr.c: Removed files. + +2009-05-05 Joel Sherrill <joel.sherrill@oarcorp.com> + + * rtems/score/cpu.h: Remove warnings. + +2009-02-11 Joel Sherrill <joel.sherrill@oarcorp.com> + + * cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and + passing address of _Thread_Dispatch to _CPU_Initialize. Clean up + comments. + +2008-09-11 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: Do not define boolean, single_precision, + double_precision unless RTEMS_DEPRECATED_TYPES is given. + +2008-09-08 Joel Sherrill <joel.sherrill@oarcorp.com> + + * cpu.c: Remove extraneous spaces. + +2008-09-07 Ralf Corsépius <ralf.corsepius@rtems.org> + + * Makefile.am: Merge thumb/Makefile.am. + * thumb/Makefile.am: Remove (superfluous). + +2008-09-05 Ralf Corsépius <ralf.corsepius@rtems.org> + + * cpu.c, rtems/score/cpu.h: Convert to "bool". + +2008-08-21 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: Include stdbool.h. + Use bool as base-type for boolean. + +2008-08-18 Joel Sherrill <joel.sherrill@OARcorp.com> + + * cpu.c, rtems/score/cpu.h: Add void. + +2008-04-18 Joel Sherrill <joel.sherrill@OARcorp.com> + + * cpu.c: Add comment. + +2008-04-17 Joel Sherrill <joel.sherrill@oarcorp.com> + + * cpu.c: Add arm_cpu_mode so ARM BSP can overrid default value for + cpsr. + +2007-12-17 Joel Sherrill <joel.sherrill@oarcorp.com> + + * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility. + +2007-12-17 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu_asm.h: Sweep to make sure grep for COPYRIGHT passes. + +2007-12-11 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Temporarily use C implementation of swap u32 for + thumb mode. + +2007-12-04 Joel Sherrill <joel.sherrill@OARcorp.com> + + * cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU + Table to Configuration Table. Eliminate CPU Table from all ports. + Delete references to CPU Table in all forms. + +2007-12-03 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Moved most of the remaining CPU Table fields to + the Configuration Table. This included pretasking_hook, + predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace, + extra_mpci_receive_server_stack, stack_allocate_hook, and + stack_free_hook. As a side-effect of this effort some multiprocessing + code was made conditional and some style clean up occurred. + +2007-11-27 Joel Sherrill <joel.sherrill@OARcorp.com> + + * rtems/score/cpu.h: Do not inline _Thread_Enable_dispatch for Thumb to + save space. + +2007-11-26 Ray Xu <rayx.cn@gmail.com> + + * cpu.c, score/cpu.h: Fix headers. Remove extra inline definition. + * cpu_asm.S: Note origin of Thumb support. + +2007-11-06 Joel Sherrill <joel.sherrill@OARcorp.com> + + * cpu.c: Fix headers. + +2007-11-03 Ray Xu <rayx.cn@gmail.com> + + * cpu.c, cpu_asm.S, score/cpu.h : add support for ARM<->THUMB veneer + thumb new dir to controll CPSR/SPRS in thumb mode + +2007-05-09 Ray Xu <rayx.cn@gmail.com> + + * cpu.c: move do_data_abort() to libbsp/arm/shared/abort/ + implement a compact do_data_abort() in simple_abort.c + +2007-05-09 Ray Xu <rayx@gmail.com> + + * cpu.c: move do_data_abort() to libbsp/arm/shared/abort/ + implement a compact do_data_abort() in simple_abort.c + +2007-05-09 Ray Xu <rayx@gmail.com> + + * cpu.c: move do_data_abort() to libbsp/arm/shared/abort/ + implement a compact do_data_abort() in simple_abort.c + +2007-05-09 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES. + +2007-04-17 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/score/cpu.h: + Use Context_Control_fp* instead of void* for fp_contexts. + Eliminate evil casts. + +2006-11-17 Ralf Corsépius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: Remove unsigned64, signed64. + +2006-09-11 Joel Sherrill <joel@OARcorp.com> + + * cpu.c: Remove warning. + +2006-06-02 Jay Monkman <jtm@lopingdog.com> + + * cpu.c, cpu_asm.S: Fixed ARM Data Abort handling. + +2005-11-08 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: Eliminate unsigned16, unsigned32. + +2005-10-27 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/asm.h: Remove private version of CONCAT macros. + Include <rtems/concat.h> instead. + +2005-09-15 Jay Monkman <jtm@lopingdog.com> + + PR 365/rtems + * rtems/score/arm.h, rtems/score/cpu.h: Removed unused ARM_HAS_CLZ + macro. + +2005-02-08 Ralf Corsepius <ralf.corsepius@rtems.org> + + * Makefile.am: Split out preinstallation rules. + * preinstall.am: New (Split out from Makefile.am). + +2005-02-04 Ralf Corsepius <ralf.corsepius@rtems.org> + + PR 754/rtems + * rtems/asm.h: New (relocated from .). + * asm.h: Remove (moved to rtems/asm.h). + * Makefile.am: Reflect changes above. + +2004-01-28 Ralf Corsepius <ralf.corsepiu@rtems.org> + + * asm.h, rtems/score/arm.h, rtems/score/cpu.h, + rtems/score/cpu_asm.h, rtems/score/types.h: New header guards. + +2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: Remove signed8, signed16, signed32, + unsigned8, unsigned16, unsigned32. + +2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/cpu.h: *_swap_u32( uint32_t ). + +2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: #include <rtems/stdint.h>. + +2005-01-07 Ralf Corsepius <ralf.corsepius@rtems.org> + + * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V. + +2005-01-01 Ralf Corsepius <ralf.corsepius@rtems.org> + + * Makefile.am: Remove build-variant support. + +2004-11-21 Ralf Corsepius <ralf.corsepius@rtems.org> + + * rtems/score/types.h: Use __rtems_score_types_h as preprocessor + guard. + +2004-11-21 Ralf Corsepius <ralf.corsepius@rtems.org> + + * asm.h: Add doxygen preamble. + +2004-10-02 Ralf Corsepius <ralf_corsepius@rtems.org> + + * rtems/score/arm.h: Add doxygen preamble. + * rtems/score/cpu.h: Add doxygen preamble. + * rtems/score/cpu_asm.h: Add doxygen preamble. + * rtems/score/types.h: Add doxygen preamble. + +2004-09-29 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: i960 obsoleted and all references removed. + +2004-08-19 Jay Monkman <jtm@lopingdog.com> + + PR 671/bsps + * rtems/score/cpu.h: Fixed bug in _CPU_ISR_Set_level, where input param + was always ignored. + +2004-04-09 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: Fix typo. + +2004-04-06 Ralf Corsepius <ralf_corsepius@rtems.org> + + * configure.ac: Remove (Merged into $(top_srcdir)/configure.ac). + * Makefile.am: Don't include multilib.am. + Reflect merging configure.ac into $(top_srcdir)/configure.ac. + +2004-04-01 Ralf Corsepius <ralf_corsepius@rtems.org> + + * Makefile.am: Install asm.h to $(includedir)/rtems. + +2004-04-01 Ralf Corsepius <ralf_corsepius@rtems.org> + + * cpu_asm.S: Include <rtems/asm.h> instead of <asm.h>. + +2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> + + * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types. + +2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org> + + * configure.ac: RTEMS_TOP([../../../..]). + +2004-01-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Move RTEMS_TOP one subdir down. + +2004-01-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Add PREINSTALL_DIRS. + +2004-01-14 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Re-add dirstamps to PREINSTALL_FILES. + Add PREINSTALL_FILES to CLEANFILES. + +2004-01-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Requires automake >= 1.8.1. + +2004-01-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Include compile.am, again. + +2004-01-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Convert to using automake compilation rules. + +2003-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Use mkdir_p. Remove dirs from PREINSTALL_FILES. + +2003-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Require automake >= 1.8, autoconf >= 2.59. + +2003-12-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Remove TMPINSTALL_FILES. + +2003-11-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Add $(dirstamp) to preinstallation rules. + +2003-11-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Add $(dirstamp) to preinstallation rules. + +2003-11-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Don't use gmake rules for preinstallation. + +2003-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Remove RTEMS_CANONICAL_HOST. + +2003-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Remove RTEMS_CHECK_CPU. + +2003-09-26 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: Obsoleting HP PA-RISC port and removing all + references. + +2003-09-04 Joel Sherrill <joel@OARcorp.com> + + * asm.h, cpu.c, cpu_asm.S, rtems/score/arm.h, rtems/score/cpu.h, + rtems/score/cpu_asm.h, rtems/score/types.h: URL for license changed. + +2003-08-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Use rtems-bugs@rtems.com as bug report email address. + +2003-04-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Use "all-local:" instead of "all:". + +2003-03-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Remove AC_CONFIG_AUX_DIR. + +2003-03-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * rtems/score/arm.h: Remove ARM_HAS_THUMB (Unused). + +2003-03-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * rtems/score/cpu.h: Set up CPU_*_ENDIAN based on -D__ARMEL__ and + -D__ARMEB__. Fix minor typo in comment. + +2003-02-26 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * rtems/score/arm.h: Set up ARM_HAS_FPU based on -D__SOFTFP__. + +2002-12-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Require autoconf-2.57 + automake-1.7.2. + * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS. + +2002-11-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Fix package name. + +2002-11-04 Joel Sherrill <joel@OARcorp.com> + + * cpu.c: Removed warning. + +2002-11-01 Joel Sherrill <joel@OARcorp.com> + + * cpu.c: Removed warnings. + +2002-10-31 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: Removed warning. + +2002-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE. + +2002-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * .cvsignore: Reformat. + Add autom4te*cache. + Remove autom4te.cache. + +2002-10-04 Jay Monkman <jtm@smoothsmoothie.com> + + * rtems/score/cpu.h: Fix u16 and u32 swap routines. + +2002-08-05 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h, rtems/score/types.h: Updated to fix some typos. + +2002-07-30 Jay Monkman <jtm@smoothsmoothie.com> + + * cpu.c, cpu_asm.S, rtems/score/arm.h, rtems/score/cpu.h, + rtems/score/cpu_asm.h, rtems/score/types.h: ARM port works + well enough to run all sptests, tmtests, and ttcp. + In addition to general cleanup, there has been considerable + optimization to interrupt disable/enable, endian swapping, + and context switching. + +2002-07-26 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Build libscorecpu.a instead of rtems-cpu.rel. + +2002-07-22 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Use .$(OBJEXT) instead of .o. + +2002-07-22 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Use . instead of .o. + +2002-07-17 Jay Monkman <jtm@smoothsmoothie.com> + + * rtems/score/cpu_asm.h: Enhanced to include register offsets. + * Makefile.am: Install rtems/score/cpu_asm.h. + * cpu.c: Significantly enhanced including the implementation of + _CPU_ISR_Get_level. + * cpu_asm.S: Improved behavior of context switch and interrupt + dispatching. + * rtems/score/arm.h: Improved the CPU model name determination. + * rtems/score/cpu.h: Improved interrupt disable/enable functions. + +2002-07-05 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: Filled in something that was marked XXX. + +2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: RTEMS_TOP(../../../..). + +2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * rtems.c: Remove. + * Makefile.am: Reflect changes above. + +2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Remove RTEMS_PROJECT_ROOT. + +2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Add RTEMS_PROG_CCAS + +2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). + Add AC_PROG_RANLIB. + +2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. + Use ../../../aclocal. + +2002-04-18 Jay Monkman <jtm@smoothsmoothie.com> + + * rtems/score/cpu.h (CPU_ISR_Disable and CPU_ISR_Enable): Correct them + where they correctly inform the compiler about the register they + are modifying. + +2001-04-03 Joel Sherrill <joel@OARcorp.com> + + * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. + * rtems/score/a29ktypes.h: Removed. + * rtems/score/types.h: New file via CVS magic. + * Makefile.am, rtems/score/cpu.h: Account for name change. + +2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: + AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). + AM_INIT_AUTOMAKE([no-define foreign 1.6]). + * Makefile.am: Remove AUTOMAKE_OPTIONS. + +2001-02-04 Joel Sherrill <joel@OARcorp.com> + + * configure.ac: Removed references to rtems/Makefile and + rtems/score/Makefile. + +2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * rtems/Makefile.am: Removed. + * rtems/score/Makefile.am: Removed. + * configure.ac: Reflect changes above. + * Makefile.am: Reflect changes above. + +2002-02-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP. + +2002-01-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * cpu.c: Include rtems/bspIo.h instead of bspIo.h. + +2001-12-20 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Use RTEMS_ENV_RTEMSCPU. + +2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Add multilib support. + +2001-12-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * asm.h: include cpuopts.h instead of targopts.h + * rtems/score/arm.h: Use __arm__. + +2001-11-28 Joel Sherrill <joel@OARcorp.com>, + + This was tracked as PR91. + * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which + is used to specify if the port uses the standard macro for this (FALSE). + A TRUE setting indicates the port provides its own implementation. + +2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * .cvsignore: Add autom4te.cache for autoconf > 2.52. + * configure.in: Remove. + * configure.ac: New file, generated from configure.in by autoupdate. + +2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. + * Makefile.am: Use 'PREINSTALL_FILES ='. + +2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am, rtems/score/Makefile.am: + Apply include_*HEADERS instead of H_FILES. + +2001-01-03 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). + +2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. + +2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. + +2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. + Switch to GNU canonicalization. + +2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Include compile.am, formatting. + * rtems/Makefile.am: Formatting. + * rtems/score/Makefile.am: Formatting. + +2000-08-29 Joel Sherrill <joel.sherrill@OARcorp.com> + + * cpu.c: Spacing issues. + * rtems/score/cpu.h: Removed warning by setting _level. + +2000-08-29 Joel Sherrill <joel.sherrill@OARcorp.com> + + * Makefile.am: Added S_O_FILES to list of objects. + +2000-08-10 Joel Sherrill <joel@OARcorp.com> + + * ChangeLog: New file. diff --git a/cpukit/score/cpu/arm/Makefile.am b/cpukit/score/cpu/arm/Makefile.am new file mode 100644 index 0000000000..57f2b70642 --- /dev/null +++ b/cpukit/score/cpu/arm/Makefile.am @@ -0,0 +1,22 @@ +## +## $Id$ +## +include $(top_srcdir)/automake/compile.am +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/cpu_asm.h \ + rtems/score/arm.h rtems/score/types.h + +noinst_LIBRARIES = libscorecpu.a +libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) +libscorecpu_a_SOURCES = cpu.c \ + cpu_asm.S \ + arm_exc_abort.S \ + arm_exc_interrupt.S \ + arm_exc_handler_low.S \ + arm_exc_handler_high.c + +include $(srcdir)/preinstall.am +include $(top_srcdir)/automake/local.am diff --git a/cpukit/score/cpu/arm/arm_exc_abort.S b/cpukit/score/cpu/arm/arm_exc_abort.S new file mode 100644 index 0000000000..cd2491fb14 --- /dev/null +++ b/cpukit/score/cpu/arm/arm_exc_abort.S @@ -0,0 +1,135 @@ +/** + * @file + * + * @ingroup ScoreCPU + * + * @brief ARM data and prefetch abort exception prologue and epilogue. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/asm.h> +#include <rtems/system.h> + +.extern rtems_fatal_error_occurred + +.globl arm_exc_data_abort_set_handler +.globl arm_exc_data_abort + +.globl arm_exc_prefetch_abort_set_handler +.globl arm_exc_prefetch_abort + +.section ".bss" + +data_abort_handler: +.long 0 + +prefetch_abort_handler: +.long 0 + +.section ".text" + +#ifdef __thumb__ + .thumb_func +#endif + +arm_exc_data_abort_set_handler: + ldr r1, =data_abort_handler + str r0, [r1] +#ifdef __thumb__ + bx lr +#else + mov pc, lr +#endif + +#ifdef __thumb__ + .thumb_func +#endif + +arm_exc_prefetch_abort_set_handler: + ldr r1, =prefetch_abort_handler + str r0, [r1] +#ifdef __thumb__ + bx lr +#else + mov pc, lr +#endif + +.arm + +arm_exc_prefetch_abort: + + /* Save context and load handler */ + sub sp, #16 + stmdb sp!, {r0-r12} + ldr r6, =prefetch_abort_handler + + b save_more_context + +arm_exc_data_abort: + + /* Save context and load handler */ + sub sp, #16 + stmdb sp!, {r0-r12} + ldr r6, =data_abort_handler + +save_more_context: + + /* Save more context */ + mov r2, lr + mrs r3, spsr + mrs r4, cpsr + orr r5, r3, #ARM_PSR_I + bic r5, #ARM_PSR_T + msr cpsr, r5 + mov r0, sp + mov r1, lr + msr cpsr, r4 + add r5, sp, #68 + stmdb r5!, {r0-r3} + + /* Call high level handler */ + ldr r2, [r6] + cmp r2, #0 + ldreq r2, =rtems_fatal_error_occurred + movne r0, sp + moveq r0, #0xaa +#ifndef __thumb__ + mov lr, pc + mov pc, r2 +#else /* __thumb__ */ + SWITCH_FROM_ARM_TO_THUMB r1 + bl call_handler + SWITCH_FROM_THUMB_TO_ARM +#endif /* __thumb__ */ + + /* Restore context */ + ldmia r5!, {r0-r3} + mov lr, r2 + msr spsr, r3 + ldmia sp!, {r0-r12} + add sp, #16 + + /* Return from interrupt */ + subs pc, lr, #8 + +#ifdef __thumb__ +.thumb +call_handler: + bx r2 +#endif /* __thumb__ */ diff --git a/cpukit/score/cpu/arm/arm_exc_handler_high.c b/cpukit/score/cpu/arm/arm_exc_handler_high.c new file mode 100644 index 0000000000..176c1b4561 --- /dev/null +++ b/cpukit/score/cpu/arm/arm_exc_handler_high.c @@ -0,0 +1,121 @@ +/** + * @file + * + * @ingroup ScoreCPU + * + * @brief ARM exception support implementation. + */ + +/* + * COPYRIGHT (c) 2000 Canon Research Centre France SA. + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * Copyright (c) 2002 Advent Networks, Inc + * Jay Monkman <jmonkman@adventnetworks.com> + * + * Copyright (c) 2007 Ray xu <rayx.cn@gmail.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * Moved from file 'cpukit/score/cpu/arm/cpu.c'. + * + * $Id$ + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/system.h> +#include <rtems.h> +#include <rtems/bspIo.h> +#include <rtems/score/isr.h> +#include <rtems/score/wkspace.h> +#include <rtems/score/thread.h> +#include <rtems/score/cpu.h> + +static void _defaultExcHandler (CPU_Exception_frame *ctx) +{ + printk("\n\r"); + printk("----------------------------------------------------------\n\r"); +#if 1 + printk("Exception 0x%x caught at PC 0x%x by thread %d\n", + ctx->register_ip, ctx->register_lr - 4, + _Thread_Executing->Object.id); +#endif + printk("----------------------------------------------------------\n\r"); + printk("Processor execution context at time of the fault was :\n\r"); + printk("----------------------------------------------------------\n\r"); +#if 0 + printk(" r0 = %8x r1 = %8x r2 = %8x r3 = %8x\n\r", + ctx->register_r0, ctx->register_r1, + ctx->register_r2, ctx->register_r3); + printk(" r4 = %8x r5 = %8x r6 = %8x r7 = %8x\n\r", + ctx->register_r4, ctx->register_r5, + ctx->register_r6, ctx->register_r7); + printk(" r8 = %8x r9 = %8x r10 = %8x\n\r", + ctx->register_r8, ctx->register_r9, ctx->register_r10); + printk(" fp = %8x ip = %8x sp = %8x pc = %8x\n\r", + ctx->register_fp, ctx->register_ip, + ctx->register_sp, ctx->register_lr - 4); + printk("----------------------------------------------------------\n\r"); +#endif + if (_ISR_Nest_level > 0) { + /* + * In this case we shall not delete the task interrupted as + * it has nothing to do with the fault. We cannot return either + * because the eip points to the faulty instruction so... + */ + printk("Exception while executing ISR!!!. System locked\n\r"); + while(1); + } + else { + printk("*********** FAULTY THREAD WILL BE DELETED **************\n\r"); + rtems_task_delete(_Thread_Executing->Object.id); + } +} + +typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); + +cpuExcHandlerType _currentExcHandler = _defaultExcHandler; + +extern void _Exception_Handler_Undef_Swi(void); +extern void _Exception_Handler_Abort(void); +extern void _exc_data_abort(void); + + + +/* FIXME: put comments here */ +void rtems_exception_init_mngt(void) +{ + ISR_Level level; + + _CPU_ISR_Disable(level); + _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF, + _Exception_Handler_Undef_Swi, + NULL); + + _CPU_ISR_install_vector(ARM_EXCEPTION_SWI, + _Exception_Handler_Undef_Swi, + NULL); + + _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, + _Exception_Handler_Abort, + NULL); + + _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT, + _exc_data_abort, + NULL); + + _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ, + _Exception_Handler_Abort, + NULL); + + _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, + _Exception_Handler_Abort, + NULL); + + _CPU_ISR_Enable(level); +} diff --git a/cpukit/score/cpu/arm/arm_exc_handler_low.S b/cpukit/score/cpu/arm/arm_exc_handler_low.S new file mode 100644 index 0000000000..c43d430e2f --- /dev/null +++ b/cpukit/score/cpu/arm/arm_exc_handler_low.S @@ -0,0 +1,164 @@ +/** + * @file + * + * @ingroup ScoreCPU + * + * @brief ARM exception support implementation. + */ + +/* + * $Id$ + * + * Copyright (c) 2007 by Ray Xu, <Rayx.cn@gmail.com> + * Thumb support added. + * + * Copyright (c) 2002 by Advent Networks, Inc. + * Jay Monkman <jmonkman@adventnetworks.com> + * + * COPYRIGHT (c) 2000 Canon Research Centre France SA. + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * Moved from file 'cpukit/score/cpu/arm/cpu_asm.S'. + * + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/asm.h> +#include <rtems/score/cpu_asm.h> + + .text + +/* FIXME: _Exception_Handler_Undef_Swi is untested */ +DEFINE_FUNCTION_ARM(_Exception_Handler_Undef_Swi) +/* FIXME: This should use load and store multiple instructions */ + sub r13,r13,#SIZE_REGS + str r4, [r13, #REG_R4] + str r5, [r13, #REG_R5] + str r6, [r13, #REG_R6] + str r7, [r13, #REG_R7] + str r8, [r13, #REG_R8] + str r9, [r13, #REG_R9] + str r10, [r13, #REG_R10] + str r11, [r13, #REG_R11] + str sp, [r13, #REG_SP] + str lr, [r13, #REG_LR] + mrs r0, cpsr /* read the status */ + and r0, r0,#0x1f /* we keep the mode as exception number */ + str r0, [r13, #REG_PC] /* we store it in a free place */ + mov r0, r13 /* put frame address in r0 (C arg 1) */ + + ldr r1, =SWI_Handler + ldr lr, =_go_back_1 + ldr pc,[r1] /* call handler */ +_go_back_1: + ldr r4, [r13, #REG_R4] + ldr r5, [r13, #REG_R5] + ldr r6, [r13, #REG_R6] + ldr r7, [r13, #REG_R7] + ldr r8, [r13, #REG_R8] + ldr r9, [r13, #REG_R9] + ldr r10, [r13, #REG_R10] + ldr r11, [r13, #REG_R11] + ldr sp, [r13, #REG_SP] + ldr lr, [r13, #REG_LR] + add r13,r13,#SIZE_REGS + movs pc,r14 /* return */ + +/* FIXME: _Exception_Handler_Abort is untested */ +DEFINE_FUNCTION_ARM(_Exception_Handler_Abort) +/* FIXME: This should use load and store multiple instructions */ + sub r13,r13,#SIZE_REGS + str r4, [r13, #REG_R4] + str r5, [r13, #REG_R5] + str r6, [r13, #REG_R6] + str r7, [r13, #REG_R7] + str r8, [r13, #REG_R8] + str r9, [r13, #REG_R9] + str sp, [r13, #REG_R11] + str lr, [r13, #REG_SP] + str lr, [r13, #REG_LR] + mrs r0, cpsr /* read the status */ + and r0, r0,#0x1f /* we keep the mode as exception number */ + str r0, [r13, #REG_PC] /* we store it in a free place */ + mov r0, r13 /* put frame address in ro (C arg 1) */ + + ldr r1, =_currentExcHandler + ldr lr, =_go_back_2 + ldr pc,[r1] /* call handler */ +_go_back_2: + ldr r4, [r13, #REG_R4] + ldr r5, [r13, #REG_R5] + ldr r6, [r13, #REG_R6] + ldr r7, [r13, #REG_R7] + ldr r8, [r13, #REG_R8] + ldr r9, [r13, #REG_R9] + ldr r10, [r13, #REG_R10] + ldr sp, [r13, #REG_R11] + ldr lr, [r13, #REG_SP] + ldr lr, [r13, #REG_LR] + add r13,r13,#SIZE_REGS +#ifdef __thumb__ + subs r11, r14,#4 + bx r11 + nop +#else + subs pc,r14,#4 /* return */ +#endif + +#define ABORT_REGS_OFFS 32-REG_R4 +#define ABORT_SIZE_REGS SIZE_REGS+ABORT_REGS_OFFS + +DEFINE_FUNCTION_ARM(_exc_data_abort) + sub sp, sp, #ABORT_SIZE_REGS /* reserve register frame */ + stmia sp, {r0-r11} + add sp, sp, #ABORT_REGS_OFFS /* the Context_Control structure starts by CPSR, R4, ... */ + + str ip, [sp, #REG_PC] /* store R12 (ip) somewhere, oh hackery, hackery, hack */ + str lr, [sp, #REG_LR] + + mov r1, lr + ldr r0, [r1, #-8] /* r0 = bad instruction */ + mrs r1, spsr /* r1 = spsr */ + mov r2, r13 /* r2 = exception frame of Context_Control type */ +#if defined(__thumb__) + .code 32 + /*arm to thumb*/ + adr r5, to_thumb + 1 + bx r5 + .code 16 +to_thumb: +#endif + bl do_data_abort +#if defined(__thumb__) +/*back to arm*/ + .code 16 +thumb_to_arm: + .align 2 + adr r5, arm_code + bx r5 + nop + .code 32 +arm_code: +#endif + + ldr lr, [sp, #REG_LR] + ldr ip, [sp, #REG_PC] /* restore R12 (ip) */ + + sub sp, sp, #ABORT_REGS_OFFS + ldmia sp, {r0-r11} + add sp, sp, #ABORT_SIZE_REGS +#ifdef __thumb__ + subs r11, r14, #4 /* return to the instruction */ + bx r11 + nop +#else + subs pc, r14, #4 +#endif + /* _AFTER_ the aborted one */ diff --git a/cpukit/score/cpu/arm/arm_exc_interrupt.S b/cpukit/score/cpu/arm/arm_exc_interrupt.S new file mode 100644 index 0000000000..e269e13455 --- /dev/null +++ b/cpukit/score/cpu/arm/arm_exc_interrupt.S @@ -0,0 +1,177 @@ +/** + * @file + * + * @ingroup ScoreCPU + * + * @brief ARM interrupt exception prologue and epilogue. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +/* + * The upper EXCHANGE_SIZE bytes of the INT stack area are used for data + * exchange between INT and SVC mode. Below of this is the actual INT stack. + * The exchange area is only accessed if INT is disabled. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/asm.h> +#include <rtems/score/percpu.h> + +#define EXCHANGE_LR r4 +#define EXCHANGE_SPSR r5 +#define EXCHANGE_CPSR r6 +#define EXCHANGE_INT_SP r7 + +#define EXCHANGE_LIST {EXCHANGE_LR, EXCHANGE_SPSR, EXCHANGE_CPSR, EXCHANGE_INT_SP} +#define EXCHANGE_SIZE 16 + +#define CONTEXT_LIST {r0, r1, r2, r3, EXCHANGE_LR, EXCHANGE_SPSR, r12} +#define CONTEXT_SIZE 28 + +.extern _Thread_Dispatch_disable_level + +.extern bsp_interrupt_dispatch + +.arm +.globl arm_exc_interrupt +arm_exc_interrupt: + + /* Save exchange registers to exchange area */ + stmdb sp, EXCHANGE_LIST + + /* Set exchange registers */ + mov EXCHANGE_LR, lr + mrs EXCHANGE_SPSR, spsr + mrs EXCHANGE_CPSR, cpsr + sub EXCHANGE_INT_SP, sp, #EXCHANGE_SIZE + + /* Switch to SVC mode */ + orr EXCHANGE_CPSR, EXCHANGE_CPSR, #0x1 + msr cpsr, EXCHANGE_CPSR + + /* + * Save context. We save the LR separately because it has to be + * restored in SVC mode. The other registers can be restored in INT + * mode. + */ + stmdb sp!, CONTEXT_LIST + stmdb sp!, {lr} + + /* Remember INT stack pointer */ + mov r1, EXCHANGE_INT_SP + + /* Restore exchange registers from exchange area */ + ldmia r1, EXCHANGE_LIST + + /* Get interrupt nest level */ + ldr r0, =ISR_NEST_LEVEL + ldr r2, [r0] + + /* Switch stack if necessary and save original stack pointer */ + mov r3, sp + cmp r2, #0 + moveq sp, r1 + stmdb sp!, {r3} + + /* Switch to THUMB instructions if necessary */ + SWITCH_FROM_ARM_TO_THUMB r1 + + /* Increment interrupt nest and thread dispatch disable level */ + ldr r1, =_Thread_Dispatch_disable_level + ldr r3, [r1] + add r2, #1 + add r3, #1 + str r2, [r0] + str r3, [r1] + + /* Call BSP dependent interrupt dispatcher */ + bl bsp_interrupt_dispatch + + /* Decrement interrupt nest and thread dispatch disable level */ + ldr r0, =ISR_NEST_LEVEL + ldr r1, =_Thread_Dispatch_disable_level + ldr r2, [r0] + ldr r3, [r1] + sub r2, #1 + sub r3, #1 + str r2, [r0] + str r3, [r1] + + /* Restore stack pointer */ + SWITCH_FROM_THUMB_TO_ARM + ldr sp, [sp] + SWITCH_FROM_ARM_TO_THUMB r0 + + /* Check thread dispatch disable level */ + cmp r3, #0 + bne thread_dispatch_done + + /* Check context switch necessary */ + ldr r0, =DISPATCH_NEEDED + ldrb r1, [r0] + cmp r1, #0 + beq thread_dispatch_done + + /* This aligns thread_dispatch_done on a 4 byte boundary */ +#ifdef __thumb__ + nop +#endif /* __thumb__ */ + +do_thread_dispatch: + + /* Thread dispatch */ + bl _Thread_Dispatch + +thread_dispatch_done: + + /* Switch to ARM instructions if necessary */ + SWITCH_FROM_THUMB_TO_ARM + + /* Restore link register */ + ldmia sp!, {lr} + + /* + * XXX: Remember and restore stack pointer. The data on the stack is + * still in use. So the stack is now in an inconsistent state. The + * FIQ handler implementation must not use this area. + */ + mov r0, sp + add sp, #CONTEXT_SIZE + + /* Get INT mode program status register */ + mrs r1, cpsr + bic r1, r1, #0x1 + + /* Switch to INT mode */ + msr cpsr, r1 + + /* Save EXCHANGE_LR and EXCHANGE_SPSR registers to exchange area */ + stmdb sp!, {EXCHANGE_LR, EXCHANGE_SPSR} + + /* Restore context */ + ldmia r0, CONTEXT_LIST + + /* Set return address and program status */ + mov lr, EXCHANGE_LR + msr spsr, EXCHANGE_SPSR + + /* Restore EXCHANGE_LR and EXCHANGE_SPSR registers from exchange area */ + ldmia sp!, {EXCHANGE_LR, EXCHANGE_SPSR} + + /* Return from interrupt */ + subs pc, lr, #4 diff --git a/cpukit/score/cpu/arm/cpu.c b/cpukit/score/cpu/arm/cpu.c new file mode 100644 index 0000000000..00ff4aabcd --- /dev/null +++ b/cpukit/score/cpu/arm/cpu.c @@ -0,0 +1,125 @@ +/** + * @file + * + * @ingroup ScoreCPU + * + * @brief ARM architecture support implementation. + */ + +/* + * COPYRIGHT (c) 2000 Canon Research Centre France SA. + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * Copyright (c) 2002 Advent Networks, Inc + * Jay Monkman <jmonkman@adventnetworks.com> + * + * Copyright (c) 2007 Ray xu <rayx.cn@gmail.com> + * + * Copyright (c) 2009 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/system.h> +#include <rtems.h> +#include <rtems/bspIo.h> +#include <rtems/score/isr.h> +#include <rtems/score/wkspace.h> +#include <rtems/score/thread.h> +#include <rtems/score/cpu.h> + +/* + * This variable can be used to change the running mode of the execution + * contexts. + */ +uint32_t arm_cpu_mode = 0x13; + +void _CPU_Context_Initialize( + Context_Control *the_context, + uint32_t *stack_base, + uint32_t size, + uint32_t new_level, + void *entry_point, + bool is_fp +) +{ + the_context->register_sp = (uint32_t) stack_base + size ; + the_context->register_lr = (uint32_t) entry_point; + the_context->register_cpsr = new_level | arm_cpu_mode; +} + +/* Preprocessor magic for stringification of x */ +#define _CPU_ISR_LEVEL_DO_STRINGOF( x) #x +#define _CPU_ISR_LEVEL_STRINGOF( x) _CPU_ISR_LEVEL_DO_STRINGOF( x) + +void _CPU_ISR_Set_level( uint32_t level ) +{ + uint32_t arm_switch_reg; + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "mrs %[arm_switch_reg], cpsr\n" + "bic %[arm_switch_reg], #" _CPU_ISR_LEVEL_STRINGOF( CPU_MODES_INTERRUPT_MASK ) "\n" + "orr %[arm_switch_reg], %[level]\n" + "msr cpsr, %0\n" + ARM_SWITCH_BACK + : [arm_switch_reg] "=&r" (arm_switch_reg) + : [level] "r" (level) + ); +} + +uint32_t _CPU_ISR_Get_level( void ) +{ + ARM_SWITCH_REGISTERS; + uint32_t level; + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "mrs %[level], cpsr\n" + "and %[level], #" _CPU_ISR_LEVEL_STRINGOF( CPU_MODES_INTERRUPT_MASK ) "\n" + ARM_SWITCH_BACK + : [level] "=&r" (level) ARM_SWITCH_ADDITIONAL_OUTPUT + ); + + return level; +} + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + /* Redirection table starts at the end of the vector table */ + volatile uint32_t *table = (volatile uint32_t *) (MAX_EXCEPTIONS * 4); + + uint32_t current_handler = table [vector]; + + /* The current handler is now the old one */ + if (old_handler != NULL) { + *old_handler = (proc_ptr) current_handler; + } + + /* Write only if necessary to avoid writes to a maybe read-only memory */ + if (current_handler != (uint32_t) new_handler) { + table [vector] = (uint32_t) new_handler; + } +} + +void _CPU_Install_interrupt_stack( void ) +{ + /* This function is empty since the BSP must set up the interrupt stacks */ +} + +void _CPU_Initialize( void ) +{ + /* Do nothing */ +} diff --git a/cpukit/score/cpu/arm/cpu_asm.S b/cpukit/score/cpu/arm/cpu_asm.S new file mode 100644 index 0000000000..9eebabae38 --- /dev/null +++ b/cpukit/score/cpu/arm/cpu_asm.S @@ -0,0 +1,80 @@ +/** + * @file + * + * @ingroup ScoreCPU + * + * @brief ARM architecture support implementation. + */ + +/* + * $Id$ + * + * This file contains all assembly code for the ARM implementation + * of RTEMS. + * + * Copyright (c) 2007 by Ray Xu, <Rayx.cn@gmail.com> + * Thumb support added. + * + * Copyright (c) 2002 by Advent Networks, Inc. + * Jay Monkman <jmonkman@adventnetworks.com> + * + * COPYRIGHT (c) 2000 Canon Research Centre France SA. + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/asm.h> +#include <rtems/score/cpu_asm.h> + + .text + +/* + * void _CPU_Context_switch( run_context, heir_context ) + * void _CPU_Context_restore( run_context, heir_context ) + * + * This routine performs a normal non-FP context. + * + * R0 = run_context R1 = heir_context + * + * This function copies the current registers to where r0 points, then + * restores the ones from where r1 points. + * + * Using the ldm/stm opcodes save 2-3 us on 100 MHz ARM9TDMI with + * a 16 bit data bus. + * + */ + +DEFINE_FUNCTION_ARM(_CPU_Context_switch) +/* Start saving context */ + mrs r2, cpsr + stmia r0, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14} + + +/* Start restoring context */ +_restore: + ldmia r1, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14} + msr cpsr, r2 +#ifdef __thumb__ + bx lr + nop +#else + mov pc, lr +#endif +/* + * void _CPU_Context_restore( new_context ) + * + * This function copies the restores the registers from where r0 points. + * It must match _CPU_Context_switch() + * + */ +DEFINE_FUNCTION_ARM(_CPU_Context_restore) + mov r1, r0 + b _restore diff --git a/cpukit/score/cpu/arm/preinstall.am b/cpukit/score/cpu/arm/preinstall.am new file mode 100644 index 0000000000..90ac37443e --- /dev/null +++ b/cpukit/score/cpu/arm/preinstall.am @@ -0,0 +1,45 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif + +PREINSTALL_DIRS = +DISTCLEANFILES = $(PREINSTALL_DIRS) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES = $(PREINSTALL_FILES) + +$(PROJECT_INCLUDE)/rtems/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems + @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) + +$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h + +$(PROJECT_INCLUDE)/rtems/score/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score + @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + +$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h + +$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h + +$(PROJECT_INCLUDE)/rtems/score/arm.h: rtems/score/arm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/arm.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/arm.h + +$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h + diff --git a/cpukit/score/cpu/arm/rtems/asm.h b/cpukit/score/cpu/arm/rtems/asm.h new file mode 100644 index 0000000000..9d56c514a6 --- /dev/null +++ b/cpukit/score/cpu/arm/rtems/asm.h @@ -0,0 +1,178 @@ +/** + * @file + * + * @ingroup ScoreCPU + * + * @brief ARM assembler support API. + */ + +/* + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 2000 Canon Research Centre France SA. + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include <rtems/score/cpuopts.h> +#include <rtems/score/arm.h> + +/** + * @defgroup ScoreCPUARMASM ARM Assembler Support + * + * @ingroup ScoreCPU + * + * @brief ARM assembler support. + * + * @{ + */ + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +#include <rtems/concat.h> + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +#define r0 REG(r0) +#define r1 REG(r1) +#define r2 REG(r2) +#define r3 REG(r3) +#define r4 REG(r4) +#define r5 REG(r5) +#define r6 REG(r6) +#define r7 REG(r7) +#define r8 REG(r8) +#define r9 REG(r9) +#define r10 REG(r10) +#define r11 REG(r11) +#define r12 REG(r12) +#define r13 REG(r13) +#define r14 REG(r14) +#define r15 REG(r15) + +#define CPSR REG(CPSR) + +#define SPSR REG(SPSR) + +#define NUM_IRQ_VECTOR 6 // IRQ number +#define NUM_FIQ_VECTOR 7 // IRQ number + // // +#define CPSR_IRQ_DISABLE 0x80 // FIQ disabled when =1 +#define CPSR_FIQ_DISABLE 0x40 // FIQ disabled when =1 +#define CPSR_THUMB_ENABLE 0x20 // Thumb mode when =1 +#define CPSR_FIQ_MODE 0x11 +#define CPSR_IRQ_MODE 0x12 +#define CPSR_SUPERVISOR_MODE 0x13 +#define CPSR_UNDEF_MODE 0x1B + +#define CPSR_MODE_BITS 0x1F + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .globl SYM (sym) +#define EXTERN(sym) .globl SYM (sym) + +#ifdef __thumb__ + #define DEFINE_FUNCTION_ARM(name) \ + .thumb_func ; .globl name ; name: ; bx pc ; \ + .arm ; .globl name ## _arm ; name ## _arm: +#else + #define DEFINE_FUNCTION_ARM(name) \ + .globl name ; name: ; .globl name ## _arm ; name ## _arm: +#endif + +.macro SWITCH_FROM_THUMB_TO_ARM +#ifdef __thumb__ +.align 2 + bx pc +.arm +#endif /* __thumb__ */ +.endm + +.macro SWITCH_FROM_ARM_TO_THUMB REG +#ifdef __thumb__ + add \REG, pc, #1 + bx \REG +.thumb +#endif /* __thumb__ */ +.endm + +/** @} */ + +#endif /* _RTEMS_ASM_H */ diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h b/cpukit/score/cpu/arm/rtems/score/arm.h new file mode 100644 index 0000000000..d74765c5f7 --- /dev/null +++ b/cpukit/score/cpu/arm/rtems/score/arm.h @@ -0,0 +1,98 @@ +/** + * @file + * + * @ingroup ScoreCPU + * + * @brief ARM assembler support API. + */ + +/* + * $Id$ + * + * COPYRIGHT (c) 2000 Canon Research Centre France SA. + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * Copyright (c) 2002 Advent Networks, Inc. + * Jay Monkman <jmonkman@adventnetworks.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_ARM_H +#define _RTEMS_SCORE_ARM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup ScoreCPU + * + * @{ + */ + +/* + * This file contains the information required to build + * RTEMS for a particular member of the "arm" + * family when executing in protected mode. It does + * this by setting variables to indicate which implementation + * dependent features are present in a particular member + * of the family. + */ +#if defined(__ARM_ARCH_4__) +# define CPU_MODEL_NAME "ARMv4" + +#elif defined(__ARM_ARCH_4T__) +# define CPU_MODEL_NAME "ARMv4T" + +#elif defined(__ARM_ARCH_5__) +# define CPU_MODEL_NAME "ARMv5" + +#elif defined(__ARM_ARCH_5T__) +# define CPU_MODEL_NAME "ARMv5T" + +#elif defined(__ARM_ARCH_5E__) +# define CPU_MODEL_NAME "ARMv5E" + +#elif defined(__ARM_ARCH_5TE__) +# define CPU_MODEL_NAME "ARMv5TE" + +#elif defined(__ARM_ARCH_5TEJ__) +# define CPU_MODEL_NAME "ARMv5TEJ" + +#elif defined(__ARM_ARCH_6J__) +# define CPU_MODEL_NAME "ARMv6J" + +#elif defined(__ARM_ARCH_7A__) +# define CPU_MODEL_NAME "ARMv7A" + +#else +# error "Unsupported CPU Model" + +#endif + +/* All ARM CPUs are assumed to not have floating point units */ +#if defined(__SOFTFP__) +#define ARM_HAS_FPU 0 +#else +#define ARM_HAS_FPU 1 +#warning "FPU-support not yet implemented for the arm" +#endif + + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "ARM" + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_ARM_H */ diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h new file mode 100644 index 0000000000..405ccb79bb --- /dev/null +++ b/cpukit/score/cpu/arm/rtems/score/cpu.h @@ -0,0 +1,495 @@ +/** + * @file + * + * @ingroup ScoreCPU + * + * @brief ARM architecture support API. + */ + +/* + * $Id$ + * + * This include file contains information pertaining to the ARM + * processor. + * + * Copyright (c) 2009-2010 embedded brains GmbH. + * + * Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com> + * + * Copyright (c) 2006 OAR Corporation + * + * Copyright (c) 2002 Advent Networks, Inc. + * Jay Monkman <jmonkman@adventnetworks.com> + * + * COPYRIGHT (c) 2000 Canon Research Centre France SA. + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#include <rtems/score/types.h> +#include <rtems/score/arm.h> + +/** + * @defgroup ScoreCPUARM ARM Specific Support + * + * @ingroup ScoreCPU + * + * @brief ARM specific support. + * + * @{ + */ + +#ifdef __thumb__ + #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg + #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n" + #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n" + #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg) + #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT +#else + #define ARM_SWITCH_REGISTERS + #define ARM_SWITCH_TO_ARM + #define ARM_SWITCH_BACK + #define ARM_SWITCH_OUTPUT + #define ARM_SWITCH_ADDITIONAL_OUTPUT +#endif + +/** + * @name Program Status Register + * + * @{ + */ + +#define ARM_PSR_N (1 << 31) +#define ARM_PSR_Z (1 << 30) +#define ARM_PSR_C (1 << 29) +#define ARM_PSR_V (1 << 28) +#define ARM_PSR_Q (1 << 27) +#define ARM_PSR_J (1 << 24) +#define ARM_PSR_GE_SHIFT 16 +#define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT) +#define ARM_PSR_E (1 << 9) +#define ARM_PSR_A (1 << 8) +#define ARM_PSR_I (1 << 7) +#define ARM_PSR_F (1 << 6) +#define ARM_PSR_T (1 << 5) +#define ARM_PSR_M_SHIFT 0 +#define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT) +#define ARM_PSR_M_USR 0x10 +#define ARM_PSR_M_FIQ 0x11 +#define ARM_PSR_M_IRQ 0x12 +#define ARM_PSR_M_SVC 0x13 +#define ARM_PSR_M_ABT 0x17 +#define ARM_PSR_M_UND 0x1b +#define ARM_PSR_M_SYS 0x1f + +/** @} */ + +/** @} */ + +/** + * @addtogroup ScoreCPU + * + * @{ + */ + +/* If someone uses THUMB we assume she wants minimal code size */ +#ifdef __thumb__ + #define CPU_INLINE_ENABLE_DISPATCH FALSE +#else + #define CPU_INLINE_ENABLE_DISPATCH TRUE +#endif + +#if defined(__ARMEL__) + #define CPU_BIG_ENDIAN FALSE + #define CPU_LITTLE_ENDIAN TRUE +#elif defined(__ARMEB__) + #define CPU_BIG_ENDIAN TRUE + #define CPU_LITTLE_ENDIAN FALSE +#else + #error "unknown endianness" +#endif + +#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE + +#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE + +#define CPU_ALLOCATE_INTERRUPT_STACK FALSE + +#define CPU_ISR_PASSES_FRAME_POINTER 0 + +#if ( ARM_HAS_FPU == 1 ) + #define CPU_HARDWARE_FP TRUE +#else + #define CPU_HARDWARE_FP FALSE +#endif + +#define CPU_SOFTWARE_FP FALSE + +#define CPU_ALL_TASKS_ARE_FP FALSE + +#define CPU_IDLE_TASK_IS_FP FALSE + +#define CPU_USE_DEFERRED_FP_SWITCH FALSE + +#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE + +#define CPU_STACK_GROWS_UP FALSE + +/* XXX Why 32? */ +#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) + +/* + * The interrupt mask disables only normal interrupts (IRQ). + * + * In order to support fast interrupts (FIQ) such that they can do something + * useful, we have to disable the operating system support for FIQs. Having + * operating system support for them would require that FIQs are disabled + * during critical sections of the operating system and application. At this + * level IRQs and FIQs would be equal. It is true that FIQs could interrupt + * the non critical sections of IRQs, so here they would have a small + * advantage. Without operating system support, the FIQs can execute at any + * time (of course not during the service of another FIQ). If someone needs + * operating system support for a FIQ, she can trigger a software interrupt and + * service the request in a two-step process. + */ +#define CPU_MODES_INTERRUPT_MASK 0x80 + +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 8 + +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) + +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +#define CPU_STACK_MINIMUM_SIZE (1024 * 4) + +/* AAPCS, section 4.1, Fundamental Data Types */ +#define CPU_ALIGNMENT 8 + +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/* AAPCS, section 5.2.1.2, Stack constraints at a public interface */ +#define CPU_STACK_ALIGNMENT 8 + +/* + * Bitfield handler macros. + * + * If we had a particularly fast function for finding the first + * bit set in a word, it would go here. Since we don't (*), we'll + * just use the universal macros. + * + * (*) On ARM V5 and later, there's a CLZ function which could be + * used to implement much quicker than the default macro. + */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +#define CPU_USE_GENERIC_BITFIELD_DATA TRUE + +/** @} */ + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup ScoreCPU + * + * @{ + */ + +typedef struct { + uint32_t register_cpsr; + uint32_t register_r4; + uint32_t register_r5; + uint32_t register_r6; + uint32_t register_r7; + uint32_t register_r8; + uint32_t register_r9; + uint32_t register_r10; + uint32_t register_fp; + uint32_t register_sp; + uint32_t register_lr; + uint32_t register_pc; +} Context_Control; + +typedef struct { + /* Not supported */ +} Context_Control_fp; + +SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; + +extern uint32_t arm_cpu_mode; + +static inline uint32_t arm_interrupt_disable( void ) +{ + uint32_t arm_switch_reg; + uint32_t level; + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "mrs %[level], cpsr\n" + "orr %[arm_switch_reg], %[level], #0x80\n" + "msr cpsr, %[arm_switch_reg]\n" + ARM_SWITCH_BACK + : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level) + ); + + return level; +} + +static inline void arm_interrupt_enable( uint32_t level ) +{ + ARM_SWITCH_REGISTERS; + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "msr cpsr, %[level]\n" + ARM_SWITCH_BACK + : ARM_SWITCH_OUTPUT + : [level] "r" (level) + ); +} + +static inline void arm_interrupt_flash( uint32_t level ) +{ + uint32_t arm_switch_reg; + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "mrs %[arm_switch_reg], cpsr\n" + "msr cpsr, %[level]\n" + "msr cpsr, %[arm_switch_reg]\n" + ARM_SWITCH_BACK + : [arm_switch_reg] "=&r" (arm_switch_reg) + : [level] "r" (level) + ); +} + +#define _CPU_ISR_Disable( _isr_cookie ) \ + do { \ + _isr_cookie = arm_interrupt_disable(); \ + } while (0) + +#define _CPU_ISR_Enable( _isr_cookie ) \ + arm_interrupt_enable( _isr_cookie ) + +#define _CPU_ISR_Flash( _isr_cookie ) \ + arm_interrupt_flash( _isr_cookie ) + +void _CPU_ISR_Set_level( uint32_t level ); + +uint32_t _CPU_ISR_Get_level( void ); + +void _CPU_Context_Initialize( + Context_Control *the_context, + uint32_t *stack_base, + uint32_t size, + uint32_t new_level, + void *entry_point, + bool is_fp +); + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->register_sp + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +#define _CPU_Context_Fp_start( _base, _offset ) \ + ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) + +#define _CPU_Context_Initialize_fp( _destination ) \ + do { \ + *(*(_destination)) = _CPU_Null_fp_context; \ + } while (0) + +#define _CPU_Fatal_halt( _err ) \ + do { \ + uint32_t _level; \ + uint32_t _error = _err; \ + _CPU_ISR_Disable( _level ); \ + __asm__ volatile ("mov r0, %0\n" \ + : "=r" (_error) \ + : "0" (_error) \ + : "r0" ); \ + while (1); \ + } while (0); + +void _CPU_Initialize( void ); + +#define _CPU_Initialize_vectors() + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +void _CPU_Install_interrupt_stack( void ); + +void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); + +void _CPU_Context_restore( Context_Control *new_context ) + RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; + +void _CPU_Context_save_fp( Context_Control_fp **fp_context_ptr ); + +void _CPU_Context_restore_fp( Context_Control_fp **fp_context_ptr ); + +static inline uint32_t CPU_swap_u32( uint32_t value ) +{ +#if defined(__thumb__) + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return swapped; +#else + uint32_t tmp = value; /* make compiler warnings go away */ + __asm__ volatile ("EOR %1, %0, %0, ROR #16\n" + "BIC %1, %1, #0xff0000\n" + "MOV %0, %0, ROR #8\n" + "EOR %0, %0, %1, LSR #8\n" + : "=r" (value), "=r" (tmp) + : "0" (value), "1" (tmp)); + return value; +#endif +} + +static inline uint16_t CPU_swap_u16( uint16_t value ) +{ + return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU)); +} + +/** @} */ + +/** + * @addtogroup ScoreCPUARM + * + * @{ + */ + +typedef struct { + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t r12; + uint32_t sp; + uint32_t lr; + uint32_t pc; + uint32_t cpsr; +} arm_cpu_context; + +typedef void arm_exc_abort_handler( arm_cpu_context *context ); + +typedef enum { + ARM_EXCEPTION_RESET = 0, + ARM_EXCEPTION_UNDEF = 1, + ARM_EXCEPTION_SWI = 2, + ARM_EXCEPTION_PREF_ABORT = 3, + ARM_EXCEPTION_DATA_ABORT = 4, + ARM_EXCEPTION_RESERVED = 5, + ARM_EXCEPTION_IRQ = 6, + ARM_EXCEPTION_FIQ = 7, + MAX_EXCEPTIONS = 8 +} Arm_symbolic_exception_name; + +static inline uint32_t arm_status_irq_enable( void ) +{ + uint32_t arm_switch_reg; + uint32_t psr; + + RTEMS_COMPILER_MEMORY_BARRIER(); + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "mrs %[psr], cpsr\n" + "bic %[arm_switch_reg], %[psr], #0x80\n" + "msr cpsr, %[arm_switch_reg]\n" + ARM_SWITCH_BACK + : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr) + ); + + return psr; +} + +static inline void arm_status_restore( uint32_t psr ) +{ + ARM_SWITCH_REGISTERS; + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "msr cpsr, %[psr]\n" + ARM_SWITCH_BACK + : ARM_SWITCH_OUTPUT + : [psr] "r" (psr) + ); + + RTEMS_COMPILER_MEMORY_BARRIER(); +} + +void arm_exc_data_abort_set_handler( arm_exc_abort_handler handler ); + +void arm_exc_data_abort( void ); + +void arm_exc_prefetch_abort_set_handler( arm_exc_abort_handler handler ); + +void arm_exc_prefetch_abort( void ); + +void bsp_interrupt_dispatch( void ); + +void arm_exc_interrupt( void ); + +void arm_exc_undefined( void ); + +/** @} */ + +/* XXX This is out of date */ +typedef struct { + uint32_t register_r0; + uint32_t register_r1; + uint32_t register_r2; + uint32_t register_r3; + uint32_t register_ip; + uint32_t register_lr; +} CPU_Exception_frame; + +typedef CPU_Exception_frame CPU_Interrupt_frame; + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPU_H */ diff --git a/cpukit/score/cpu/arm/rtems/score/cpu_asm.h b/cpukit/score/cpu/arm/rtems/score/cpu_asm.h new file mode 100644 index 0000000000..ac93112c30 --- /dev/null +++ b/cpukit/score/cpu/arm/rtems/score/cpu_asm.h @@ -0,0 +1,41 @@ +/** + * @file + * + * @ingroup ScoreCPU + * + * @brief ARM assembler support API. + */ + +/* + * $Id$ + * + * COPYRIGHT (c) 2002 by Advent Networks, Inc. + * Jay Monkman <jmonkman@adventnetworks.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * This file is the include file for cpu_asm.S + */ + +#ifndef _RTEMS_SCORE_CPU_ASM_H +#define _RTEMS_SCORE_CPU_ASM_H + + +/* Registers saved in context switch: */ +.set REG_CPSR, 0 +.set REG_R4, 4 +.set REG_R5, 8 +.set REG_R6, 12 +.set REG_R7, 16 +.set REG_R8, 20 +.set REG_R9, 24 +.set REG_R10, 28 +.set REG_R11, 32 +.set REG_SP, 36 +.set REG_LR, 40 +.set REG_PC, 44 +.set SIZE_REGS, REG_PC + 4 + +#endif diff --git a/cpukit/score/cpu/arm/rtems/score/types.h b/cpukit/score/cpu/arm/rtems/score/types.h new file mode 100644 index 0000000000..5eb1bf7765 --- /dev/null +++ b/cpukit/score/cpu/arm/rtems/score/types.h @@ -0,0 +1,55 @@ +/** + * @file + * + * @ingroup ScoreCPU + * + * @brief ARM architecture types API. + */ + +/* + * $Id$ + * + * This include file contains type definitions pertaining to the + * arm processor family. + * + * COPYRIGHT (c) 2000 Canon Research Centre France SA. + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + */ + +#ifndef _RTEMS_SCORE_TYPES_H +#define _RTEMS_SCORE_TYPES_H + +#include <rtems/score/basedefs.h> + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup ScoreCPU + * + * @{ + */ + +/* + * This section defines the basic types for this processor. + */ + +typedef uint16_t Priority_bit_map_Control; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif |