diff options
Diffstat (limited to '')
43 files changed, 473 insertions, 167 deletions
diff --git a/cpukit/score/cpu/arm/__aeabi_read_tp.c b/cpukit/score/cpu/arm/__aeabi_read_tp.c index 671065825d..0f4eba8d9a 100644 --- a/cpukit/score/cpu/arm/__aeabi_read_tp.c +++ b/cpukit/score/cpu/arm/__aeabi_read_tp.c @@ -1,7 +1,15 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of __aeabi_read_tp(). + */ + /* - * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * Copyright (c) 2014 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -42,15 +50,15 @@ void __attribute__((naked)) __aeabi_read_tp(void) "ldr r0, =_Per_CPU_Information\n" "ldr r0, [r0, %[executingoff]]\n" #if defined(__thumb__) && !defined(__thumb2__) - "add r0, %[tlsareaoff]\n" + "add r0, %[threadidoff]\n" "ldr r0, [r0]\n" #else - "ldr r0, [r0, %[tlsareaoff]]\n" + "ldr r0, [r0, %[threadidoff]]\n" #endif "bx lr\n" : : [executingoff] "I" (offsetof(Per_CPU_Control, executing)), - [tlsareaoff] "I" (offsetof(Thread_Control, Start.tls_area)) + [threadidoff] "I" (offsetof(Thread_Control, Registers.thread_id)) ); } diff --git a/cpukit/score/cpu/arm/__tls_get_addr.c b/cpukit/score/cpu/arm/__tls_get_addr.c index 5c8e60ae06..407bf3d639 100644 --- a/cpukit/score/cpu/arm/__tls_get_addr.c +++ b/cpukit/score/cpu/arm/__tls_get_addr.c @@ -1,7 +1,15 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of __tls_get_addr(). + */ + /* - * Copyright (c) 2014-2015 embedded brains GmbH. All rights reserved. + * Copyright (C) 2014, 2015 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -39,10 +47,10 @@ void *__tls_get_addr(const TLS_Index *ti); void *__tls_get_addr(const TLS_Index *ti) { const Thread_Control *executing = _Thread_Get_executing(); - void *tls_block = (char *) executing->Start.tls_area - + _TLS_Get_thread_control_block_area_size( (uintptr_t) _TLS_Alignment ); + void *tls_data = (char *) executing->Registers.thread_id + + _TLS_Get_thread_control_block_area_size( &_TLS_Configuration ); assert(ti->module == 1); - return (char *) tls_block + ti->offset; + return (char *) tls_data + ti->offset; } diff --git a/cpukit/score/cpu/arm/aarch32-psma-init-default.c b/cpukit/score/cpu/arm/aarch32-psma-init-default.c index da710d77fc..615e7a528a 100644 --- a/cpukit/score/cpu/arm/aarch32-psma-init-default.c +++ b/cpukit/score/cpu/arm/aarch32-psma-init-default.c @@ -10,7 +10,7 @@ */ /* - * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2020 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/arm/aarch32-psma-init.c b/cpukit/score/cpu/arm/aarch32-psma-init.c index 543e1b7d9b..93a3673a98 100644 --- a/cpukit/score/cpu/arm/aarch32-psma-init.c +++ b/cpukit/score/cpu/arm/aarch32-psma-init.c @@ -10,7 +10,7 @@ */ /* - * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2020 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/arm/arm-context-validate.S b/cpukit/score/cpu/arm/arm-context-validate.S index 424fa60daf..51157071dd 100644 --- a/cpukit/score/cpu/arm/arm-context-validate.S +++ b/cpukit/score/cpu/arm/arm-context-validate.S @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2017 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S index ac40755d4d..5cbbb27754 100644 --- a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S +++ b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2017 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/arm/arm-exception-default.c b/cpukit/score/cpu/arm/arm-exception-default.c index d2b2fc2767..02df769287 100644 --- a/cpukit/score/cpu/arm/arm-exception-default.c +++ b/cpukit/score/cpu/arm/arm-exception-default.c @@ -1,7 +1,16 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _ARM_Exception_default(). + */ + /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/arm/arm-exception-frame-print.c b/cpukit/score/cpu/arm/arm-exception-frame-print.c index 4bb1efedec..b089648184 100644 --- a/cpukit/score/cpu/arm/arm-exception-frame-print.c +++ b/cpukit/score/cpu/arm/arm-exception-frame-print.c @@ -1,7 +1,16 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _CPU_Exception_frame_print(). + */ + /* - * Copyright (c) 2012-2013 embedded brains GmbH. All rights reserved. + * Copyright (C) 2012, 2013 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -32,11 +41,14 @@ #include <inttypes.h> #include <rtems/score/cpu.h> +#if defined(ARM_MULTILIB_ARCH_V7M) +#include <rtems/score/armv7m.h> +#endif #include <rtems/bspIo.h> static void _ARM_VFP_context_print( const ARM_VFP_context *vfp_context ) { -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP if ( vfp_context != NULL ) { const uint64_t *dx = &vfp_context->register_d0; int i; @@ -47,7 +59,14 @@ static void _ARM_VFP_context_print( const ARM_VFP_context *vfp_context ) vfp_context->register_fpscr ); - for ( i = 0; i < 32; ++i ) { +#if defined(ARM_MULTILIB_VFP_D32) + int regcount = 32; +#elif defined(ARM_MULTILIB_VFP_D16) + int regcount = 16; +#else + int regcount = 0; +#endif + for ( i = 0; i < regcount; ++i ) { uint32_t low = (uint32_t) dx[i]; uint32_t high = (uint32_t) (dx[i] >> 32); @@ -57,6 +76,136 @@ static void _ARM_VFP_context_print( const ARM_VFP_context *vfp_context ) #endif } +static void _ARM_Cortex_M_fault_info_print( void ) +{ +#if defined(ARM_MULTILIB_ARCH_V7M) + /* + * prints content of additional debugging registers + * available on Cortex-Mx where x > 0 cores. + */ + uint32_t cfsr = _ARMV7M_SCB->cfsr; + uint8_t mmfsr = ARMV7M_SCB_CFSR_MMFSR_GET( cfsr ); + uint8_t bfsr = ( ARMV7M_SCB_CFSR_BFSR_GET( cfsr ) >> 8 ); + uint16_t ufsr = ( ARMV7M_SCB_CFSR_UFSR_GET( cfsr ) >> 16 ); + uint32_t hfsr = _ARMV7M_SCB->hfsr; + if ( mmfsr > 0 ) { + printk( "MMFSR= 0x%08" PRIx32 " (memory fault)\n", mmfsr ); + if ( ( mmfsr & 0x1 ) != 0 ) { + printk( " IACCVIOL : 1 (instruction access violation)\n" ); + } + if ( ( mmfsr & 0x2 ) != 0 ) { + printk( " DACCVIOL : 1 (data access violation)\n" ); + } + if ( (mmfsr & 0x8 ) != 0 ) { + printk( + " MUNSTKERR : 1 (fault on unstacking on exception return)\n" + ); + } + if ( ( mmfsr & 0x10 ) != 0 ) { + printk( " MSTKERR : 1 (fault on stacking on exception entry)\n" ); + } + if ( (mmfsr & 0x20 ) != 0 ) { + printk( " MLSPERR : 1 (fault during lazy FP stack preservation)\n" ); + } + if ( (mmfsr & 0x80 ) != 0 ) { + printk( + " MMFARVALID : 1 -> 0x%08" PRIx32 " (error address)\n", + _ARMV7M_SCB->mmfar + ); + } + else { + printk( " MMFARVALID : 0 (undetermined error address)\n" ); + } + } + if ( bfsr > 0 ) { + printk( "BFSR = 0x%08" PRIx32 " (bus fault)\n", bfsr ); + if ( ( bfsr & 0x1 ) != 0 ) { + printk( " IBUSERR : 1 (instruction fetch error)\n" ); + } + if ( (bfsr & 0x2 ) != 0 ) { + printk( + " PRECISERR : 1 (data bus error with known exact location)\n" + ); + } + if ( ( bfsr & 0x4) != 0 ) { + printk( + " IMPRECISERR: 1 (data bus error without known exact location)\n" + ); + } + if ( (bfsr & 0x8 ) != 0 ) { + printk( + " UNSTKERR : 1 (fault on unstacking on exception return)\n" + ); + } + if ( ( bfsr & 0x10 ) != 0 ) { + printk( " STKERR : 1 (fault on stacking on exception entry)\n" ); + } + if ( ( bfsr & 0x20 ) != 0 ) { + printk( " LSPERR : 1 (fault during lazy FP stack preservation)\n" ); + } + if ( (bfsr & 0x80 ) != 0 ) { + printk( + " BFARVALID : 1 -> 0x%08" PRIx32 " (error address)\n", + _ARMV7M_SCB->bfar + ); + } + else { + printk( " BFARVALID : 0 (undetermined error address)\n" ); + } + } + if ( ufsr > 0 ) { + printk( "UFSR = 0x%08" PRIx32 " (usage fault)\n", ufsr); + if ( (ufsr & 0x1 ) != 0 ) { + printk( " UNDEFINSTR : 1 (undefined instruction issued)\n"); + } + if ( (ufsr & 0x2 ) != 0 ) { + printk( + " INVSTATE : 1" + " (invalid instruction state" + " (Thumb not set in EPSR or invalid IT state in EPSR))\n" + ); + } + if ( (ufsr & 0x4 ) != 0 ) { + printk( " INVPC : 1 (integrity check failure on EXC_RETURN)\n" ); + } + if ( (ufsr & 0x8 ) != 0 ) { + printk( + " NOCP : 1" + " (coprocessor instruction issued" + " but coprocessor disabled or non existent)\n" + ); + } + if ( ( ufsr & 0x100) != 0 ) { + printk( " UNALIGNED : 1 (unaligned access operation occurred)\n" ); + } + if ( ( ufsr & 0x200) != 0 ) { + printk( " DIVBYZERO : 1 (division by zero)" ); + } + } + if ( (hfsr & ( + ARMV7M_SCB_HFSR_VECTTBL_MASK + | ARMV7M_SCB_HFSR_DEBUGEVT_MASK + | ARMV7M_SCB_HFSR_FORCED_MASK + ) ) != 0 ) { + printk( "HFSR = 0x%08" PRIx32 " (hard fault)\n", hfsr ); + if ( (hfsr & ARMV7M_SCB_HFSR_VECTTBL_MASK ) != 0 ) { + printk( + " VECTTBL : 1 (error in address located in vector table)\n" + ); + } + if ( (hfsr & ARMV7M_SCB_HFSR_FORCED_MASK ) != 0 ) { + printk( + " FORCED : 1 (configurable fault escalated to hard fault)\n" + ); + } + if ( (hfsr & ARMV7M_SCB_HFSR_DEBUGEVT_MASK ) != 0 ) { + printk( + " DEBUGEVT : 1 (debug event occurred with debug system disabled)\n" + ); + } + } +#endif +} void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ) { printk( @@ -100,4 +249,5 @@ void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ) ); _ARM_VFP_context_print( frame->vfp_context ); + _ARM_Cortex_M_fault_info_print(); } diff --git a/cpukit/score/cpu/arm/arm_exc_abort.S b/cpukit/score/cpu/arm/arm_exc_abort.S index b2fe0b726a..2721e3fed0 100644 --- a/cpukit/score/cpu/arm/arm_exc_abort.S +++ b/cpukit/score/cpu/arm/arm_exc_abort.S @@ -9,7 +9,7 @@ */ /* - * Copyright (c) 2009 embedded brains GmbH. All rights reserved. + * Copyright (c) 2009 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/arm/arm_exc_interrupt.S b/cpukit/score/cpu/arm/arm_exc_interrupt.S index 696aeb786f..5a7109da26 100644 --- a/cpukit/score/cpu/arm/arm_exc_interrupt.S +++ b/cpukit/score/cpu/arm/arm_exc_interrupt.S @@ -9,7 +9,7 @@ */ /* - * Copyright (c) 2009, 2022 embedded brains GmbH. All rights reserved. + * Copyright (C) 2009, 2022 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/arm/armv4-exception-default.S b/cpukit/score/cpu/arm/armv4-exception-default.S index 595951073d..a23aef76a4 100644 --- a/cpukit/score/cpu/arm/armv4-exception-default.S +++ b/cpukit/score/cpu/arm/armv4-exception-default.S @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/arm/armv4-isr-install-vector.c b/cpukit/score/cpu/arm/armv4-isr-install-vector.c new file mode 100644 index 0000000000..739b02f8bf --- /dev/null +++ b/cpukit/score/cpu/arm/armv4-isr-install-vector.c @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the ARM-specific _CPU_ISR_install_vector(). + */ + +/* + * COPYRIGHT (c) 2000 Canon Research Centre France SA. + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * Copyright (c) 2002 Advent Networks, Inc + * Jay Monkman <jmonkman@adventnetworks.com> + * + * Copyright (C) 2009, 2017 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/score/cpu.h> + +#ifdef ARM_MULTILIB_ARCH_V4 + +void _CPU_ISR_install_vector( + uint32_t vector, + CPU_ISR_handler new_handler, + CPU_ISR_handler *old_handler +) +{ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Warray-bounds" + /* Redirection table starts at the end of the vector table */ + CPU_ISR_handler volatile *table = (CPU_ISR_handler *) (MAX_EXCEPTIONS * 4); + + CPU_ISR_handler current_handler = table [vector]; + + /* The current handler is now the old one */ + if (old_handler != NULL) { + *old_handler = current_handler; + } + + /* Write only if necessary to avoid writes to a maybe read-only memory */ + if (current_handler != new_handler) { + table [vector] = new_handler; + } +#pragma GCC diagnostic pop +} + +#endif /* ARM_MULTILIB_ARCH_V4 */ diff --git a/cpukit/score/cpu/arm/armv4-sync-synchronize.c b/cpukit/score/cpu/arm/armv4-sync-synchronize.c index 4445022fd6..2f454306d8 100644 --- a/cpukit/score/cpu/arm/armv4-sync-synchronize.c +++ b/cpukit/score/cpu/arm/armv4-sync-synchronize.c @@ -1,7 +1,15 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of __sync_synchronize(). + */ + /* - * Copyright (c) 2015 embedded brains GmbH. All rights reserved. + * Copyright (c) 2015 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/arm/armv7-thread-idle.c b/cpukit/score/cpu/arm/armv7-thread-idle.c index 399e41796e..720cb2be83 100644 --- a/cpukit/score/cpu/arm/armv7-thread-idle.c +++ b/cpukit/score/cpu/arm/armv7-thread-idle.c @@ -1,13 +1,16 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /** - * @file + * @file * - * @brief CPU Thread Idle Body + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _CPU_Thread_Idle_body(). */ /* - * Copyright (c) 2012 embedded brains GmbH. All rights reserved. + * Copyright (c) 2012 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/arm/armv7m-context-initialize.c b/cpukit/score/cpu/arm/armv7m-context-initialize.c index 6bdedecb77..d67bcf93b5 100644 --- a/cpukit/score/cpu/arm/armv7m-context-initialize.c +++ b/cpukit/score/cpu/arm/armv7m-context-initialize.c @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /** - * @file + * @file * - * @brief CPU Initialize Context + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _CPU_Context_Initialize(). */ /* @@ -61,7 +64,7 @@ void _CPU_Context_Initialize( context->register_sp = stack_area_end; if ( tls_area != NULL ) { - _TLS_TCB_at_area_begin_initialize( tls_area ); + context->thread_id = (uint32_t) _TLS_Initialize_area( tls_area ); } } diff --git a/cpukit/score/cpu/arm/armv7m-context-restore.c b/cpukit/score/cpu/arm/armv7m-context-restore.c index bf402953a3..b888abe29f 100644 --- a/cpukit/score/cpu/arm/armv7m-context-restore.c +++ b/cpukit/score/cpu/arm/armv7m-context-restore.c @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /** - * @file + * @file * - * @brief CPU Restore Context + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _CPU_Context_restore(). */ /* diff --git a/cpukit/score/cpu/arm/armv7m-context-switch.c b/cpukit/score/cpu/arm/armv7m-context-switch.c index 091611aebf..74d6b953ef 100644 --- a/cpukit/score/cpu/arm/armv7m-context-switch.c +++ b/cpukit/score/cpu/arm/armv7m-context-switch.c @@ -3,7 +3,10 @@ /** * @file * - * @brief ARM7M CPU Context Switch + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _CPU_Context_switch(). */ /* diff --git a/cpukit/score/cpu/arm/armv7m-exception-default.c b/cpukit/score/cpu/arm/armv7m-exception-default.c index c9d1841afb..35dde50dc3 100644 --- a/cpukit/score/cpu/arm/armv7m-exception-default.c +++ b/cpukit/score/cpu/arm/armv7m-exception-default.c @@ -1,7 +1,16 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _ARMV7M_Exception_default(). + */ + /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/arm/armv7m-exception-handler-get.c b/cpukit/score/cpu/arm/armv7m-exception-handler-get.c index 63fcfffcfa..41effd1e18 100644 --- a/cpukit/score/cpu/arm/armv7m-exception-handler-get.c +++ b/cpukit/score/cpu/arm/armv7m-exception-handler-get.c @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /** - * @file + * @file * - * @brief ARMV7M Get Exception Handler + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _ARMV7M_Get_exception_handler(). */ /* diff --git a/cpukit/score/cpu/arm/armv7m-exception-handler-set.c b/cpukit/score/cpu/arm/armv7m-exception-handler-set.c index a138cbeec1..94c9dc5360 100644 --- a/cpukit/score/cpu/arm/armv7m-exception-handler-set.c +++ b/cpukit/score/cpu/arm/armv7m-exception-handler-set.c @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /** - * @file + * @file * - * @brief ARMV7M Set Exception Handler + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _ARMV7M_Set_exception_handler(). */ /* diff --git a/cpukit/score/cpu/arm/armv7m-exception-priority-get.c b/cpukit/score/cpu/arm/armv7m-exception-priority-get.c index c22e874404..bb0892a32f 100644 --- a/cpukit/score/cpu/arm/armv7m-exception-priority-get.c +++ b/cpukit/score/cpu/arm/armv7m-exception-priority-get.c @@ -1,10 +1,14 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /** - * @file + * @file * - * @brief ARMV7M Get Exception Priority + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _ARMV7M_Get_exception_priority(). */ + /* * Copyright (c) 2011 Sebastian Huber. All rights reserved. * diff --git a/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c b/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c index f77aa73522..b94366e07c 100644 --- a/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c +++ b/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c @@ -3,7 +3,10 @@ /** * @file * - * @brief ARMV7M Set Exception Priority and Handler + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _ARMV7M_Set_exception_priority_and_handler(). */ /* diff --git a/cpukit/score/cpu/arm/armv7m-exception-priority-set.c b/cpukit/score/cpu/arm/armv7m-exception-priority-set.c index da0a635497..05136a47db 100644 --- a/cpukit/score/cpu/arm/armv7m-exception-priority-set.c +++ b/cpukit/score/cpu/arm/armv7m-exception-priority-set.c @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /** - * @file + * @file * - * @brief ARMV7M Set Exception Priority + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _ARMV7M_Set_exception_priority(). */ /* diff --git a/cpukit/score/cpu/arm/armv7m-initialize.c b/cpukit/score/cpu/arm/armv7m-initialize.c index 6ec863fa30..0f47b49af7 100644 --- a/cpukit/score/cpu/arm/armv7m-initialize.c +++ b/cpukit/score/cpu/arm/armv7m-initialize.c @@ -3,11 +3,13 @@ /** * @file * - * @brief ARM7M CPU Initialize + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of _CPU_Initialize(). */ /* - * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2020 embedded brains GmbH & Co. KG * Copyright (C) 2011 Sebastian Huber * * Redistribution and use in source and binary forms, with or without diff --git a/cpukit/score/cpu/arm/armv7m-isr-dispatch.c b/cpukit/score/cpu/arm/armv7m-isr-dispatch.c index 5ab9d1fae2..ea168969ba 100644 --- a/cpukit/score/cpu/arm/armv7m-isr-dispatch.c +++ b/cpukit/score/cpu/arm/armv7m-isr-dispatch.c @@ -3,7 +3,10 @@ /** * @file * - * @brief ARMV7M ISR Dispatch + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _ARMV7M_Thread_dispatch(). */ /* diff --git a/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c b/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c index e2f5b5b62f..1490f6e219 100644 --- a/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c +++ b/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /** - * @file + * @file * - * @brief ARMV7M Interrupt Service Enter and Leave + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _ARMV7M_Interrupt_service_enter() and _ARMV7M_Interrupt_service_leave(). */ /* diff --git a/cpukit/score/cpu/arm/armv7m-isr-level-get.c b/cpukit/score/cpu/arm/armv7m-isr-level-get.c index d597e3bf3d..cc2b674e13 100644 --- a/cpukit/score/cpu/arm/armv7m-isr-level-get.c +++ b/cpukit/score/cpu/arm/armv7m-isr-level-get.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /** - * @file + * @file * - * @brief CPU Get ISR Level + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of _CPU_ISR_Get_level(). */ /* diff --git a/cpukit/score/cpu/arm/armv7m-isr-level-set.c b/cpukit/score/cpu/arm/armv7m-isr-level-set.c index 01835075fb..72c9684025 100644 --- a/cpukit/score/cpu/arm/armv7m-isr-level-set.c +++ b/cpukit/score/cpu/arm/armv7m-isr-level-set.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /** - * @file + * @file * - * @brief CPU Set ISR Level + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of _CPU_ISR_Set_level(). */ /* diff --git a/cpukit/score/cpu/arm/armv7m-isr-vector-install.c b/cpukit/score/cpu/arm/armv7m-isr-vector-install.c index 1616577895..c1e9eb70cb 100644 --- a/cpukit/score/cpu/arm/armv7m-isr-vector-install.c +++ b/cpukit/score/cpu/arm/armv7m-isr-vector-install.c @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /** - * @file + * @file * - * @brief CPU ISR Vector Install + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _CPU_ISR_install_vector(). */ /* diff --git a/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c b/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c index ffd21772a8..a9b59dec84 100644 --- a/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c +++ b/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c @@ -3,7 +3,10 @@ /** * @file * - * @brief ARMV7M Start Multitasking + * @ingroup RTEMSScoreCPUARM + * + * @brief This source file contains the implementation of + * _ARMV7M_Start_multitasking(). */ /* diff --git a/cpukit/score/cpu/arm/cpu.c b/cpukit/score/cpu/arm/cpu.c index b2cc6039b0..c27f4de9f9 100644 --- a/cpukit/score/cpu/arm/cpu.c +++ b/cpukit/score/cpu/arm/cpu.c @@ -5,7 +5,10 @@ * * @ingroup RTEMSScoreCPUARM * - * @brief ARM architecture support implementation. + * @brief This source file contains static assertions to ensure the consistency + * of interfaces used in C and assembler and it contains the ARM-specific + * implementation of _CPU_Initialize(), _CPU_ISR_Get_level(), + * _CPU_ISR_Set_level(), _CPU_Context_Initialize(), and _CPU_Fatal_halt(). */ /* @@ -17,7 +20,7 @@ * * Copyright (c) 2007 Ray xu <rayx.cn@gmail.com> * - * Copyright (c) 2009, 2017 embedded brains GmbH + * Copyright (C) 2009, 2017 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -56,13 +59,11 @@ ); #endif -#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER - RTEMS_STATIC_ASSERT( - offsetof( Context_Control, thread_id ) - == ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET, - ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET - ); -#endif +RTEMS_STATIC_ASSERT( + offsetof( Context_Control, thread_id ) + == ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET, + ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET +); #ifdef ARM_MULTILIB_ARCH_V4 RTEMS_STATIC_ASSERT( @@ -118,13 +119,10 @@ void _CPU_Context_Initialize( the_context->register_sp = (uint32_t) stack_area_begin + stack_area_size; the_context->register_lr = (uint32_t) entry_point; the_context->isr_dispatch_disable = 0; - -#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER the_context->thread_id = (uint32_t) tls_area; -#endif if ( tls_area != NULL ) { - _TLS_TCB_at_area_begin_initialize( tls_area ); + the_context->thread_id = (uint32_t) _TLS_Initialize_area( tls_area ); } } @@ -161,31 +159,6 @@ uint32_t _CPU_ISR_Get_level( void ) return ( level & ARM_PSR_I ) != 0; } -void _CPU_ISR_install_vector( - uint32_t vector, - CPU_ISR_handler new_handler, - CPU_ISR_handler *old_handler -) -{ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Warray-bounds" - /* Redirection table starts at the end of the vector table */ - CPU_ISR_handler volatile *table = (CPU_ISR_handler *) (MAX_EXCEPTIONS * 4); - - CPU_ISR_handler current_handler = table [vector]; - - /* The current handler is now the old one */ - if (old_handler != NULL) { - *old_handler = current_handler; - } - - /* Write only if necessary to avoid writes to a maybe read-only memory */ - if (current_handler != new_handler) { - table [vector] = new_handler; - } -#pragma GCC diagnostic pop -} - void _CPU_Initialize( void ) { /* Do nothing */ diff --git a/cpukit/score/cpu/arm/cpu_asm.S b/cpukit/score/cpu/arm/cpu_asm.S index d52a43f70d..87bbfc4f01 100644 --- a/cpukit/score/cpu/arm/cpu_asm.S +++ b/cpukit/score/cpu/arm/cpu_asm.S @@ -21,7 +21,7 @@ * COPYRIGHT (c) 2000 Canon Research Centre France SA. * Emmanuel Raguet, mailto:raguet@crf.canon.fr * - * Copyright (c) 2013, 2017 embedded brains GmbH + * Copyright (C) 2013, 2017 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h index 1e707191cf..c239eaccc8 100644 --- a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h +++ b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h @@ -10,7 +10,7 @@ /* * Copyright (c) 2013 Hesham AL-Matary - * Copyright (c) 2009-2017 embedded brains GmbH. All rights reserved. + * Copyright (C) 2009, 2017 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -1309,15 +1309,17 @@ arm_cp15_data_cache_test_and_clean(void) ); } -/* In DDI0301H_arm1176jzfs_r0p7_trm - * 'MCR p15, 0, <Rd>, c7, c14, 0' means - * Clean and Invalidate Entire Data Cache - */ ARM_CP15_TEXT_SECTION static inline void arm_cp15_data_cache_clean_and_invalidate(void) { ARM_SWITCH_REGISTERS; +#if __ARM_ARCH >= 6 + /* + * In DDI0301H_arm1176jzfs_r0p7_trm + * 'MCR p15, 0, <Rd>, c7, c14, 0' means + * Clean and Invalidate Entire Data Cache + */ uint32_t sbz = 0; __asm__ volatile ( @@ -1328,6 +1330,22 @@ arm_cp15_data_cache_clean_and_invalidate(void) : [sbz] "r" (sbz) : "memory" ); +#else + /* + * Assume this is an ARM926EJ-S. Use the test, clean, and invalidate DCache + * operation. + */ + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "1:\n" + "mrc p15, 0, r15, c7, c14, 3\n" + "bne 1b\n" + ARM_SWITCH_BACK + : ARM_SWITCH_OUTPUT + : + : "memory" + ); +#endif } ARM_CP15_TEXT_SECTION static inline void diff --git a/cpukit/score/cpu/arm/include/rtems/asm.h b/cpukit/score/cpu/arm/include/rtems/asm.h index 0bbe43c837..9f676e40ab 100644 --- a/cpukit/score/cpu/arm/include/rtems/asm.h +++ b/cpukit/score/cpu/arm/include/rtems/asm.h @@ -3,7 +3,10 @@ /** * @file * - * @brief ARM Assembler Support API + * @ingroup RTEMSScoreCPUARMASM + * + * @brief This header file provides interfaces to address problems caused by + * incompatible flavor of assemblers and toolsets. * * This include file attempts to address the problems * caused by incompatible flavors of assemblers and @@ -86,15 +89,13 @@ #define __REGISTER_PREFIX__ #endif -#include <rtems/concat.h> - /* Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) +#define SYM(x) RTEMS_XCONCAT(__USER_LABEL_PREFIX__, x) /* Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) +#define REG(x) RTEMS_XCONCAT(__REGISTER_PREFIX__, x) /* * define macros for all of the registers on this CPU diff --git a/cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h b/cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h index d7244138ca..36541a97aa 100644 --- a/cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h +++ b/cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h @@ -10,7 +10,7 @@ */ /* - * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2020 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/arm/include/rtems/score/aarch32-system-registers.h b/cpukit/score/cpu/arm/include/rtems/score/aarch32-system-registers.h index 2c532ca669..5af0921547 100644 --- a/cpukit/score/cpu/arm/include/rtems/score/aarch32-system-registers.h +++ b/cpukit/score/cpu/arm/include/rtems/score/aarch32-system-registers.h @@ -10,7 +10,7 @@ */ /* - * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2020 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/arm/include/rtems/score/arm.h b/cpukit/score/cpu/arm/include/rtems/score/arm.h index 67fa579e67..650c48d55f 100644 --- a/cpukit/score/cpu/arm/include/rtems/score/arm.h +++ b/cpukit/score/cpu/arm/include/rtems/score/arm.h @@ -72,7 +72,8 @@ extern "C" { #ifndef ARM_DISABLE_THREAD_ID_REGISTER_USE #if defined(__ARM_ARCH_7A__) \ || defined(__ARM_ARCH_7R__) \ - || __ARM_ARCH >= 8 + || __ARM_ARCH >= 8 \ + || __ARM_ARCH == 6 #define ARM_MULTILIB_HAS_THREAD_ID_REGISTER #endif #endif diff --git a/cpukit/score/cpu/arm/include/rtems/score/armv4.h b/cpukit/score/cpu/arm/include/rtems/score/armv4.h index 7f40fb66ce..1d3a6de5ff 100644 --- a/cpukit/score/cpu/arm/include/rtems/score/armv4.h +++ b/cpukit/score/cpu/arm/include/rtems/score/armv4.h @@ -1,7 +1,16 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPUARM + * + * @brief This header file provides interfaces of the ARMv4 architecture + * support. + */ + /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -34,6 +43,12 @@ extern "C" { #endif /* __cplusplus */ +/** + * @addtogroup RTEMSScoreCPUARM + * + * @{ + */ + #ifdef ARM_MULTILIB_ARCH_V4 void bsp_interrupt_dispatch( void ); @@ -104,6 +119,8 @@ static inline void _ARMV4_Status_restore( uint32_t psr ) #endif /* ARM_MULTILIB_ARCH_V4 */ +/** @} */ + #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/cpukit/score/cpu/arm/include/rtems/score/armv7m.h b/cpukit/score/cpu/arm/include/rtems/score/armv7m.h index 10b3955671..7fa48b3aa5 100644 --- a/cpukit/score/cpu/arm/include/rtems/score/armv7m.h +++ b/cpukit/score/cpu/arm/include/rtems/score/armv7m.h @@ -3,7 +3,10 @@ /** * @file * - * @brief ARMV7M Architecture Support + * @ingroup RTEMSScoreCPUARM + * + * @brief This header file provides interfaces of the ARMv7-M architecture + * support. */ /* @@ -156,8 +159,19 @@ typedef struct { #define ARMV7M_SCB_SHCSR_MEMFAULTENA (1U << 16) uint32_t shcsr; +#define ARMV7M_SCB_CFSR_MMFSR_MASK 0xff +#define ARMV7M_SCB_CFSR_MMFSR_GET(n) (n & ARMV7M_SCB_CFSR_MMFSR_MASK) +#define ARMV7M_SCB_CFSR_BFSR_MASK 0xff00 +#define ARMV7M_SCB_CFSR_BFSR_GET(n) (n & ARMV7M_SCB_CFSR_BFSR_MASK) +#define ARMV7M_SCB_CFSR_UFSR_MASK 0xffff0000 +#define ARMV7M_SCB_CFSR_UFSR_GET(n) (n & ARMV7M_SCB_CFSR_UFSR_MASK) uint32_t cfsr; + +#define ARMV7M_SCB_HFSR_VECTTBL_MASK 0x2 +#define ARMV7M_SCB_HFSR_FORCED_MASK (1U << 30) +#define ARMV7M_SCB_HFSR_DEBUGEVT_MASK (1U << 31) uint32_t hfsr; + uint32_t dfsr; uint32_t mmfar; uint32_t bfar; @@ -691,6 +705,7 @@ static inline void _ARMV7M_MPU_Disable_region( } static inline void _ARMV7M_MPU_Setup( + uint32_t ctrl, const ARMV7M_MPU_Region_config *cfg, size_t cfg_count ) @@ -726,7 +741,7 @@ static inline void _ARMV7M_MPU_Setup( _ARMV7M_MPU_Disable_region(mpu, region); } - mpu->ctrl = ARMV7M_MPU_CTRL_ENABLE | ARMV7M_MPU_CTRL_PRIVDEFENA; + mpu->ctrl = ctrl; scb->shcsr |= ARMV7M_SCB_SHCSR_MEMFAULTENA; _ARM_Data_synchronization_barrier(); diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu.h b/cpukit/score/cpu/arm/include/rtems/score/cpu.h index 7ac180ac26..a462b48cf1 100644 --- a/cpukit/score/cpu/arm/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/arm/include/rtems/score/cpu.h @@ -3,14 +3,17 @@ /** * @file * - * @brief ARM Architecture Support API + * @ingroup RTEMSScoreCPUARM + * + * @brief This header file defines implementation interfaces pertaining to the + * port of the executive to the ARM architecture. */ /* * This include file contains information pertaining to the ARM * processor. * - * Copyright (c) 2009, 2017 embedded brains GmbH + * Copyright (C) 2009, 2017 embedded brains GmbH & Co. KG * * Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com> * @@ -176,9 +179,7 @@ #define CPU_MAXIMUM_PROCESSORS 32 -#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER - #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44 -#endif +#define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44 #ifdef ARM_MULTILIB_VFP #define ARM_CONTEXT_CONTROL_D8_OFFSET 48 @@ -191,10 +192,8 @@ #ifdef RTEMS_SMP #if defined(ARM_MULTILIB_VFP) #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112 - #elif defined(ARM_MULTILIB_HAS_THREAD_ID_REGISTER) - #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48 #else - #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 44 + #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48 #endif #endif @@ -240,9 +239,7 @@ typedef struct { #else void *register_sp; #endif -#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER uint32_t thread_id; -#endif #ifdef ARM_MULTILIB_VFP uint64_t register_d8; uint64_t register_d9; @@ -402,7 +399,7 @@ static inline void arm_interrupt_flash( uint32_t level ) #define _CPU_ISR_Flash( _isr_cookie ) \ arm_interrupt_flash( _isr_cookie ) -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { #if defined(ARM_MULTILIB_ARCH_V4) return ( level & 0x80 ) == 0; @@ -574,14 +571,6 @@ uint32_t _CPU_Counter_frequency( void ); CPU_Counter_ticks _CPU_Counter_read( void ); -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - void *_CPU_Thread_Idle_body( uintptr_t ignored ); #if defined(ARM_MULTILIB_ARCH_V4) @@ -596,7 +585,7 @@ typedef enum { ARM_EXCEPTION_IRQ = 6, ARM_EXCEPTION_FIQ = 7, MAX_EXCEPTIONS = 8, - ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff + ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0x7fffffff } Arm_symbolic_exception_name; #endif /* defined(ARM_MULTILIB_ARCH_V4) */ diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/arm/include/rtems/score/cpuatomic.h deleted file mode 100644 index 01bb99cda3..0000000000 --- a/cpukit/score/cpu/arm/include/rtems/score/cpuatomic.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include <rtems/score/cpustdatomic.h> - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h index 4f20113b71..04d23f0ea7 100644 --- a/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h @@ -3,11 +3,14 @@ /** * @file * - * @brief CPU Port Implementation API + * @ingroup RTEMSScoreCPUARM + * + * @brief This header file defines implementation interfaces pertaining to the + * port of the executive to the ARM architecture. */ /* - * Copyright (c) 2013, 2016 embedded brains GmbH + * Copyright (C) 2013, 2016 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -60,6 +63,8 @@ #endif /* ARM_MULTILIB_ARCH_V4 */ +#define CPU_THREAD_LOCAL_STORAGE_VARIANT 11 + #ifndef ASM #ifdef __cplusplus @@ -150,17 +155,17 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern ); void _CPU_Context_validate( uintptr_t pattern ); -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( "udf" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( const Context_Control *context ) { @@ -173,6 +178,13 @@ RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( #endif } +static inline void *_CPU_Get_TLS_thread_pointer( + const Context_Control *context +) +{ + return (void *) context->thread_id; +} + #ifdef __cplusplus } #endif diff --git a/cpukit/score/cpu/arm/include/rtems/score/paravirt.h b/cpukit/score/cpu/arm/include/rtems/score/paravirt.h index e3fb9009ad..4aa98499ad 100644 --- a/cpukit/score/cpu/arm/include/rtems/score/paravirt.h +++ b/cpukit/score/cpu/arm/include/rtems/score/paravirt.h @@ -3,10 +3,10 @@ /** * @file * - * @brief ARM Paravirtualization Definitions + * @ingroup RTEMSScoreCPUARMParavirt * - * This include file contains definitions pertaining to paravirtualization - * of the ARM port. + * @brief This header file provides definitions pertaining to + * paravirtualization of the ARM port. */ /* |