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Diffstat (limited to '')
-rw-r--r-- | cpukit/dev/i2c/xilinx-axi-i2c.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpukit/dev/i2c/xilinx-axi-i2c.c b/cpukit/dev/i2c/xilinx-axi-i2c.c index 11b0658161..fc8b4dd92c 100644 --- a/cpukit/dev/i2c/xilinx-axi-i2c.c +++ b/cpukit/dev/i2c/xilinx-axi-i2c.c @@ -502,7 +502,7 @@ xilinx_axi_i2c_read_rx_fifo(xilinx_axi_i2c_bus* bus) * One more byte to be received. This is set up by programming the RX * FIFO programmable depth interrupt register with a value that is 2 * less than the number we need (the register is minus 1). When we have - * one byte left disable the TX error interrupt because setting the NO + * one byte left, disable the TX error interrupt because setting the NO * ACK bit in the command register causes a TX error interrupt. Set the * TXAK bit in the CR to not-acknowledge the next byte received telling * the slave sender the master accepts no more data, then read the |