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-rw-r--r--c/src/exec/score/cpu/sh/ispsh7045.c321
-rw-r--r--c/src/exec/score/cpu/sh/rtems/score/iosh7045.h321
-rw-r--r--c/src/exec/score/cpu/sh/rtems/score/ispsh7045.h211
-rw-r--r--c/src/lib/libcpu/sh/sh7045/include/iosh7045.h321
-rw-r--r--c/src/lib/libcpu/sh/sh7045/include/ispsh7045.h211
-rw-r--r--c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c321
6 files changed, 1706 insertions, 0 deletions
diff --git a/c/src/exec/score/cpu/sh/ispsh7045.c b/c/src/exec/score/cpu/sh/ispsh7045.c
new file mode 100644
index 0000000000..b535840f9f
--- /dev/null
+++ b/c/src/exec/score/cpu/sh/ispsh7045.c
@@ -0,0 +1,321 @@
+/*
+ * This file contains the isp frames for the user interrupts.
+ * From these procedures __ISR_Handler is called with the vector number
+ * as argument.
+ *
+ * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
+ * some releases of gcc doesn't properly handle #pragma interrupt, if a
+ * file contains both isrs and normal functions.
+ *
+ * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ * Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
+ *
+ *
+ * COPYRIGHT (c) 1998.
+ * On-Line Applications Research Corporation (OAR).
+ * Copyright assigned to U.S. Government, 1994.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * Modified to reflect isp entries for sh7045 processor:
+ * John M. Mills (jmills@tga.com)
+ * TGA Technologies, Inc.
+ * 100 Pinnacle Way, Suite 140
+ * Norcross, GA 30071 U.S.A.
+ * August, 1999
+ *
+ * This modified file may be copied and distributed in accordance
+ * the above-referenced license. It is provided for critique and
+ * developmental purposes without any warranty nor representation
+ * by the authors or by TGA Technologies.
+ *
+ * $Id$
+ */
+
+/**************************************************************************
+ * Note this file contains two pair of independent sections which are
+ * used conditionally, depending on whether the module is being built
+ * for the SH703x or SH704x families of processor
+ **************************************************************************/
+
+#include <rtems/system.h>
+#include <rtems/score/shtypes.h>
+
+#if !defined (sh7045)
+#error Wrong CPU MODEL
+#endif
+
+/*
+ * This is a exception vector table
+ *
+ * It has the same structure as the actual vector table (vectab)
+ */
+
+
+/* SH-2 ISR Table */
+#include <rtems/score/ispsh7045.h>
+
+proc_ptr _Hardware_isr_Table[256]={
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* PWRon Reset, Maual Reset,...*/
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp,
+_nmi_isp, _usb_isp, /* irq 11, 12*/
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp,
+/* trapa 0 -31 */
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, /* external H/W: irq 64-71 */
+_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
+_dma0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DMAC: irq 72-87*/
+_dma1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dma2_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dma3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_mtua0_isp, _mtub0_isp, _mtuc0_isp, _mtud0_isp, /* MTUs: irq 88-127 */
+_mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_mtua1_isp, _mtub1_isp, _dummy_isp, _dummy_isp,
+_mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp,
+_mtua2_isp, _mtub2_isp, _dummy_isp, _dummy_isp,
+_mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp,
+_mtua3_isp, _mtub3_isp, _mtuc3_isp, _mtud3_isp,
+_mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_mtua4_isp, _mtub4_isp, _mtuc4_isp, _mtud4_isp,
+_mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, /* SCI0-1: irq 128-135*/
+_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
+_adi0_isp, _adi1_isp, _dummy_isp, _dummy_isp, /* ADC0-1: irq 136-139*/
+_dtci_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DTU: irq 140-143 */
+_cmt0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* CMT0-1: irq 144-151 */
+_cmt1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_wdt_isp, /* WDT: irq 152*/
+_bsc_isp, _dummy_isp, _dummy_isp, /* BSC: irq 153-155*/
+_oei_isp, /* I/O Port: irq 156*/
+};
+
+#define Str(a)#a
+
+/*
+ * Some versions of gcc and all version of egcs at least until egcs-1.1b
+ * are not able to handle #pragma interrupt correctly if more than 1 isr is
+ * contained in a file and when optimizing.
+ * We try to work around this problem by using the macro below.
+ */
+#define isp( name, number, func)\
+asm (".global _"Str(name)"\n\t" \
+ "_"Str(name)": \n\t" \
+ " mov.l r0,@-r15 \n\t" \
+ " mov.l r1,@-r15 \n\t" \
+ " mov.l r2,@-r15 \n\t" \
+ " mov.l r3,@-r15 \n\t" \
+ " mov.l r4,@-r15 \n\t" \
+ " mov.l r5,@-r15 \n\t" \
+ " mov.l r6,@-r15 \n\t" \
+ " mov.l r7,@-r15 \n\t" \
+ " mov.l r14,@-r15 \n\t" \
+ " sts.l pr,@-r15 \n\t" \
+ " sts.l mach,@-r15 \n\t" \
+ " sts.l macl,@-r15 \n\t" \
+ " mov r15,r14 \n\t" \
+ " mov.l "Str(name)"_k, r1\n\t" \
+ " jsr @r1 \n\t" \
+ " mov #"Str(number)", r4\n\t" \
+ " mov r14,r15 \n\t" \
+ " lds.l @r15+,macl \n\t" \
+ " lds.l @r15+,mach \n\t" \
+ " lds.l @r15+,pr \n\t" \
+ " mov.l @r15+,r14 \n\t" \
+ " mov.l @r15+,r7 \n\t" \
+ " mov.l @r15+,r6 \n\t" \
+ " mov.l @r15+,r5 \n\t" \
+ " mov.l @r15+,r4 \n\t" \
+ " mov.l @r15+,r3 \n\t" \
+ " mov.l @r15+,r2 \n\t" \
+ " mov.l @r15+,r1 \n\t" \
+ " mov.l @r15+,r0 \n\t" \
+ " rte \n\t" \
+ " nop \n\t" \
+ " .align 2 \n\t" \
+ #name"_k: \n\t" \
+ ".long "Str(func));
+
+/************************************************
+ * Dummy interrupt service procedure for
+ * interrupts being not allowed --> Trap 34
+ ************************************************/
+asm(" .section .text
+.global __dummy_isp
+__dummy_isp:
+ mov.l r14,@-r15
+ mov r15, r14
+ trapa #34
+ mov.l @r15+,r14
+ rte
+ nop");
+
+/*******************************************************************
+ * ISP Vector Table for sh7045 family of processors *
+ *******************************************************************/
+
+
+/*****************************
+ * Non maskable interrupt
+ *****************************/
+isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * User break controller
+ *****************************/
+isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * External interrupts 0-7
+ *****************************/
+isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
+isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
+isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
+isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
+isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
+isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
+isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
+isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * DMA - controller
+ *****************************/
+isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
+isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
+isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
+isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Match timer unit
+ *****************************/
+
+/*****************************
+ * Timer 0
+ *****************************/
+isp( _mtua0_isp, MTUA0_ISP_V, ___ISR_Handler);
+isp( _mtub0_isp, MTUB0_ISP_V, ___ISR_Handler);
+isp( _mtuc0_isp, MTUC0_ISP_V, ___ISR_Handler);
+isp( _mtud0_isp, MTUD0_ISP_V, ___ISR_Handler);
+isp( _mtuv0_isp, MTUV0_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 1
+ *****************************/
+isp( _mtua1_isp, MTUA1_ISP_V, ___ISR_Handler);
+isp( _mtub1_isp, MTUB1_ISP_V, ___ISR_Handler);
+isp( _mtuv1_isp, MTUV1_ISP_V, ___ISR_Handler);
+isp( _mtuu1_isp, MTUU1_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 2
+ *****************************/
+isp( _mtua2_isp, MTUA2_ISP_V, ___ISR_Handler);
+isp( _mtub2_isp, MTUB2_ISP_V, ___ISR_Handler);
+isp( _mtuv2_isp, MTUV2_ISP_V, ___ISR_Handler);
+isp( _mtuu2_isp, MTUU2_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 3
+ *****************************/
+isp( _mtua3_isp, MTUA3_ISP_V, ___ISR_Handler);
+isp( _mtub3_isp, MTUB3_ISP_V, ___ISR_Handler);
+isp( _mtuc3_isp, MTUC3_ISP_V, ___ISR_Handler);
+isp( _mtud3_isp, MTUD3_ISP_V, ___ISR_Handler);
+isp( _mtuv3_isp, MTUV3_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 4
+ *****************************/
+isp( _mtua4_isp, MTUA4_ISP_V, ___ISR_Handler);
+isp( _mtub4_isp, MTUB4_ISP_V, ___ISR_Handler);
+isp( _mtuc4_isp, MTUC4_ISP_V, ___ISR_Handler);
+isp( _mtud4_isp, MTUD4_ISP_V, ___ISR_Handler);
+isp( _mtuv4_isp, MTUV4_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Serial interfaces
+ *****************************/
+
+/*****************************
+ * Serial interface 0
+ *****************************/
+isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler);
+isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler);
+isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler);
+isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Serial interface 1
+ *****************************/
+isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler);
+isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler);
+isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler);
+isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * A/D converters
+ * ADC0-1
+ ******************************/
+isp( _adi0_isp, ADI0_ISP_V, ___ISR_Handler);
+isp( _adi1_isp, ADI1_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * Data transfer controller
+ ******************************/
+isp( _dtci_isp, DTC_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * Counter match timer
+ ******************************/
+isp( _cmt0_isp, CMT0_ISP_V, ___ISR_Handler);
+isp( _cmt1_isp, CMT1_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * Watchdog timer
+ ******************************/
+isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * DRAM refresh control unit
+ * of bus state controller
+ ******************************/
+isp( _bsc_isp, CMI_ISP_V, ___ISR_Handler);
+
+/******************************
+ * I/O port
+ ******************************/
+isp( _oei_isp, OEI_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Parity control unit of
+ * the bus state controller
+ * NOT PROVIDED IN SH-2
+ *****************************/
+/* isp( _prt_isp, PRT_ISP_V, ___ISR_Handler); */
diff --git a/c/src/exec/score/cpu/sh/rtems/score/iosh7045.h b/c/src/exec/score/cpu/sh/rtems/score/iosh7045.h
new file mode 100644
index 0000000000..327cd34f86
--- /dev/null
+++ b/c/src/exec/score/cpu/sh/rtems/score/iosh7045.h
@@ -0,0 +1,321 @@
+/*
+ * This include file contains information pertaining to the Hitachi SH
+ * processor.
+ *
+ * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
+ *
+ * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ * Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
+ * contained no copyright notice.
+ *
+ * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ * COPYRIGHT (c) 1998.
+ * On-Line Applications Research Corporation (OAR).
+ * Copyright assigned to U.S. Government, 1994.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * Modified to reflect on-chip registers for sh7045 processor, based on
+ * "Register.h" distributed with Hitachi's EVB7045F tutorials, and which
+ * contained no copyright notice:
+ * John M. Mills (jmills@tga.com)
+ * TGA Technologies, Inc.
+ * 100 Pinnacle Way, Suite 140
+ * Norcross, GA 30071 U.S.A.
+ * August, 1999
+ *
+ * This modified file may be copied and distributed in accordance
+ * the above-referenced license. It is provided for critique and
+ * developmental purposes without any warranty nor representation
+ * by the authors or by TGA Technologies.
+ *
+ * $Id$
+ */
+
+#ifndef __IOSH7045_H
+#define __IOSH7045_H
+
+/*
+ * After each line is explained whether the access is char short or long.
+ * The functions read/writeb, w, l, 8, 16, 32 can be found
+ * in exec/score/cpu/sh/sh_io.h
+ *
+ * 8 bit == char ( readb, writeb, read8, write8)
+ * 16 bit == short ( readw, writew, read16, write16 )
+ * 32 bit == long ( readl, writel, read32, write32 )
+ * JMM: Addresses noted "[char, ]short,word" are per Hitachi _SuperH_RISC_
+ * ENGINE_..Hardware_Manual; alignment access-restrictions may apply
+ */
+
+#define REG_BASE 0xFFFF8000
+
+/* SCI0 Registers */
+#define SCI_SMR0 (REG_BASE + 0x01a0) /*char: Serial mode ch 0 */
+#define SCI_BRR0 (REG_BASE + 0x01a1) /*char: Bit rate ch 0 */
+#define SCI_SCR0 (REG_BASE + 0x01a2) /*char: Serial control ch 0 */
+#define SCI_TDR0 (REG_BASE + 0x01a3) /*char: Transmit data ch 0 */
+#define SCI_SSR0 (REG_BASE + 0x01a4) /*char: Serial status ch 0 */
+#define SCI_RDR0 (REG_BASE + 0x01a5) /*char: Receive data ch 0 */
+
+/* SCI1 Registers */
+#define SCI_SMR1 (REG_BASE + 0x01b0) /* char: Serial mode ch 1 */
+#define SCI_BRR1 (REG_BASE + 0x01b1) /* char: Bit rate ch 1 */
+#define SCI_SCR1 (REG_BASE + 0x01b2) /* char: Serial control ch 1 */
+#define SCI_TDR1 (REG_BASE + 0x01b3) /* char: Transmit data ch 1 */
+#define SCI_SSR1 (REG_BASE + 0x01b4) /* char: Serial status ch 1 */
+#define SCI_RDR1 (REG_BASE + 0x01b5) /* char: Receive data ch 1 */
+
+/* ADI */
+/* High Speed A/D (Excluding A-Mask Part)*/
+#define ADDRA (REG_BASE + 0x03F0) /* short */
+#define ADDRB (REG_BASE + 0x03F2) /* short */
+#define ADDRC (REG_BASE + 0x03F4) /* short */
+#define ADDRD (REG_BASE + 0x03F6) /* short */
+#define ADDRE (REG_BASE + 0x03F8) /* short */
+#define ADDRF (REG_BASE + 0x03FA) /* short */
+#define ADDRG (REG_BASE + 0x03FC) /* short */
+#define ADDRH (REG_BASE + 0x03FE) /* short */
+#define ADCSR (REG_BASE + 0x03E0) /* char */
+#define ADCR (REG_BASE + 0x03E1) /* char */
+
+/* Mid-Speed A/D (A-Mask part)*/
+#define ADDRA0 (REG_BASE + 0x0400) /* char, short */
+#define ADDRA0H (REG_BASE + 0x0400) /* char, short */
+#define ADDRA0L (REG_BASE + 0x0401) /* char */
+#define ADDRB0 (REG_BASE + 0x0402) /* char, short */
+#define ADDRB0H (REG_BASE + 0x0402) /* char, short */
+#define ADDRB0L (REG_BASE + 0x0403) /* char */
+#define ADDRC0 (REG_BASE + 0x0404) /* char, short */
+#define ADDRC0H (REG_BASE + 0x0404) /* char, short */
+#define ADDRC0L (REG_BASE + 0x0405) /* char */
+#define ADDRD0 (REG_BASE + 0x0406) /* char, short */
+#define ADDRD0H (REG_BASE + 0x0406) /* char, short */
+#define ADDRD0L (REG_BASE + 0x0407) /* char */
+#define ADCSR0 (REG_BASE + 0x0410) /* char */
+#define ADCR0 (REG_BASE + 0x0412) /* char */
+#define ADDRA1 (REG_BASE + 0x0408) /* char, short */
+#define ADDRA1H (REG_BASE + 0x0408) /* char, short */
+#define ADDRA1L (REG_BASE + 0x0409) /* char */
+#define ADDRB1 (REG_BASE + 0x040A) /* char, short */
+#define ADDRB1H (REG_BASE + 0x040A) /* char, short */
+#define ADDRB1L (REG_BASE + 0x040B) /* char */
+#define ADDRC1 (REG_BASE + 0x040C) /* char, short */
+#define ADDRC1H (REG_BASE + 0x040C) /* char, short */
+#define ADDRC1L (REG_BASE + 0x040D) /* char */
+#define ADDRD1 (REG_BASE + 0x040E) /* char, short */
+#define ADDRD1H (REG_BASE + 0x040E) /* char, short */
+#define ADDRD1L (REG_BASE + 0x040F) /* char */
+#define ADCSR1 (REG_BASE + 0x0411) /* char */
+#define ADCR1 (REG_BASE + 0x0413) /* char */
+
+/*MTU SHARED*/
+#define MTU_TSTR (REG_BASE + 0x0240) /* char, short, word */
+#define MTU_TSYR (REG_BASE + 0x0241) /* char, short, word */
+#define MTU_ICSR (REG_BASE + 0x03C0) /* input lev. CSR */
+#define MTU_OCSR (REG_BASE + 0x03C0) /* output lev. CSR */
+
+/*MTU CHANNEL 0*/
+#define MTU_TCR0 (REG_BASE + 0x0260) /* char, short, word */
+#define MTU_TMDR0 (REG_BASE + 0x0261) /* char, short, word */
+#define MTU_TIORH0 (REG_BASE + 0x0262) /* char, short, word */
+#define MTU_TIORL0 (REG_BASE + 0x0263) /* char, short, word */
+#define MTU_TIER0 (REG_BASE + 0x0264) /* char, short, word */
+#define MTU_TSR0 (REG_BASE + 0x0265) /* char, short, word */
+#define MTU_TCNT0 (REG_BASE + 0x0266) /* short, word */
+#define MTU_GR0A (REG_BASE + 0x0268) /* short, word */
+#define MTU_GR0B (REG_BASE + 0x026A) /* short, word */
+#define MTU_GR0C (REG_BASE + 0x026C) /* short, word */
+#define MTU_GR0D (REG_BASE + 0x026E) /* short, word */
+
+/*MTU CHANNEL 1*/
+#define MTU_TCR1 (REG_BASE + 0x0280) /* char, short, word */
+#define MTU_TMDR1 (REG_BASE + 0x0281) /* char, short, word */
+#define MTU_TIOR1 (REG_BASE + 0x0282) /* char, short, word */
+#define MTU_TIER1 (REG_BASE + 0x0284) /* char, short, word */
+#define MTU_TSR1 (REG_BASE + 0x0285) /* char, short, word */
+#define MTU_TCNT1 (REG_BASE + 0x0286) /* short, word */
+#define MTU_GR1A (REG_BASE + 0x0288) /* short, word */
+#define MTU_GR1B (REG_BASE + 0x028A) /* short, word */
+
+/*MTU CHANNEL 2*/
+#define MTU_TCR2 (REG_BASE + 0x02A0) /* char, short, word */
+#define MTU_TMDR2 (REG_BASE + 0x02A1) /* char, short, word */
+#define MTU_TIOR2 (REG_BASE + 0x02A2) /* char, short, word */
+#define MTU_TIER2 (REG_BASE + 0x02A4) /* char, short, word */
+#define MTU_TSR2 (REG_BASE + 0x02A5) /* char, short, word */
+#define MTU_TCNT2 (REG_BASE + 0x02A6) /* short, word */
+#define MTU_GR2A (REG_BASE + 0x02A8) /* short, word */
+#define MTU_GR2B (REG_BASE + 0x02AA) /* short, word */
+
+/*MTU CHANNELS 3-4 SHARED*/
+#define MTU_TOER (REG_BASE + 0x020A) /* char, short, word */
+#define MTU_TOCR (REG_BASE + 0x020B) /* char, short, word */
+#define MTU_TGCR (REG_BASE + 0x020D) /* char, short, word */
+#define MTU_TCDR (REG_BASE + 0x0214) /* short, word */
+#define MTU_TDDR (REG_BASE + 0x0216) /* short, word */
+#define MTU_TCNTS (REG_BASE + 0x0220) /* short, word */
+#define MTU_TCBR (REG_BASE + 0x0222) /* short, word */
+
+/*MTU CHANNEL 3*/
+#define MTU_TCR3 (REG_BASE + 0x0200) /* char, short, word */
+#define MTU_TMDR3 (REG_BASE + 0x0202) /* char, short, word */
+#define MTU_TIORH3 (REG_BASE + 0x0204) /* char, short, word */
+#define MTU_TIORL3 (REG_BASE + 0x0205) /* char, short, word */
+#define MTU_TIER3 (REG_BASE + 0x0208) /* char, short, word */
+#define MTU_TSR3 (REG_BASE + 0x022C) /* char, short, word */
+#define MTU_TCNT3 (REG_BASE + 0x0210) /* short, word */
+#define MTU_GR3A (REG_BASE + 0x0218) /* short, word */
+#define MTU_GR3B (REG_BASE + 0x021A) /* short, word */
+#define MTU_GR3C (REG_BASE + 0x0224) /* short, word */
+#define MTU_GR3D (REG_BASE + 0x0226) /* short, word */
+
+/*MTU CHANNEL 4*/
+#define MTU_TCR4 (REG_BASE + 0x0201) /* char, short, word */
+#define MTU_TMDR4 (REG_BASE + 0x0203) /* char, short, word */
+#define MTU_TIOR4 (REG_BASE + 0x0206) /* char, short, word */
+#define MTU_TIORH4 (REG_BASE + 0x0206) /* char, short, word */
+#define MTU_TIORL4 (REG_BASE + 0x0207) /* char, short, word */
+#define MTU_TIER4 (REG_BASE + 0x0209) /* char, short, word */
+#define MTU_TSR4 (REG_BASE + 0x022D) /* char, short, word */
+#define MTU_TCNT4 (REG_BASE + 0x0212) /* short, word */
+#define MTU_GR4A (REG_BASE + 0x021C) /* short, word */
+#define MTU_GR4B (REG_BASE + 0x021E) /* short, word */
+#define MTU_GR4C (REG_BASE + 0x0228) /* short, word */
+#define MTU_GR4D (REG_BASE + 0x022A) /* short, word */
+
+/*DMAC CHANNELS 0-3 SHARED*/
+#define DMAOR (REG_BASE + 0x06B0) /* short */
+
+/*DMAC CHANNEL 0*/
+#define DMA_SAR0 (REG_BASE + 0x06C0) /* short, word */
+#define DMA_DAR0 (REG_BASE + 0x06C4) /* short, word */
+#define DMA_DMATCR0 (REG_BASE + 0x06C8) /* short, word */
+#define DMA_CHCR0 (REG_BASE + 0x06CC) /* short, word */
+
+/*DMAC CHANNEL 1*/
+#define DMA_SAR1 (REG_BASE + 0x06D0) /* short, word */
+#define DMA_DAR1 (REG_BASE + 0x06D4) /* short, word */
+#define DMA_DMATCR1 (REG_BASE + 0x06D8) /* short, wordt */
+#define DMA_CHCR1 (REG_BASE + 0x06DC) /* short, word */
+
+/*DMAC CHANNEL 3*/
+#define DMA_SAR3 (REG_BASE + 0x06E0) /* short, word */
+#define DMA_DAR3 (REG_BASE + 0x06E4) /* short, word */
+#define DMA_DMATCR3 (REG_BASE + 0x06E8) /* short, word */
+#define DMA_CHCR3 (REG_BASE + 0x06EC) /* short, word */
+
+/*DMAC CHANNEL 4*/
+#define DMA_SAR4 (REG_BASE + 0x06F0) /* short, word */
+#define DMA_DAR4 (REG_BASE + 0x06F4) /* short, word */
+#define DMA_DMATCR4 (REG_BASE + 0x06F8) /* short, word */
+#define DMA_CHCR4 (REG_BASE + 0x06FC) /* short, word */
+
+/*Data Transfer Controller*/
+#define DTC_DTEA (REG_BASE + 0x0700) /* char, short, word */
+#define DTC_DTEB (REG_BASE + 0x0701) /* char, short(?), word(?) */
+#define DTC_DTEC (REG_BASE + 0x0702) /* char, short(?), word(?) */
+#define DTC_DTED (REG_BASE + 0x0703) /* char, short(?), word(?) */
+#define DTC_DTEE (REG_BASE + 0x0704) /* char, short(?), word(?) */
+#define DTC_DTCSR (REG_BASE + 0x0706) /* char, short, word */
+#define DTC_DTBR (REG_BASE + 0x0708) /* short, word */
+
+/*Cache Memory*/
+#define CAC_CCR (REG_BASE + 0x0740) /* char, short, word */
+
+/*INTC*/
+#define INTC_IPRA (REG_BASE + 0x0348) /* char, short, word */
+#define INTC_IPRB (REG_BASE + 0x034A) /* char, short, word */
+#define INTC_IPRC (REG_BASE + 0x034C) /* char, short, word */
+#define INTC_IPRD (REG_BASE + 0x034E) /* char, short, word */
+#define INTC_IPRE (REG_BASE + 0x0350) /* char, short, word */
+#define INTC_IPRF (REG_BASE + 0x0352) /* char, short, word */
+#define INTC_IPRG (REG_BASE + 0x0354) /* char, short, word */
+#define INTC_IPRH (REG_BASE + 0x0356) /* char, short, word */
+#define INTC_ICR (REG_BASE + 0x0358) /* char, short, word */
+#define INTC_ISR (REG_BASE + 0x035A) /* char, short, word */
+
+/*Flash (F-ZTAT)*/
+#define FL_FLMCR1 (REG_BASE + 0x0580) /* Fl.Mem.Contr.Reg 1: char */
+#define FL_FLMCR2 (REG_BASE + 0x0581) /* Fl.Mem.Contr.Reg 2: char */
+#define FL_EBR1 (REG_BASE + 0x0582) /* Fl.Mem.Erase Blk.1: char */
+#define FL_EBR2 (REG_BASE + 0x0584) /* Fl.Mem.Erase Blk.2: char */
+#define FL_RAMER (REG_BASE + 0x0628) /* Ram Emul.Reg.- char,short,word */
+
+/*UBC*/
+#define UBC_BARH (REG_BASE + 0x0600) /* char, short, word */
+#define UBC_BARL (REG_BASE + 0x0602) /* char, short, word */
+#define UBC_BAMRH (REG_BASE + 0x0604) /* char, short, word */
+#define UBC_BAMRL (REG_BASE + 0x0606) /* char, short, word */
+#define UBC_BBR (REG_BASE + 0x0608) /* char, short, word */
+/*BSC*/
+#define BSC_BCR1 (REG_BASE + 0x0620) /* short */
+#define BSC_BCR2 (REG_BASE + 0x0622) /* short */
+#define BSC_WCR1 (REG_BASE + 0x0624) /* short */
+#define BSC_WCR2 (REG_BASE + 0x0626) /* short */
+#define BSC_DCR (REG_BASE + 0x062A) /* short */
+#define BSC_RTCSR (REG_BASE + 0x062C) /* short */
+#define BSC_RTCNT (REG_BASE + 0x062E) /* short */
+#define BSC_RTCOR (REG_BASE + 0x0630) /* short */
+
+/*WDT*/
+#define WDT_R_TCSR (REG_BASE + 0x0610) /* rd: char */
+#define WDT_R_TCNT (REG_BASE + 0x0611) /* rd: char */
+#define WDT_R_RSTCSR (REG_BASE + 0x0613) /* rd: char */
+#define WDT_W_TCSR (REG_BASE + 0x0610) /* wrt: short */
+#define WDT_W_TCNT (REG_BASE + 0x0610) /* wrt: short */
+#define WDT_W_RSTCSR (REG_BASE + 0x0612) /* wrt: short */
+
+/*POWER DOWN STATE*/
+#define PDT_SBYCR (REG_BASE + 0x0614) /* char */
+
+/* Port I/O Control Registers */
+#define IO_PADRH (REG_BASE + 0x0380) /* Port A Data Register */
+#define IO_PADRL (REG_BASE + 0x0382) /* Port A Data Register */
+#define IO_PBDR (REG_BASE + 0x0390) /* Port B Data Register */
+#define IO_PCDR (REG_BASE + 0x0392) /* Port C Data Register */
+#define IO_PDDRH (REG_BASE + 0x03A0) /* Port D Data Register */
+#define IO_PDDRL (REG_BASE + 0x03A2) /* Port D Data Register */
+#define IO_PEDR (REG_BASE + 0x03B0) /* Port E Data Register */
+#define IO_PFDR (REG_BASE + 0x03B2) /* Port F Data Register */
+
+/*Pin Function Control Register*/
+#define PFC_PAIORH (REG_BASE + 0x0384) /* Port A I/O Reg. H */
+#define PFC_PAIORL (REG_BASE + 0x0386) /* Port A I/O Reg. L */
+#define PFC_PACRH (REG_BASE + 0x0388) /* Port A Ctr. Reg. H */
+#define PFC_PACRL1 (REG_BASE + 0x038C) /* Port A Ctr. Reg. L1 */
+#define PFC_PACRL2 (REG_BASE + 0x038E) /* Port A Ctr. Reg. L2 */
+#define PFC_PBIOR (REG_BASE + 0x0394) /* Port B I/O Register */
+#define PFC_PBCR1 (REG_BASE + 0x0398) /* Port B Ctr. Reg. R1 */
+#define PFC_PBCR2 (REG_BASE + 0x039A) /* Port B Ctr. Reg. R2 */
+#define PFC_PCIOR (REG_BASE + 0x0396) /* Port C I/O Register */
+#define PFC_PCCR (REG_BASE + 0x039C) /* Port C Ctr. Reg. */
+#define PFC_PDIORH (REG_BASE + 0x03A4) /* Port D I/O Reg. H */
+#define PFC_PDIORL (REG_BASE + 0x03A6) /* Port D I/O Reg. L */
+#define PFC_PDCRH1 (REG_BASE + 0x03A8) /* Port D Ctr. Reg. H1 */
+#define PFC_PDCRH2 (REG_BASE + 0x03AA) /* Port D Ctr. Reg. H2 */
+#define PFC_PDCRL (REG_BASE + 0x03AC) /* Port D Ctr. Reg. L */
+#define PFC_PEIOR (REG_BASE + 0x03B4) /* Port E I/O Register */
+#define PFC_PECR1 (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */
+#define PFC_PECR2 (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */
+#define PFC_IFCR (REG_BASE + 0x03C8) /* short */
+
+/*Compare/Match Timer*/
+#define CMT_CMSTR (REG_BASE + 0x3D0) /* Start Reg. char, short, word */
+#define CMT_CMCSR0 (REG_BASE + 0x3D2) /* C0 SCR short, word */
+#define CMT_CMCNT0 (REG_BASE + 0x3D4) /* C0 Counter char, short, word */
+#define CMT_CMCOR0 (REG_BASE + 0x3D6) /* C0 Const.Reg. char, short, word */
+#define CMT_CMCSR1 (REG_BASE + 0x3D8) /* C1 SCR short, word */
+#define CMT_CMCNT1 (REG_BASE + 0x3DA) /* C1 Counter char, short, word */
+#define CMT_CMCOR1 (REG_BASE + 0x3DC) /* C1 Const.Reg. char, short, word */
+
+#endif
diff --git a/c/src/exec/score/cpu/sh/rtems/score/ispsh7045.h b/c/src/exec/score/cpu/sh/rtems/score/ispsh7045.h
new file mode 100644
index 0000000000..e711bb1a21
--- /dev/null
+++ b/c/src/exec/score/cpu/sh/rtems/score/ispsh7045.h
@@ -0,0 +1,211 @@
+/*
+ * This include file contains information pertaining to the Hitachi SH
+ * processor.
+ *
+ * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ * Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ * COPYRIGHT (c) 1998.
+ * On-Line Applications Research Corporation (OAR).
+ * Copyright assigned to U.S. Government, 1994.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * Modified to reflect isp entries for sh7045 processor:
+ * John M. Mills (jmills@tga.com)
+ * TGA Technologies, Inc.
+ * 100 Pinnacle Way, Suite 140
+ * Norcross, GA 30071 U.S.A.
+ *
+ *
+ * This modified file may be copied and distributed in accordance
+ * the above-referenced license. It is provided for critique and
+ * developmental purposes without any warranty nor representation
+ * by the authors or by TGA Technologies.
+ *
+ * $Id$
+ */
+
+#ifndef __CPU_ISPS_H
+#define __CPU_ISPS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems/score/shtypes.h>
+
+extern void __ISR_Handler( unsigned32 vector );
+
+
+/*
+ * interrupt vector table offsets
+ */
+#define NMI_ISP_V 11
+#define USB_ISP_V 12
+#define IRQ0_ISP_V 64
+#define IRQ1_ISP_V 65
+#define IRQ2_ISP_V 66
+#define IRQ3_ISP_V 67
+#define IRQ4_ISP_V 68
+#define IRQ5_ISP_V 69
+#define IRQ6_ISP_V 70
+#define IRQ7_ISP_V 71
+#define DMA0_ISP_V 72
+#define DMA1_ISP_V 76
+#define DMA2_ISP_V 80
+#define DMA3_ISP_V 84
+
+#define MTUA0_ISP_V 88
+#define MTUB0_ISP_V 89
+#define MTUC0_ISP_V 90
+#define MTUD0_ISP_V 91
+#define MTUV0_ISP_V 92
+
+#define MTUA1_ISP_V 96
+#define MTUB1_ISP_V 97
+#define MTUV1_ISP_V 100
+#define MTUU1_ISP_V 101
+
+#define MTUA2_ISP_V 104
+#define MTUB2_ISP_V 105
+#define MTUV2_ISP_V 108
+#define MTUU2_ISP_V 109
+
+#define MTUA3_ISP_V 112
+#define MTUB3_ISP_V 113
+#define MTUC3_ISP_V 114
+#define MTUD3_ISP_V 115
+#define MTUV3_ISP_V 116
+
+#define MTUA4_ISP_V 120
+#define MTUB4_ISP_V 121
+#define MTUC4_ISP_V 122
+#define MTUD4_ISP_V 123
+#define MTUV4_ISP_V 124
+
+#define ERI0_ISP_V 128
+#define RXI0_ISP_V 129
+#define TXI0_ISP_V 130
+#define TEI0_ISP_V 131
+
+#define ERI1_ISP_V 132
+#define RXI1_ISP_V 133
+#define TXI1_ISP_V 134
+#define TEI1_ISP_V 135
+
+#define ADI0_ISP_V 136
+#define ADI1_ISP_V 137
+#define DTC_ISP_V 140 /* Data Transfer Controller */
+#define CMT0_ISP_V 144 /* Compare Match Timer */
+#define CMT1_ISP_V 148
+#define WDT_ISP_V 152 /* Wtachdog Timer */
+#define CMI_ISP_V 153 /* BSC RAS interrupt */
+#define OEI_ISP_V 156 /* I/O Port */
+#define DREF_ISP_V CMI_ISP_V /* DRAM Refresh from BSC */
+#if 0
+#define PRT_ISP_V /* parity error - no equivalent */
+#endif
+
+/* dummy ISP */
+extern void _dummy_isp( void );
+
+/* Non Maskable Interrupt */
+extern void _nmi_isp( void );
+
+/* User Break Controller */
+extern void _usb_isp( void );
+
+/* External interrupts 0-7 */
+extern void _irq0_isp( void );
+extern void _irq1_isp( void );
+extern void _irq2_isp( void );
+extern void _irq3_isp( void );
+extern void _irq4_isp( void );
+extern void _irq5_isp( void );
+extern void _irq6_isp( void );
+extern void _irq7_isp( void );
+
+/* DMA - Controller */
+extern void _dma0_isp( void );
+extern void _dma1_isp( void );
+extern void _dma2_isp( void );
+extern void _dma3_isp( void );
+
+/* Interrupt Timer Unit */
+/* Timer 0 */
+extern void _mtua0_isp( void );
+extern void _mtub0_isp( void );
+extern void _mtuc0_isp( void );
+extern void _mtud0_isp( void );
+extern void _mtuv0_isp( void );
+/* Timer 1 */
+extern void _mtua1_isp( void );
+extern void _mtub1_isp( void );
+extern void _mtuv1_isp( void );
+extern void _mtuu1_isp( void );
+/* Timer 2 */
+extern void _mtua2_isp( void );
+extern void _mtub2_isp( void );
+extern void _mtuv2_isp( void );
+extern void _mtuu2_isp( void );
+/* Timer 3 */
+extern void _mtua3_isp( void );
+extern void _mtub3_isp( void );
+extern void _mtuc3_isp( void );
+extern void _mtud3_isp( void );
+extern void _mtuv3_isp( void );
+/* Timer 4 */
+extern void _mtua4_isp( void );
+extern void _mtub4_isp( void );
+extern void _mtuc4_isp( void );
+extern void _mtud4_isp( void );
+extern void _mtuv4_isp( void );
+
+/* serial interfaces */
+extern void _eri0_isp( void );
+extern void _rxi0_isp( void );
+extern void _txi0_isp( void );
+extern void _tei0_isp( void );
+extern void _eri1_isp( void );
+extern void _rxi1_isp( void );
+extern void _txi1_isp( void );
+extern void _tei1_isp( void );
+
+/* ADC */
+extern void _adi0_isp( void );
+extern void _adi1_isp( void );
+
+/* Data Transfer Controller */
+extern void _dtci_isp( void );
+
+/* Compare Match Timer */
+extern void _cmt0_isp( void );
+extern void _cmt1_isp( void );
+
+/* Watchdog Timer */
+extern void _wdt_isp( void );
+
+/* DRAM refresh control unit of bus state controller */
+extern void _bsc_isp( void );
+
+/* I/O Port */
+extern void _oei_isp( void );
+
+/* Parity Control Unit of the Bus State Controllers */
+/* extern void _prt_isp( void ); */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/lib/libcpu/sh/sh7045/include/iosh7045.h b/c/src/lib/libcpu/sh/sh7045/include/iosh7045.h
new file mode 100644
index 0000000000..327cd34f86
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7045/include/iosh7045.h
@@ -0,0 +1,321 @@
+/*
+ * This include file contains information pertaining to the Hitachi SH
+ * processor.
+ *
+ * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
+ *
+ * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ * Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
+ * contained no copyright notice.
+ *
+ * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ * COPYRIGHT (c) 1998.
+ * On-Line Applications Research Corporation (OAR).
+ * Copyright assigned to U.S. Government, 1994.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * Modified to reflect on-chip registers for sh7045 processor, based on
+ * "Register.h" distributed with Hitachi's EVB7045F tutorials, and which
+ * contained no copyright notice:
+ * John M. Mills (jmills@tga.com)
+ * TGA Technologies, Inc.
+ * 100 Pinnacle Way, Suite 140
+ * Norcross, GA 30071 U.S.A.
+ * August, 1999
+ *
+ * This modified file may be copied and distributed in accordance
+ * the above-referenced license. It is provided for critique and
+ * developmental purposes without any warranty nor representation
+ * by the authors or by TGA Technologies.
+ *
+ * $Id$
+ */
+
+#ifndef __IOSH7045_H
+#define __IOSH7045_H
+
+/*
+ * After each line is explained whether the access is char short or long.
+ * The functions read/writeb, w, l, 8, 16, 32 can be found
+ * in exec/score/cpu/sh/sh_io.h
+ *
+ * 8 bit == char ( readb, writeb, read8, write8)
+ * 16 bit == short ( readw, writew, read16, write16 )
+ * 32 bit == long ( readl, writel, read32, write32 )
+ * JMM: Addresses noted "[char, ]short,word" are per Hitachi _SuperH_RISC_
+ * ENGINE_..Hardware_Manual; alignment access-restrictions may apply
+ */
+
+#define REG_BASE 0xFFFF8000
+
+/* SCI0 Registers */
+#define SCI_SMR0 (REG_BASE + 0x01a0) /*char: Serial mode ch 0 */
+#define SCI_BRR0 (REG_BASE + 0x01a1) /*char: Bit rate ch 0 */
+#define SCI_SCR0 (REG_BASE + 0x01a2) /*char: Serial control ch 0 */
+#define SCI_TDR0 (REG_BASE + 0x01a3) /*char: Transmit data ch 0 */
+#define SCI_SSR0 (REG_BASE + 0x01a4) /*char: Serial status ch 0 */
+#define SCI_RDR0 (REG_BASE + 0x01a5) /*char: Receive data ch 0 */
+
+/* SCI1 Registers */
+#define SCI_SMR1 (REG_BASE + 0x01b0) /* char: Serial mode ch 1 */
+#define SCI_BRR1 (REG_BASE + 0x01b1) /* char: Bit rate ch 1 */
+#define SCI_SCR1 (REG_BASE + 0x01b2) /* char: Serial control ch 1 */
+#define SCI_TDR1 (REG_BASE + 0x01b3) /* char: Transmit data ch 1 */
+#define SCI_SSR1 (REG_BASE + 0x01b4) /* char: Serial status ch 1 */
+#define SCI_RDR1 (REG_BASE + 0x01b5) /* char: Receive data ch 1 */
+
+/* ADI */
+/* High Speed A/D (Excluding A-Mask Part)*/
+#define ADDRA (REG_BASE + 0x03F0) /* short */
+#define ADDRB (REG_BASE + 0x03F2) /* short */
+#define ADDRC (REG_BASE + 0x03F4) /* short */
+#define ADDRD (REG_BASE + 0x03F6) /* short */
+#define ADDRE (REG_BASE + 0x03F8) /* short */
+#define ADDRF (REG_BASE + 0x03FA) /* short */
+#define ADDRG (REG_BASE + 0x03FC) /* short */
+#define ADDRH (REG_BASE + 0x03FE) /* short */
+#define ADCSR (REG_BASE + 0x03E0) /* char */
+#define ADCR (REG_BASE + 0x03E1) /* char */
+
+/* Mid-Speed A/D (A-Mask part)*/
+#define ADDRA0 (REG_BASE + 0x0400) /* char, short */
+#define ADDRA0H (REG_BASE + 0x0400) /* char, short */
+#define ADDRA0L (REG_BASE + 0x0401) /* char */
+#define ADDRB0 (REG_BASE + 0x0402) /* char, short */
+#define ADDRB0H (REG_BASE + 0x0402) /* char, short */
+#define ADDRB0L (REG_BASE + 0x0403) /* char */
+#define ADDRC0 (REG_BASE + 0x0404) /* char, short */
+#define ADDRC0H (REG_BASE + 0x0404) /* char, short */
+#define ADDRC0L (REG_BASE + 0x0405) /* char */
+#define ADDRD0 (REG_BASE + 0x0406) /* char, short */
+#define ADDRD0H (REG_BASE + 0x0406) /* char, short */
+#define ADDRD0L (REG_BASE + 0x0407) /* char */
+#define ADCSR0 (REG_BASE + 0x0410) /* char */
+#define ADCR0 (REG_BASE + 0x0412) /* char */
+#define ADDRA1 (REG_BASE + 0x0408) /* char, short */
+#define ADDRA1H (REG_BASE + 0x0408) /* char, short */
+#define ADDRA1L (REG_BASE + 0x0409) /* char */
+#define ADDRB1 (REG_BASE + 0x040A) /* char, short */
+#define ADDRB1H (REG_BASE + 0x040A) /* char, short */
+#define ADDRB1L (REG_BASE + 0x040B) /* char */
+#define ADDRC1 (REG_BASE + 0x040C) /* char, short */
+#define ADDRC1H (REG_BASE + 0x040C) /* char, short */
+#define ADDRC1L (REG_BASE + 0x040D) /* char */
+#define ADDRD1 (REG_BASE + 0x040E) /* char, short */
+#define ADDRD1H (REG_BASE + 0x040E) /* char, short */
+#define ADDRD1L (REG_BASE + 0x040F) /* char */
+#define ADCSR1 (REG_BASE + 0x0411) /* char */
+#define ADCR1 (REG_BASE + 0x0413) /* char */
+
+/*MTU SHARED*/
+#define MTU_TSTR (REG_BASE + 0x0240) /* char, short, word */
+#define MTU_TSYR (REG_BASE + 0x0241) /* char, short, word */
+#define MTU_ICSR (REG_BASE + 0x03C0) /* input lev. CSR */
+#define MTU_OCSR (REG_BASE + 0x03C0) /* output lev. CSR */
+
+/*MTU CHANNEL 0*/
+#define MTU_TCR0 (REG_BASE + 0x0260) /* char, short, word */
+#define MTU_TMDR0 (REG_BASE + 0x0261) /* char, short, word */
+#define MTU_TIORH0 (REG_BASE + 0x0262) /* char, short, word */
+#define MTU_TIORL0 (REG_BASE + 0x0263) /* char, short, word */
+#define MTU_TIER0 (REG_BASE + 0x0264) /* char, short, word */
+#define MTU_TSR0 (REG_BASE + 0x0265) /* char, short, word */
+#define MTU_TCNT0 (REG_BASE + 0x0266) /* short, word */
+#define MTU_GR0A (REG_BASE + 0x0268) /* short, word */
+#define MTU_GR0B (REG_BASE + 0x026A) /* short, word */
+#define MTU_GR0C (REG_BASE + 0x026C) /* short, word */
+#define MTU_GR0D (REG_BASE + 0x026E) /* short, word */
+
+/*MTU CHANNEL 1*/
+#define MTU_TCR1 (REG_BASE + 0x0280) /* char, short, word */
+#define MTU_TMDR1 (REG_BASE + 0x0281) /* char, short, word */
+#define MTU_TIOR1 (REG_BASE + 0x0282) /* char, short, word */
+#define MTU_TIER1 (REG_BASE + 0x0284) /* char, short, word */
+#define MTU_TSR1 (REG_BASE + 0x0285) /* char, short, word */
+#define MTU_TCNT1 (REG_BASE + 0x0286) /* short, word */
+#define MTU_GR1A (REG_BASE + 0x0288) /* short, word */
+#define MTU_GR1B (REG_BASE + 0x028A) /* short, word */
+
+/*MTU CHANNEL 2*/
+#define MTU_TCR2 (REG_BASE + 0x02A0) /* char, short, word */
+#define MTU_TMDR2 (REG_BASE + 0x02A1) /* char, short, word */
+#define MTU_TIOR2 (REG_BASE + 0x02A2) /* char, short, word */
+#define MTU_TIER2 (REG_BASE + 0x02A4) /* char, short, word */
+#define MTU_TSR2 (REG_BASE + 0x02A5) /* char, short, word */
+#define MTU_TCNT2 (REG_BASE + 0x02A6) /* short, word */
+#define MTU_GR2A (REG_BASE + 0x02A8) /* short, word */
+#define MTU_GR2B (REG_BASE + 0x02AA) /* short, word */
+
+/*MTU CHANNELS 3-4 SHARED*/
+#define MTU_TOER (REG_BASE + 0x020A) /* char, short, word */
+#define MTU_TOCR (REG_BASE + 0x020B) /* char, short, word */
+#define MTU_TGCR (REG_BASE + 0x020D) /* char, short, word */
+#define MTU_TCDR (REG_BASE + 0x0214) /* short, word */
+#define MTU_TDDR (REG_BASE + 0x0216) /* short, word */
+#define MTU_TCNTS (REG_BASE + 0x0220) /* short, word */
+#define MTU_TCBR (REG_BASE + 0x0222) /* short, word */
+
+/*MTU CHANNEL 3*/
+#define MTU_TCR3 (REG_BASE + 0x0200) /* char, short, word */
+#define MTU_TMDR3 (REG_BASE + 0x0202) /* char, short, word */
+#define MTU_TIORH3 (REG_BASE + 0x0204) /* char, short, word */
+#define MTU_TIORL3 (REG_BASE + 0x0205) /* char, short, word */
+#define MTU_TIER3 (REG_BASE + 0x0208) /* char, short, word */
+#define MTU_TSR3 (REG_BASE + 0x022C) /* char, short, word */
+#define MTU_TCNT3 (REG_BASE + 0x0210) /* short, word */
+#define MTU_GR3A (REG_BASE + 0x0218) /* short, word */
+#define MTU_GR3B (REG_BASE + 0x021A) /* short, word */
+#define MTU_GR3C (REG_BASE + 0x0224) /* short, word */
+#define MTU_GR3D (REG_BASE + 0x0226) /* short, word */
+
+/*MTU CHANNEL 4*/
+#define MTU_TCR4 (REG_BASE + 0x0201) /* char, short, word */
+#define MTU_TMDR4 (REG_BASE + 0x0203) /* char, short, word */
+#define MTU_TIOR4 (REG_BASE + 0x0206) /* char, short, word */
+#define MTU_TIORH4 (REG_BASE + 0x0206) /* char, short, word */
+#define MTU_TIORL4 (REG_BASE + 0x0207) /* char, short, word */
+#define MTU_TIER4 (REG_BASE + 0x0209) /* char, short, word */
+#define MTU_TSR4 (REG_BASE + 0x022D) /* char, short, word */
+#define MTU_TCNT4 (REG_BASE + 0x0212) /* short, word */
+#define MTU_GR4A (REG_BASE + 0x021C) /* short, word */
+#define MTU_GR4B (REG_BASE + 0x021E) /* short, word */
+#define MTU_GR4C (REG_BASE + 0x0228) /* short, word */
+#define MTU_GR4D (REG_BASE + 0x022A) /* short, word */
+
+/*DMAC CHANNELS 0-3 SHARED*/
+#define DMAOR (REG_BASE + 0x06B0) /* short */
+
+/*DMAC CHANNEL 0*/
+#define DMA_SAR0 (REG_BASE + 0x06C0) /* short, word */
+#define DMA_DAR0 (REG_BASE + 0x06C4) /* short, word */
+#define DMA_DMATCR0 (REG_BASE + 0x06C8) /* short, word */
+#define DMA_CHCR0 (REG_BASE + 0x06CC) /* short, word */
+
+/*DMAC CHANNEL 1*/
+#define DMA_SAR1 (REG_BASE + 0x06D0) /* short, word */
+#define DMA_DAR1 (REG_BASE + 0x06D4) /* short, word */
+#define DMA_DMATCR1 (REG_BASE + 0x06D8) /* short, wordt */
+#define DMA_CHCR1 (REG_BASE + 0x06DC) /* short, word */
+
+/*DMAC CHANNEL 3*/
+#define DMA_SAR3 (REG_BASE + 0x06E0) /* short, word */
+#define DMA_DAR3 (REG_BASE + 0x06E4) /* short, word */
+#define DMA_DMATCR3 (REG_BASE + 0x06E8) /* short, word */
+#define DMA_CHCR3 (REG_BASE + 0x06EC) /* short, word */
+
+/*DMAC CHANNEL 4*/
+#define DMA_SAR4 (REG_BASE + 0x06F0) /* short, word */
+#define DMA_DAR4 (REG_BASE + 0x06F4) /* short, word */
+#define DMA_DMATCR4 (REG_BASE + 0x06F8) /* short, word */
+#define DMA_CHCR4 (REG_BASE + 0x06FC) /* short, word */
+
+/*Data Transfer Controller*/
+#define DTC_DTEA (REG_BASE + 0x0700) /* char, short, word */
+#define DTC_DTEB (REG_BASE + 0x0701) /* char, short(?), word(?) */
+#define DTC_DTEC (REG_BASE + 0x0702) /* char, short(?), word(?) */
+#define DTC_DTED (REG_BASE + 0x0703) /* char, short(?), word(?) */
+#define DTC_DTEE (REG_BASE + 0x0704) /* char, short(?), word(?) */
+#define DTC_DTCSR (REG_BASE + 0x0706) /* char, short, word */
+#define DTC_DTBR (REG_BASE + 0x0708) /* short, word */
+
+/*Cache Memory*/
+#define CAC_CCR (REG_BASE + 0x0740) /* char, short, word */
+
+/*INTC*/
+#define INTC_IPRA (REG_BASE + 0x0348) /* char, short, word */
+#define INTC_IPRB (REG_BASE + 0x034A) /* char, short, word */
+#define INTC_IPRC (REG_BASE + 0x034C) /* char, short, word */
+#define INTC_IPRD (REG_BASE + 0x034E) /* char, short, word */
+#define INTC_IPRE (REG_BASE + 0x0350) /* char, short, word */
+#define INTC_IPRF (REG_BASE + 0x0352) /* char, short, word */
+#define INTC_IPRG (REG_BASE + 0x0354) /* char, short, word */
+#define INTC_IPRH (REG_BASE + 0x0356) /* char, short, word */
+#define INTC_ICR (REG_BASE + 0x0358) /* char, short, word */
+#define INTC_ISR (REG_BASE + 0x035A) /* char, short, word */
+
+/*Flash (F-ZTAT)*/
+#define FL_FLMCR1 (REG_BASE + 0x0580) /* Fl.Mem.Contr.Reg 1: char */
+#define FL_FLMCR2 (REG_BASE + 0x0581) /* Fl.Mem.Contr.Reg 2: char */
+#define FL_EBR1 (REG_BASE + 0x0582) /* Fl.Mem.Erase Blk.1: char */
+#define FL_EBR2 (REG_BASE + 0x0584) /* Fl.Mem.Erase Blk.2: char */
+#define FL_RAMER (REG_BASE + 0x0628) /* Ram Emul.Reg.- char,short,word */
+
+/*UBC*/
+#define UBC_BARH (REG_BASE + 0x0600) /* char, short, word */
+#define UBC_BARL (REG_BASE + 0x0602) /* char, short, word */
+#define UBC_BAMRH (REG_BASE + 0x0604) /* char, short, word */
+#define UBC_BAMRL (REG_BASE + 0x0606) /* char, short, word */
+#define UBC_BBR (REG_BASE + 0x0608) /* char, short, word */
+/*BSC*/
+#define BSC_BCR1 (REG_BASE + 0x0620) /* short */
+#define BSC_BCR2 (REG_BASE + 0x0622) /* short */
+#define BSC_WCR1 (REG_BASE + 0x0624) /* short */
+#define BSC_WCR2 (REG_BASE + 0x0626) /* short */
+#define BSC_DCR (REG_BASE + 0x062A) /* short */
+#define BSC_RTCSR (REG_BASE + 0x062C) /* short */
+#define BSC_RTCNT (REG_BASE + 0x062E) /* short */
+#define BSC_RTCOR (REG_BASE + 0x0630) /* short */
+
+/*WDT*/
+#define WDT_R_TCSR (REG_BASE + 0x0610) /* rd: char */
+#define WDT_R_TCNT (REG_BASE + 0x0611) /* rd: char */
+#define WDT_R_RSTCSR (REG_BASE + 0x0613) /* rd: char */
+#define WDT_W_TCSR (REG_BASE + 0x0610) /* wrt: short */
+#define WDT_W_TCNT (REG_BASE + 0x0610) /* wrt: short */
+#define WDT_W_RSTCSR (REG_BASE + 0x0612) /* wrt: short */
+
+/*POWER DOWN STATE*/
+#define PDT_SBYCR (REG_BASE + 0x0614) /* char */
+
+/* Port I/O Control Registers */
+#define IO_PADRH (REG_BASE + 0x0380) /* Port A Data Register */
+#define IO_PADRL (REG_BASE + 0x0382) /* Port A Data Register */
+#define IO_PBDR (REG_BASE + 0x0390) /* Port B Data Register */
+#define IO_PCDR (REG_BASE + 0x0392) /* Port C Data Register */
+#define IO_PDDRH (REG_BASE + 0x03A0) /* Port D Data Register */
+#define IO_PDDRL (REG_BASE + 0x03A2) /* Port D Data Register */
+#define IO_PEDR (REG_BASE + 0x03B0) /* Port E Data Register */
+#define IO_PFDR (REG_BASE + 0x03B2) /* Port F Data Register */
+
+/*Pin Function Control Register*/
+#define PFC_PAIORH (REG_BASE + 0x0384) /* Port A I/O Reg. H */
+#define PFC_PAIORL (REG_BASE + 0x0386) /* Port A I/O Reg. L */
+#define PFC_PACRH (REG_BASE + 0x0388) /* Port A Ctr. Reg. H */
+#define PFC_PACRL1 (REG_BASE + 0x038C) /* Port A Ctr. Reg. L1 */
+#define PFC_PACRL2 (REG_BASE + 0x038E) /* Port A Ctr. Reg. L2 */
+#define PFC_PBIOR (REG_BASE + 0x0394) /* Port B I/O Register */
+#define PFC_PBCR1 (REG_BASE + 0x0398) /* Port B Ctr. Reg. R1 */
+#define PFC_PBCR2 (REG_BASE + 0x039A) /* Port B Ctr. Reg. R2 */
+#define PFC_PCIOR (REG_BASE + 0x0396) /* Port C I/O Register */
+#define PFC_PCCR (REG_BASE + 0x039C) /* Port C Ctr. Reg. */
+#define PFC_PDIORH (REG_BASE + 0x03A4) /* Port D I/O Reg. H */
+#define PFC_PDIORL (REG_BASE + 0x03A6) /* Port D I/O Reg. L */
+#define PFC_PDCRH1 (REG_BASE + 0x03A8) /* Port D Ctr. Reg. H1 */
+#define PFC_PDCRH2 (REG_BASE + 0x03AA) /* Port D Ctr. Reg. H2 */
+#define PFC_PDCRL (REG_BASE + 0x03AC) /* Port D Ctr. Reg. L */
+#define PFC_PEIOR (REG_BASE + 0x03B4) /* Port E I/O Register */
+#define PFC_PECR1 (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */
+#define PFC_PECR2 (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */
+#define PFC_IFCR (REG_BASE + 0x03C8) /* short */
+
+/*Compare/Match Timer*/
+#define CMT_CMSTR (REG_BASE + 0x3D0) /* Start Reg. char, short, word */
+#define CMT_CMCSR0 (REG_BASE + 0x3D2) /* C0 SCR short, word */
+#define CMT_CMCNT0 (REG_BASE + 0x3D4) /* C0 Counter char, short, word */
+#define CMT_CMCOR0 (REG_BASE + 0x3D6) /* C0 Const.Reg. char, short, word */
+#define CMT_CMCSR1 (REG_BASE + 0x3D8) /* C1 SCR short, word */
+#define CMT_CMCNT1 (REG_BASE + 0x3DA) /* C1 Counter char, short, word */
+#define CMT_CMCOR1 (REG_BASE + 0x3DC) /* C1 Const.Reg. char, short, word */
+
+#endif
diff --git a/c/src/lib/libcpu/sh/sh7045/include/ispsh7045.h b/c/src/lib/libcpu/sh/sh7045/include/ispsh7045.h
new file mode 100644
index 0000000000..e711bb1a21
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7045/include/ispsh7045.h
@@ -0,0 +1,211 @@
+/*
+ * This include file contains information pertaining to the Hitachi SH
+ * processor.
+ *
+ * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ * Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ * COPYRIGHT (c) 1998.
+ * On-Line Applications Research Corporation (OAR).
+ * Copyright assigned to U.S. Government, 1994.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * Modified to reflect isp entries for sh7045 processor:
+ * John M. Mills (jmills@tga.com)
+ * TGA Technologies, Inc.
+ * 100 Pinnacle Way, Suite 140
+ * Norcross, GA 30071 U.S.A.
+ *
+ *
+ * This modified file may be copied and distributed in accordance
+ * the above-referenced license. It is provided for critique and
+ * developmental purposes without any warranty nor representation
+ * by the authors or by TGA Technologies.
+ *
+ * $Id$
+ */
+
+#ifndef __CPU_ISPS_H
+#define __CPU_ISPS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems/score/shtypes.h>
+
+extern void __ISR_Handler( unsigned32 vector );
+
+
+/*
+ * interrupt vector table offsets
+ */
+#define NMI_ISP_V 11
+#define USB_ISP_V 12
+#define IRQ0_ISP_V 64
+#define IRQ1_ISP_V 65
+#define IRQ2_ISP_V 66
+#define IRQ3_ISP_V 67
+#define IRQ4_ISP_V 68
+#define IRQ5_ISP_V 69
+#define IRQ6_ISP_V 70
+#define IRQ7_ISP_V 71
+#define DMA0_ISP_V 72
+#define DMA1_ISP_V 76
+#define DMA2_ISP_V 80
+#define DMA3_ISP_V 84
+
+#define MTUA0_ISP_V 88
+#define MTUB0_ISP_V 89
+#define MTUC0_ISP_V 90
+#define MTUD0_ISP_V 91
+#define MTUV0_ISP_V 92
+
+#define MTUA1_ISP_V 96
+#define MTUB1_ISP_V 97
+#define MTUV1_ISP_V 100
+#define MTUU1_ISP_V 101
+
+#define MTUA2_ISP_V 104
+#define MTUB2_ISP_V 105
+#define MTUV2_ISP_V 108
+#define MTUU2_ISP_V 109
+
+#define MTUA3_ISP_V 112
+#define MTUB3_ISP_V 113
+#define MTUC3_ISP_V 114
+#define MTUD3_ISP_V 115
+#define MTUV3_ISP_V 116
+
+#define MTUA4_ISP_V 120
+#define MTUB4_ISP_V 121
+#define MTUC4_ISP_V 122
+#define MTUD4_ISP_V 123
+#define MTUV4_ISP_V 124
+
+#define ERI0_ISP_V 128
+#define RXI0_ISP_V 129
+#define TXI0_ISP_V 130
+#define TEI0_ISP_V 131
+
+#define ERI1_ISP_V 132
+#define RXI1_ISP_V 133
+#define TXI1_ISP_V 134
+#define TEI1_ISP_V 135
+
+#define ADI0_ISP_V 136
+#define ADI1_ISP_V 137
+#define DTC_ISP_V 140 /* Data Transfer Controller */
+#define CMT0_ISP_V 144 /* Compare Match Timer */
+#define CMT1_ISP_V 148
+#define WDT_ISP_V 152 /* Wtachdog Timer */
+#define CMI_ISP_V 153 /* BSC RAS interrupt */
+#define OEI_ISP_V 156 /* I/O Port */
+#define DREF_ISP_V CMI_ISP_V /* DRAM Refresh from BSC */
+#if 0
+#define PRT_ISP_V /* parity error - no equivalent */
+#endif
+
+/* dummy ISP */
+extern void _dummy_isp( void );
+
+/* Non Maskable Interrupt */
+extern void _nmi_isp( void );
+
+/* User Break Controller */
+extern void _usb_isp( void );
+
+/* External interrupts 0-7 */
+extern void _irq0_isp( void );
+extern void _irq1_isp( void );
+extern void _irq2_isp( void );
+extern void _irq3_isp( void );
+extern void _irq4_isp( void );
+extern void _irq5_isp( void );
+extern void _irq6_isp( void );
+extern void _irq7_isp( void );
+
+/* DMA - Controller */
+extern void _dma0_isp( void );
+extern void _dma1_isp( void );
+extern void _dma2_isp( void );
+extern void _dma3_isp( void );
+
+/* Interrupt Timer Unit */
+/* Timer 0 */
+extern void _mtua0_isp( void );
+extern void _mtub0_isp( void );
+extern void _mtuc0_isp( void );
+extern void _mtud0_isp( void );
+extern void _mtuv0_isp( void );
+/* Timer 1 */
+extern void _mtua1_isp( void );
+extern void _mtub1_isp( void );
+extern void _mtuv1_isp( void );
+extern void _mtuu1_isp( void );
+/* Timer 2 */
+extern void _mtua2_isp( void );
+extern void _mtub2_isp( void );
+extern void _mtuv2_isp( void );
+extern void _mtuu2_isp( void );
+/* Timer 3 */
+extern void _mtua3_isp( void );
+extern void _mtub3_isp( void );
+extern void _mtuc3_isp( void );
+extern void _mtud3_isp( void );
+extern void _mtuv3_isp( void );
+/* Timer 4 */
+extern void _mtua4_isp( void );
+extern void _mtub4_isp( void );
+extern void _mtuc4_isp( void );
+extern void _mtud4_isp( void );
+extern void _mtuv4_isp( void );
+
+/* serial interfaces */
+extern void _eri0_isp( void );
+extern void _rxi0_isp( void );
+extern void _txi0_isp( void );
+extern void _tei0_isp( void );
+extern void _eri1_isp( void );
+extern void _rxi1_isp( void );
+extern void _txi1_isp( void );
+extern void _tei1_isp( void );
+
+/* ADC */
+extern void _adi0_isp( void );
+extern void _adi1_isp( void );
+
+/* Data Transfer Controller */
+extern void _dtci_isp( void );
+
+/* Compare Match Timer */
+extern void _cmt0_isp( void );
+extern void _cmt1_isp( void );
+
+/* Watchdog Timer */
+extern void _wdt_isp( void );
+
+/* DRAM refresh control unit of bus state controller */
+extern void _bsc_isp( void );
+
+/* I/O Port */
+extern void _oei_isp( void );
+
+/* Parity Control Unit of the Bus State Controllers */
+/* extern void _prt_isp( void ); */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c b/c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c
new file mode 100644
index 0000000000..b535840f9f
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c
@@ -0,0 +1,321 @@
+/*
+ * This file contains the isp frames for the user interrupts.
+ * From these procedures __ISR_Handler is called with the vector number
+ * as argument.
+ *
+ * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
+ * some releases of gcc doesn't properly handle #pragma interrupt, if a
+ * file contains both isrs and normal functions.
+ *
+ * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ * Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
+ *
+ *
+ * COPYRIGHT (c) 1998.
+ * On-Line Applications Research Corporation (OAR).
+ * Copyright assigned to U.S. Government, 1994.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * Modified to reflect isp entries for sh7045 processor:
+ * John M. Mills (jmills@tga.com)
+ * TGA Technologies, Inc.
+ * 100 Pinnacle Way, Suite 140
+ * Norcross, GA 30071 U.S.A.
+ * August, 1999
+ *
+ * This modified file may be copied and distributed in accordance
+ * the above-referenced license. It is provided for critique and
+ * developmental purposes without any warranty nor representation
+ * by the authors or by TGA Technologies.
+ *
+ * $Id$
+ */
+
+/**************************************************************************
+ * Note this file contains two pair of independent sections which are
+ * used conditionally, depending on whether the module is being built
+ * for the SH703x or SH704x families of processor
+ **************************************************************************/
+
+#include <rtems/system.h>
+#include <rtems/score/shtypes.h>
+
+#if !defined (sh7045)
+#error Wrong CPU MODEL
+#endif
+
+/*
+ * This is a exception vector table
+ *
+ * It has the same structure as the actual vector table (vectab)
+ */
+
+
+/* SH-2 ISR Table */
+#include <rtems/score/ispsh7045.h>
+
+proc_ptr _Hardware_isr_Table[256]={
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* PWRon Reset, Maual Reset,...*/
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp,
+_nmi_isp, _usb_isp, /* irq 11, 12*/
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp,
+/* trapa 0 -31 */
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, /* external H/W: irq 64-71 */
+_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
+_dma0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DMAC: irq 72-87*/
+_dma1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dma2_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dma3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_mtua0_isp, _mtub0_isp, _mtuc0_isp, _mtud0_isp, /* MTUs: irq 88-127 */
+_mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_mtua1_isp, _mtub1_isp, _dummy_isp, _dummy_isp,
+_mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp,
+_mtua2_isp, _mtub2_isp, _dummy_isp, _dummy_isp,
+_mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp,
+_mtua3_isp, _mtub3_isp, _mtuc3_isp, _mtud3_isp,
+_mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_mtua4_isp, _mtub4_isp, _mtuc4_isp, _mtud4_isp,
+_mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, /* SCI0-1: irq 128-135*/
+_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
+_adi0_isp, _adi1_isp, _dummy_isp, _dummy_isp, /* ADC0-1: irq 136-139*/
+_dtci_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DTU: irq 140-143 */
+_cmt0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* CMT0-1: irq 144-151 */
+_cmt1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_wdt_isp, /* WDT: irq 152*/
+_bsc_isp, _dummy_isp, _dummy_isp, /* BSC: irq 153-155*/
+_oei_isp, /* I/O Port: irq 156*/
+};
+
+#define Str(a)#a
+
+/*
+ * Some versions of gcc and all version of egcs at least until egcs-1.1b
+ * are not able to handle #pragma interrupt correctly if more than 1 isr is
+ * contained in a file and when optimizing.
+ * We try to work around this problem by using the macro below.
+ */
+#define isp( name, number, func)\
+asm (".global _"Str(name)"\n\t" \
+ "_"Str(name)": \n\t" \
+ " mov.l r0,@-r15 \n\t" \
+ " mov.l r1,@-r15 \n\t" \
+ " mov.l r2,@-r15 \n\t" \
+ " mov.l r3,@-r15 \n\t" \
+ " mov.l r4,@-r15 \n\t" \
+ " mov.l r5,@-r15 \n\t" \
+ " mov.l r6,@-r15 \n\t" \
+ " mov.l r7,@-r15 \n\t" \
+ " mov.l r14,@-r15 \n\t" \
+ " sts.l pr,@-r15 \n\t" \
+ " sts.l mach,@-r15 \n\t" \
+ " sts.l macl,@-r15 \n\t" \
+ " mov r15,r14 \n\t" \
+ " mov.l "Str(name)"_k, r1\n\t" \
+ " jsr @r1 \n\t" \
+ " mov #"Str(number)", r4\n\t" \
+ " mov r14,r15 \n\t" \
+ " lds.l @r15+,macl \n\t" \
+ " lds.l @r15+,mach \n\t" \
+ " lds.l @r15+,pr \n\t" \
+ " mov.l @r15+,r14 \n\t" \
+ " mov.l @r15+,r7 \n\t" \
+ " mov.l @r15+,r6 \n\t" \
+ " mov.l @r15+,r5 \n\t" \
+ " mov.l @r15+,r4 \n\t" \
+ " mov.l @r15+,r3 \n\t" \
+ " mov.l @r15+,r2 \n\t" \
+ " mov.l @r15+,r1 \n\t" \
+ " mov.l @r15+,r0 \n\t" \
+ " rte \n\t" \
+ " nop \n\t" \
+ " .align 2 \n\t" \
+ #name"_k: \n\t" \
+ ".long "Str(func));
+
+/************************************************
+ * Dummy interrupt service procedure for
+ * interrupts being not allowed --> Trap 34
+ ************************************************/
+asm(" .section .text
+.global __dummy_isp
+__dummy_isp:
+ mov.l r14,@-r15
+ mov r15, r14
+ trapa #34
+ mov.l @r15+,r14
+ rte
+ nop");
+
+/*******************************************************************
+ * ISP Vector Table for sh7045 family of processors *
+ *******************************************************************/
+
+
+/*****************************
+ * Non maskable interrupt
+ *****************************/
+isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * User break controller
+ *****************************/
+isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * External interrupts 0-7
+ *****************************/
+isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
+isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
+isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
+isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
+isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
+isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
+isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
+isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * DMA - controller
+ *****************************/
+isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
+isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
+isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
+isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Match timer unit
+ *****************************/
+
+/*****************************
+ * Timer 0
+ *****************************/
+isp( _mtua0_isp, MTUA0_ISP_V, ___ISR_Handler);
+isp( _mtub0_isp, MTUB0_ISP_V, ___ISR_Handler);
+isp( _mtuc0_isp, MTUC0_ISP_V, ___ISR_Handler);
+isp( _mtud0_isp, MTUD0_ISP_V, ___ISR_Handler);
+isp( _mtuv0_isp, MTUV0_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 1
+ *****************************/
+isp( _mtua1_isp, MTUA1_ISP_V, ___ISR_Handler);
+isp( _mtub1_isp, MTUB1_ISP_V, ___ISR_Handler);
+isp( _mtuv1_isp, MTUV1_ISP_V, ___ISR_Handler);
+isp( _mtuu1_isp, MTUU1_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 2
+ *****************************/
+isp( _mtua2_isp, MTUA2_ISP_V, ___ISR_Handler);
+isp( _mtub2_isp, MTUB2_ISP_V, ___ISR_Handler);
+isp( _mtuv2_isp, MTUV2_ISP_V, ___ISR_Handler);
+isp( _mtuu2_isp, MTUU2_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 3
+ *****************************/
+isp( _mtua3_isp, MTUA3_ISP_V, ___ISR_Handler);
+isp( _mtub3_isp, MTUB3_ISP_V, ___ISR_Handler);
+isp( _mtuc3_isp, MTUC3_ISP_V, ___ISR_Handler);
+isp( _mtud3_isp, MTUD3_ISP_V, ___ISR_Handler);
+isp( _mtuv3_isp, MTUV3_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 4
+ *****************************/
+isp( _mtua4_isp, MTUA4_ISP_V, ___ISR_Handler);
+isp( _mtub4_isp, MTUB4_ISP_V, ___ISR_Handler);
+isp( _mtuc4_isp, MTUC4_ISP_V, ___ISR_Handler);
+isp( _mtud4_isp, MTUD4_ISP_V, ___ISR_Handler);
+isp( _mtuv4_isp, MTUV4_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Serial interfaces
+ *****************************/
+
+/*****************************
+ * Serial interface 0
+ *****************************/
+isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler);
+isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler);
+isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler);
+isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Serial interface 1
+ *****************************/
+isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler);
+isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler);
+isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler);
+isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * A/D converters
+ * ADC0-1
+ ******************************/
+isp( _adi0_isp, ADI0_ISP_V, ___ISR_Handler);
+isp( _adi1_isp, ADI1_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * Data transfer controller
+ ******************************/
+isp( _dtci_isp, DTC_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * Counter match timer
+ ******************************/
+isp( _cmt0_isp, CMT0_ISP_V, ___ISR_Handler);
+isp( _cmt1_isp, CMT1_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * Watchdog timer
+ ******************************/
+isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * DRAM refresh control unit
+ * of bus state controller
+ ******************************/
+isp( _bsc_isp, CMI_ISP_V, ___ISR_Handler);
+
+/******************************
+ * I/O port
+ ******************************/
+isp( _oei_isp, OEI_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Parity control unit of
+ * the bus state controller
+ * NOT PROVIDED IN SH-2
+ *****************************/
+/* isp( _prt_isp, PRT_ISP_V, ___ISR_Handler); */
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-19 10:46:39 +0000