diff options
Diffstat (limited to '')
37 files changed, 910 insertions, 602 deletions
diff --git a/c/src/exec/score/cpu/i960/Makefile.am b/c/src/exec/score/cpu/i960/Makefile.am index f26a4e9382..cd40092077 100644 --- a/c/src/exec/score/cpu/i960/Makefile.am +++ b/c/src/exec/score/cpu/i960/Makefile.am @@ -10,7 +10,7 @@ SUBDIRS = rtems C_FILES = cpu.c C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) -H_FILES = asm.h i960RP.h +H_FILES = asm.h S_FILES = cpu_asm.S S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) diff --git a/c/src/exec/score/cpu/i960/cpu.c b/c/src/exec/score/cpu/i960/cpu.c index 009e0d3ca4..78eeb3c5f2 100644 --- a/c/src/exec/score/cpu/i960/cpu.c +++ b/c/src/exec/score/cpu/i960/cpu.c @@ -11,18 +11,6 @@ * * $Id$ */ -/* - * 1999/04/26: added support for Intel i960RP - */ - -#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) -#elif defined(__i960RP__) -#elif defined(__i960KA__) - -#else -#warning "*** ENTIRE FILE IMPLEMENTED & TESTED FOR CA & RP ONLY ***" -#warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***" -#endif #include <rtems/system.h> #include <rtems/score/isr.h> @@ -64,45 +52,6 @@ unsigned32 _CPU_ISR_Get_level( void ) /*PAGE * - * _CPU_ISR_install_raw_handler - */ - -#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) -#define i960_vector_caching_enabled( _prcb ) \ - ((_prcb)->control_tbl->icon & 0x2000) -#elif defined(__i960RP__) -#define i960_vector_caching_enabled( _prcb ) \ - ((*((unsigned int *) ICON_ADDR)) & 0x2000) -#elif defined(__i960KA__) -#define i960_vector_caching_enabled( _prcb ) 0 -#endif - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - i960_PRCB *prcb = _CPU_Table.Prcb; - proc_ptr *cached_intr_tbl = NULL; - - /* The i80960CA does not support vectors 0-7. The first 9 entries - * in the Interrupt Table are used to manage pending interrupts. - * Thus vector 8, the first valid vector number, is actually in - * slot 9 in the table. - */ - - *old_handler = prcb->intr_tbl[ vector + 1 ]; - - prcb->intr_tbl[ vector + 1 ] = new_handler; - - if ( i960_vector_caching_enabled( prcb ) ) - if ( (vector & 0xf) == 0x2 ) /* cacheable? */ - cached_intr_tbl[ vector >> 4 ] = new_handler; -} - -/*PAGE - * * _CPU__ISR_install_vector * * Install the RTEMS vector wrapper in the CPU's interrupt table. @@ -130,60 +79,3 @@ void _CPU_ISR_install_vector( _ISR_Vector_table[ vector ] = new_handler; } - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) -#define soft_reset( prcb ) \ - { register i960_PRCB *_prcb = (prcb); \ - register unsigned32 *_next=0; \ - register unsigned32 _cmd = 0x30000; \ - asm volatile( "lda next,%1; \ - sysctl %0,%1,%2; \ - next: mov g0,g0" \ - : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ - : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ - } -#elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP) -#define soft_reset( prcb ) \ - { register i960_PRCB *_prcb = (prcb); \ - register unsigned32 *_next=0; \ - register unsigned32 _cmd = 0x300; \ - asm volatile( "lda next,%1; \ - sysctl %0,%1,%2; \ - next: mov g0,g0" \ - : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ - : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ - } -#elif defined(__i960KA__) -#define soft_reset( prcb ) -#endif - -void _CPU_Install_interrupt_stack( void ) -{ - i960_PRCB *prcb = _CPU_Table.Prcb; - unsigned32 level; -#if defined(__i960RP__) || defined(__i960_RP__) - unsigned32 *isp = (int *) ISP_ADDR; -#endif - - /* - * Set the Interrupt Stack in the PRCB and force a reload of it. - * Interrupts are disabled for safety. - */ - - _CPU_ISR_Disable( level ); - - prcb->intr_stack = _CPU_Interrupt_stack_low; - -#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) - soft_reset( prcb ); -#elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP) - *isp = (unsigned32) prcb->intr_stack; -#endif - - _CPU_ISR_Enable( level ); -} diff --git a/c/src/exec/score/cpu/i960/cpu_asm.S b/c/src/exec/score/cpu/i960/cpu_asm.S index 88b07a5b45..f78c1ac15d 100644 --- a/c/src/exec/score/cpu/i960/cpu_asm.S +++ b/c/src/exec/score/cpu/i960/cpu_asm.S @@ -1,7 +1,5 @@ -/* cpu_asm.s - * - * This file contains all assembly code for the i960CA implementation - * of RTEMS. +/* + * This file contains all assembly code for the i960 port of RTEMS. * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). @@ -13,12 +11,6 @@ * $Id$ */ .data - .align 4 -_soft_reset_reg_save: - .word 0 - .word 0 - .word 0 - .word 0 _ISR_reg_save: .word 0 .word 0 @@ -217,30 +209,3 @@ __ISR_Dispatch: movq r12,g4 ret - -#if !defined(__i960KA__) -/*PAGE - * - * void __i960_soft_reset_asm - * - * Flush the register cache and save the important (fp, pfp, sp) registers, - * which are clobbered by the reinit operation. (Not documented, but it happens). - */ - - .globl __i960_soft_reset_asm -__i960_soft_reset_asm: - flushreg # flush register cache - mov fp, r4 - mov pfp, r5 - mov sp, r6 - stt r4, _soft_reset_reg_save # save fp, pfp, sp - lda __i960_reset_done, r4 - ldconst 0x300, r5 - sysctl r5, r4, g0 # reinit: clobbers almost all registers -__i960_reset_done: - ldt _soft_reset_reg_save, r4 # restore fp, pfp, sp - mov r4, fp - mov r5, pfp - mov r6, sp - ret -#endif diff --git a/c/src/exec/score/cpu/i960/rtems/score/cpu.h b/c/src/exec/score/cpu/i960/rtems/score/cpu.h index dd9ced0704..71834e6dd2 100644 --- a/c/src/exec/score/cpu/i960/rtems/score/cpu.h +++ b/c/src/exec/score/cpu/i960/rtems/score/cpu.h @@ -165,8 +165,6 @@ typedef struct { void * (*stack_allocate_hook)( unsigned32 ); void (*stack_free_hook)( void* ); /* end of fields required on all CPUs */ - - i960_PRCB *Prcb; } rtems_cpu_table; /* @@ -176,11 +174,10 @@ typedef struct { /* * Macros to access i960 specific additions to the CPU Table + * + * NONE */ -#define rtems_cpu_configuration_get_prcb() \ - (_CPU_Table.Prcb) - /* variables */ SCORE_EXTERN void *_CPU_Interrupt_stack_low; diff --git a/c/src/exec/score/cpu/i960/rtems/score/i960.h b/c/src/exec/score/cpu/i960/rtems/score/i960.h index de7b635869..799d493279 100644 --- a/c/src/exec/score/cpu/i960/rtems/score/i960.h +++ b/c/src/exec/score/cpu/i960/rtems/score/i960.h @@ -33,314 +33,60 @@ extern "C" { * NOTE: RTEMS defines a canonical name for each cpu model. */ -#if defined(rtems_multilib) /* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. + * Define the name of the CPU family. */ -#define CPU_MODEL_NAME "rtems_multilib" -#define I960_HAS_FPU 0 -#define I960_CPU_ALIGNMENT 4 -#define I960_SOFT_RESET_COMMAND 0x30000 - -#elif defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) - -#define CPU_MODEL_NAME "i960ca" -#define __RTEMS_I960CA__ - -#elif defined(__i960KA__) -#define CPU_MODEL_NAME "i960ka" - -#elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA) - -#define CPU_MODEL_NAME "i960ha" -#define __RTEMS_I960HA__ - -#elif defined(__i960RP__) - -#include <i960RP.h> -#define CPU_MODEL_NAME "i960rp" -#define __RTEMS_I960RP__ -#define I960_CPU_ALIGNMENT 8 -#define I960_SOFT_RESET_COMMAND 0x300 - -#else - -#error "Unsupported CPU Model" - -#endif +#define CPU_NAME "Intel i960" /* - * Now default some CPU model variation parameters + * This should work since most i960 models do not have FPUs. The logic is: + * + * + If the user specifically asks for soft-float, give it to them + * regardless of hardware availability. + * + If the CPU has hardware FPU, then use it. + * + Otherwise, we have to use soft float. */ -#ifndef I960_HAS_FPU +#if defined(_SOFT_FLOAT) +#define I960_HAS_FPU 0 +#elif defined(_i960_KB__) || defined(_i960_SB__) || defined(_i960_SB__) || \ + defined(_i960_JF__) || defined(_i960_MC__) || defined(_i960_CC__) +#define I960_HAS_FPU 1 +#else #define I960_HAS_FPU 0 -#endif - -#ifndef I960_CPU_ALIGNMENT -#define I960_CPU_ALIGNMENT 4 -#endif - -#ifndef I960_SOFT_RESET_COMMAND -#define I960_SOFT_RESET_COMMAND 0x30000 #endif /* - * Define the name of the CPU family. + * Some of the CPU models may have better performance with + * alignment of 8 or 16 but we don't know what model we are + * being compiled for based solely on the information provided + * when multilibbing. */ -#define CPU_NAME "Intel i960" - -#ifndef ASM +#define I960_CPU_ALIGNMENT 4 /* - * XXX should have an ifdef here and have stuff for the other - * XXX family members... - */ - -#if defined(__RTEMS_I960CA__) -/* - * Now default some CPU model variation parameters + * This is not the perfect CPU model name but it is adequate and + * reflects what we know from multilib. */ -#ifndef I960_HAS_FPU -#define I960_HAS_FPU 0 -#endif - -#ifndef I960_CPU_ALIGNMENT -#define I960_CPU_ALIGNMENT 4 -#endif - - -/* i960CA control structures */ - -/* Intel i960CA Control Table */ - -typedef struct { - /* Control Group 0 */ - unsigned int ipb0; /* IP breakpoint 0 */ - unsigned int ipb1; /* IP breakpoint 1 */ - unsigned int dab0; /* data address breakpoint 0 */ - unsigned int dab1; /* data address breakpoint 1 */ - /* Control Group 1 */ - unsigned int imap0; /* interrupt map 0 */ - unsigned int imap1; /* interrupt map 1 */ - unsigned int imap2; /* interrupt map 2 */ - unsigned int icon; /* interrupt control */ - /* Control Group 2 */ - unsigned int mcon0; /* memory region 0 configuration */ - unsigned int mcon1; /* memory region 1 configuration */ - unsigned int mcon2; /* memory region 2 configuration */ - unsigned int mcon3; /* memory region 3 configuration */ - /* Control Group 3 */ - unsigned int mcon4; /* memory region 4 configuration */ - unsigned int mcon5; /* memory region 5 configuration */ - unsigned int mcon6; /* memory region 6 configuration */ - unsigned int mcon7; /* memory region 7 configuration */ - /* Control Group 4 */ - unsigned int mcon8; /* memory region 8 configuration */ - unsigned int mcon9; /* memory region 9 configuration */ - unsigned int mcon10; /* memory region 10 configuration */ - unsigned int mcon11; /* memory region 11 configuration */ - /* Control Group 5 */ - unsigned int mcon12; /* memory region 12 configuration */ - unsigned int mcon13; /* memory region 13 configuration */ - unsigned int mcon14; /* memory region 14 configuration */ - unsigned int mcon15; /* memory region 15 configuration */ - /* Control Group 6 */ - unsigned int reserved; /* reserved */ - unsigned int bpcon; /* breakpoint control */ - unsigned int tc; /* trace control */ - unsigned int bcon; /* bus configuration control */ -} i960ca_control_table; - -/* Intel i960CA Processor Control Block */ - -typedef struct { - unsigned int *fault_tbl; /* fault table base address */ - i960ca_control_table - *control_tbl; /* control table base address */ - unsigned int initial_ac; /* AC register initial value */ - unsigned int fault_config; /* fault configuration word */ - void **intr_tbl; /* interrupt table base address */ - void *sys_proc_tbl; /* system procedure table - base address */ - unsigned int reserved; /* reserved */ - unsigned int *intr_stack; /* interrupt stack pointer */ - unsigned int ins_cache_cfg; /* instruction cache - configuration word */ - unsigned int reg_cache_cfg; /* register cache configuration word */ -} i960ca_PRCB; - -typedef i960ca_control_table i960_control_table; -typedef i960ca_PRCB i960_PRCB; - -#elif defined(__RTEMS_I960HA__) - -/* i960HA control structures */ - -/* Intel i960HA Control Table */ - -typedef struct { - /* Control Group 0 */ - unsigned int ipb0; /* IP breakpoint 0 */ - unsigned int ipb1; /* IP breakpoint 1 */ - unsigned int dab0; /* data address breakpoint 0 */ - unsigned int dab1; /* data address breakpoint 1 */ - /* Control Group 1 */ - unsigned int imap0; /* interrupt map 0 */ - unsigned int imap1; /* interrupt map 1 */ - unsigned int imap2; /* interrupt map 2 */ - unsigned int icon; /* interrupt control */ - /* Control Group 2 */ - unsigned int mcon0; /* memory region 0 configuration */ - unsigned int mcon1; /* memory region 1 configuration */ - unsigned int mcon2; /* memory region 2 configuration */ - unsigned int mcon3; /* memory region 3 configuration */ - /* Control Group 3 */ - unsigned int mcon4; /* memory region 4 configuration */ - unsigned int mcon5; /* memory region 5 configuration */ - unsigned int mcon6; /* memory region 6 configuration */ - unsigned int mcon7; /* memory region 7 configuration */ - /* Control Group 4 */ - unsigned int mcon8; /* memory region 8 configuration */ - unsigned int mcon9; /* memory region 9 configuration */ - unsigned int mcon10; /* memory region 10 configuration */ - unsigned int mcon11; /* memory region 11 configuration */ - /* Control Group 5 */ - unsigned int mcon12; /* memory region 12 configuration */ - unsigned int mcon13; /* memory region 13 configuration */ - unsigned int mcon14; /* memory region 14 configuration */ - unsigned int mcon15; /* memory region 15 configuration */ - /* Control Group 6 */ - unsigned int reserved; /* reserved */ - unsigned int bpcon; /* breakpoint control */ - unsigned int tc; /* trace control */ - unsigned int bcon; /* bus configuration control */ -} i960ha_control_table; - -/* Intel i960HA Processor Control Block */ - -typedef struct { - unsigned int *fault_tbl; /* fault table base address */ - i960ha_control_table - *control_tbl; /* control table base address */ - unsigned int initial_ac; /* AC register initial value */ - unsigned int fault_config; /* fault configuration word */ - void **intr_tbl; /* interrupt table base address */ - void *sys_proc_tbl; /* system procedure table - base address */ - unsigned int reserved; /* reserved */ - unsigned int *intr_stack; /* interrupt stack pointer */ - unsigned int ins_cache_cfg; /* instruction cache - configuration word */ - unsigned int reg_cache_cfg; /* register cache configuration word */ -} i960ha_PRCB; - -typedef i960ha_control_table i960_control_table; -typedef i960ha_PRCB i960_PRCB; - -#elif defined(__RTEMS_I960RP__) - -/* i960RP control structures */ - -/* Intel i960RP Control Table */ - -typedef struct { - /* Control Group 0 */ - unsigned int rsvd00; - unsigned int rsvd01; - unsigned int rsvd02; - unsigned int rsvd03; - /* Control Group 1 */ - unsigned int imap0; /* interrupt map 0 */ - unsigned int imap1; /* interrupt map 1 */ - unsigned int imap2; /* interrupt map 2 */ - unsigned int icon; /* interrupt control */ - /* Control Group 2 */ - unsigned int pmcon0; /* memory region 0 configuration */ - unsigned int rsvd1; - unsigned int pmcon2; /* memory region 2 configuration */ - unsigned int rsvd2; - /* Control Group 3 */ - unsigned int pmcon4; /* memory region 4 configuration */ - unsigned int rsvd3; - unsigned int pmcon6; /* memory region 6 configuration */ - unsigned int rsvd4; - /* Control Group 4 */ - unsigned int pmcon8; /* memory region 8 configuration */ - unsigned int rsvd5; - unsigned int pmcon10; /* memory region 10 configuration */ - unsigned int rsvd6; - /* Control Group 5 */ - unsigned int pmcon12; /* memory region 12 configuration */ - unsigned int rsvd7; - unsigned int pmcon14; /* memory region 14 configuration */ - unsigned int rsvd8; - /* Control Group 6 */ - unsigned int rsvd9; - unsigned int rsvd10; - unsigned int tc; /* trace control */ - unsigned int bcon; /* bus configuration control */ -} i960rp_control_table; - -/* Intel i960RP Processor Control Block */ - -typedef struct { - unsigned int *fault_tbl; /* fault table base address */ - i960rp_control_table - *control_tbl; /* control table base address */ - unsigned int initial_ac; /* AC register initial value */ - unsigned int fault_config; /* fault configuration word */ - void **intr_tbl; /* interrupt table base address */ - void *sys_proc_tbl; /* system procedure table - base address */ - unsigned int reserved; /* reserved */ - unsigned int *intr_stack; /* interrupt stack pointer */ - unsigned int ins_cache_cfg; /* instruction cache - configuration word */ - unsigned int reg_cache_cfg; /* register cache configuration word */ -} i960rp_PRCB; - -typedef i960rp_control_table i960_control_table; -typedef i960rp_PRCB i960_PRCB; - -#elif defined(__i960KA__) - -/* i960KA control structures */ - -/* Intel i960KA Control Table */ - -typedef struct { -int pad0; -} i960ka_control_table; - -/* Intel i960KA Processor Control Block */ - -typedef struct { - void **intr_tbl; /* interrupt table base address */ - unsigned int *intr_stack; /* interrupt stack pointer */ -} i960ka_PRCB; - -typedef i960ka_control_table i960_control_table; -typedef i960ka_PRCB i960_PRCB; - +#if I960_HAS_FPU +#define CPU_MODEL_NAME "i960 w/FPU" #else -#error "invalid processor selection!" +#define CPU_MODEL_NAME "i960 w/soft-float" #endif +#ifndef ASM + /* * Miscellaneous Support Routines */ -#if !defined(__i960KA__) #define i960_reload_ctl_group( group ) \ { register int _cmd = ((group)|0x400) ; \ asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \ } -#endif #define i960_atomic_modify( mask, addr, prev ) \ { register unsigned int _mask = (mask); \ @@ -393,97 +139,15 @@ typedef i960ka_PRCB i960_PRCB; (_level) = ((_level) & 0x1f0000) >> 16; \ } while ( 0 ) -#if !defined(__i960KA__) #define i960_cause_intr( intr ) \ { register int _intr = (intr); \ asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \ } -#endif /* * Interrupt Masking Routines */ -#if defined(__RTEMS_I960CA__) || defined(__RTEMS_I960HA__) - -#define i960_unmask_intr( xint ) \ - { register unsigned int _mask= (1<<(xint)); \ - asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \ - } - -#define i960_mask_intr( xint ) \ - { register unsigned int _mask= (1<<(xint)); \ - asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \ - } - -#define i960_clear_intr( xint ) \ - { register unsigned int _xint=(xint); \ -asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \ - bbs %0,sf0, loop_til_cleared" \ - : "=d" (_xint) : "0" (_xint) ); \ - } - -static inline unsigned int i960_pend_intrs() -{ register unsigned int _intr=0; - asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) ); - return ( _intr ); -} - -static inline unsigned int i960_mask_intrs() -{ register unsigned int _intr=0; - asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) ); - return( _intr ); -} - -#elif defined(__RTEMS_I960RP__) - -#define i960_unmask_intr( xint ) \ - { register unsigned int _mask= (1<<(xint)); \ - register unsigned int *_imsk = (int * ) IMSK_ADDR; \ - register unsigned int _val= *_imsk; \ - asm volatile( "or %0,%2,%0; \ - st %0,(%1)" \ - : "=d" (_val), "=d" (_imsk), "=d" (_mask) \ - : "0" (_val), "1" (_imsk), "2" (_mask) ); \ - } - -#define i960_mask_intr( xint ) \ - { register unsigned int _mask= (1<<(xint)); \ - register unsigned int *_imsk = (int * ) IMSK_ADDR; \ - register unsigned int _val = *_imsk; \ - asm volatile( "andnot %2,%0,%0; \ - st %0,(%1)" \ - : "=d" (_val), "=d" (_imsk), "=d" (_mask) \ - : "0" (_val), "1" (_imsk), "2" (_mask) ); \ - } -#define i960_clear_intr( xint ) \ - { register unsigned int _xint=xint; \ - register unsigned int _mask=(1<<(xint)); \ - register unsigned int *_ipnd = (int * ) IPND_ADDR; \ - register unsigned int _rslt = 0; \ -asm volatile( "loop_til_cleared: mov 0, %0; \ - atmod %1, %2, %0; \ - bbs %3,%0, loop_til_cleared" \ - : "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \ - : "0" (_rslt), "1" (_ipnd), "2" (_mask), "3" (_xint) ); \ - } - -static inline unsigned int i960_pend_intrs() -{ register unsigned int _intr= *(unsigned int *) IPND_ADDR; - /*register unsigned int *_ipnd = (int * ) IPND_ADDR; \ - asm volatile( "mov (%0),%1" \ - : "=d" (_ipnd), "=d" (_mask) \ - : "0" (_ipnd), "1" (_mask) ); \ */ - return ( _intr ); -} - -static inline unsigned int i960_mask_intrs() -{ register unsigned int _intr= *(unsigned int *) IMSK_ADDR; - /*asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );*/ - return( _intr ); -} -#endif - static inline unsigned int i960_get_fp() { register unsigned int _fp=0; asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) ); @@ -491,26 +155,6 @@ static inline unsigned int i960_get_fp() } /* - * Soft Reset - */ - -#if defined(I960_SOFT_RESET_COMMAND) -#define i960_soft_reset( prcb ) \ - { register i960_PRCB *_prcb = (prcb); \ - register unsigned int *_next=0; \ - register unsigned int _cmd = I960_SOFT_RESET_COMMAND; \ - asm volatile( "lda next,%1; \ - sysctl %0,%1,%2; \ - next: mov g0,g0" \ - : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ - : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ - } - -#elif !defined(__i960KA__) -#warning "I960_SOFT_RESET_COMMAND is not defined" -#endif - -/* * The following routine swaps the endian format of an unsigned int. * It must be static because it is referenced indirectly. * diff --git a/c/src/lib/libbsp/i960/cvme961/include/bsp.h b/c/src/lib/libbsp/i960/cvme961/include/bsp.h index e00d525e7b..1547b40aa6 100644 --- a/c/src/lib/libbsp/i960/cvme961/include/bsp.h +++ b/c/src/lib/libbsp/i960/cvme961/include/bsp.h @@ -22,6 +22,7 @@ extern "C" { #endif #include <rtems.h> +#include <libcpu/i960CA.h> #include <iosupp.h> #include <console.h> #include <clockdrv.h> diff --git a/c/src/lib/libbsp/i960/cvme961/startup/bspstart.c b/c/src/lib/libbsp/i960/cvme961/startup/bspstart.c index 7d89f1c09d..eab65eb1c0 100644 --- a/c/src/lib/libbsp/i960/cvme961/startup/bspstart.c +++ b/c/src/lib/libbsp/i960/cvme961/startup/bspstart.c @@ -108,7 +108,6 @@ void bsp_start( void ) Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ Cpu_table.postdriver_hook = bsp_postdriver_hook; Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY; - Cpu_table.Prcb = Prcb; BSP_Configuration.work_space_start = (void *) (RAM_END - BSP_Configuration.work_space_size); diff --git a/c/src/lib/libbsp/i960/cvme961/wrapup/Makefile.am b/c/src/lib/libbsp/i960/cvme961/wrapup/Makefile.am index 01c85b4bbc..6e8b8865bd 100644 --- a/c/src/lib/libbsp/i960/cvme961/wrapup/Makefile.am +++ b/c/src/lib/libbsp/i960/cvme961/wrapup/Makefile.am @@ -19,7 +19,8 @@ include $(top_srcdir)/../../../../../../automake/lib.am # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS = $(foreach piece, $(BSP_FILES), $(wildcard ../$(piece)/$(ARCH)/*.o)) \ - $(foreach piece, $(GENERIC_FILES), ../../../$(piece)/$(ARCH)/$(piece).rel) + $(wildcard ../../../../libcpu/$(RTEMS_CPU)/$(RTEMS_CPU_MODEL)/$(ARCH)/*.o) \ + $(foreach piece, $(GENERIC_FILES), ../../../$(piece)/$(ARCH)/$(piece).rel) LIB = $(ARCH)/libbsp.a diff --git a/c/src/lib/libbsp/i960/i960sim/include/bsp.h b/c/src/lib/libbsp/i960/i960sim/include/bsp.h index 691ed73a25..ac8ecb48bb 100644 --- a/c/src/lib/libbsp/i960/i960sim/include/bsp.h +++ b/c/src/lib/libbsp/i960/i960sim/include/bsp.h @@ -13,8 +13,8 @@ * $Id$ */ -#ifndef __CVME961_h -#define __CVME961_h +#ifndef __I960SIM_h +#define __I960SIM_h #ifdef __cplusplus extern "C" { diff --git a/c/src/lib/libbsp/i960/i960sim/startup/bspstart.c b/c/src/lib/libbsp/i960/i960sim/startup/bspstart.c index f93fb3c6b9..e5b840d472 100644 --- a/c/src/lib/libbsp/i960/i960sim/startup/bspstart.c +++ b/c/src/lib/libbsp/i960/i960sim/startup/bspstart.c @@ -77,6 +77,10 @@ void bsp_pretasking_hook(void) * This routine does the bulk of the system initialization. */ +#include <libcpu/i960KA.h> + +i960_PRCB *Prcb; /* to satisfy linking */ + void bsp_start( void ) { extern int _end; @@ -86,7 +90,6 @@ void bsp_start( void ) Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ Cpu_table.postdriver_hook = bsp_postdriver_hook; Cpu_table.interrupt_stack_size = 4096; - Cpu_table.Prcb = 0; /* Prcb; */ if ( BSP_Configuration.work_space_size >(512*1024) ) _sys_exit( 1 ); diff --git a/c/src/lib/libbsp/i960/i960sim/wrapup/Makefile.am b/c/src/lib/libbsp/i960/i960sim/wrapup/Makefile.am index d79cd51a66..ae52204fdb 100644 --- a/c/src/lib/libbsp/i960/i960sim/wrapup/Makefile.am +++ b/c/src/lib/libbsp/i960/i960sim/wrapup/Makefile.am @@ -11,7 +11,8 @@ include $(top_srcdir)/../../../../../../automake/lib.am # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS = $(foreach piece, $(BSP_FILES), $(wildcard ../$(piece)/$(ARCH)/*.o)) \ - $(foreach piece, $(GENERIC_FILES), ../../../$(piece)/$(ARCH)/$(piece).rel) + $(wildcard ../../../../libcpu/$(RTEMS_CPU)/$(RTEMS_CPU_MODEL)/$(ARCH)/*.o) \ + $(foreach piece, $(GENERIC_FILES), ../../../$(piece)/$(ARCH)/$(piece).rel) LIB = $(ARCH)/libbsp.a diff --git a/c/src/lib/libbsp/i960/rxgen960/clock/ckinit.c b/c/src/lib/libbsp/i960/rxgen960/clock/ckinit.c index 20b7ea3144..cc42884639 100644 --- a/c/src/lib/libbsp/i960/rxgen960/clock/ckinit.c +++ b/c/src/lib/libbsp/i960/rxgen960/clock/ckinit.c @@ -22,7 +22,6 @@ #include <stdlib.h> #include <bsp.h> -#include <i960RP.h> #include <rtems/libio.h> #define CLOCK_VECTOR 0x92 diff --git a/c/src/lib/libbsp/i960/rxgen960/include/bsp.h b/c/src/lib/libbsp/i960/rxgen960/include/bsp.h index 4256629165..52343f6bbe 100644 --- a/c/src/lib/libbsp/i960/rxgen960/include/bsp.h +++ b/c/src/lib/libbsp/i960/rxgen960/include/bsp.h @@ -22,6 +22,7 @@ extern "C" { #endif #include <rtems.h> +#include <libcpu/i960RP.h> #include <iosupp.h> #include <console.h> #include <clockdrv.h> diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/bspstart.c b/c/src/lib/libbsp/i960/rxgen960/startup/bspstart.c index bc4ddfcff8..bfed470ce3 100644 --- a/c/src/lib/libbsp/i960/rxgen960/startup/bspstart.c +++ b/c/src/lib/libbsp/i960/rxgen960/startup/bspstart.c @@ -28,13 +28,8 @@ #include <string.h> #include <fcntl.h> #include <stdio.h> -#include "i960RP.h" #include <rtems/libio.h> -#ifdef STACK_CHECKER_ON -#include <stackchk.h> -#endif - #define HEAP_SIZE 1024*1024*2 /* @@ -84,16 +79,6 @@ bsp_pretasking_hook(void) bsp_libc_init((void *) heap_start, 64 * 1024, 0); -#ifdef STACK_CHECKER_ON - /* - * Initialize the stack bounds checker - * We can either turn it on here or from the app. - */ - -*(unsigned char *)(0x120f) = 0xe; - Stack_check_Initialize(); -#endif - #ifdef RTEMS_DEBUG rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); #endif @@ -134,7 +119,6 @@ bsp_start(void) Cpu_table.do_zero_of_workspace = TRUE; Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY; Cpu_table.extra_mpci_receive_server_stack = 0; - Cpu_table.Prcb = Prcb; /* just trying to get along */ Cpu_table.stack_allocate_hook = 0; diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.c b/c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.c index 07835ede2a..252a11d7eb 100644 --- a/c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.c +++ b/c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.c @@ -6,7 +6,7 @@ * $Id$ */ -#include "i960RP.h" +#include <bsp.h> #include "cntrltbl.h" /*-------------------------------------*/ /* Control Table. diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/rom_cntrltbl.c b/c/src/lib/libbsp/i960/rxgen960/startup/rom_cntrltbl.c index 6f3d97d6b0..fcaf48e06f 100644 --- a/c/src/lib/libbsp/i960/rxgen960/startup/rom_cntrltbl.c +++ b/c/src/lib/libbsp/i960/rxgen960/startup/rom_cntrltbl.c @@ -6,7 +6,7 @@ * $Id$ */ -#include <i960RP.h> +#include <bsp.h> #include "cntrltbl.h" /*-------------------------------------*/ /* Control Table. diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/rom_ibr.c b/c/src/lib/libbsp/i960/rxgen960/startup/rom_ibr.c index 83e456c7aa..d65d0109cd 100644 --- a/c/src/lib/libbsp/i960/rxgen960/startup/rom_ibr.c +++ b/c/src/lib/libbsp/i960/rxgen960/startup/rom_ibr.c @@ -9,7 +9,7 @@ #include "rom_ibr.h" #include "prcb.h" #include "cntrltbl.h" -#include <i960RP.h> +#include <bsp.h> #include "../include/rxgen960_config.h" /*-------------------------------------*/ extern void romStart(void); diff --git a/c/src/lib/libbsp/i960/rxgen960/timer/timer.c b/c/src/lib/libbsp/i960/rxgen960/timer/timer.c index 8b166090e2..eabb33d81a 100644 --- a/c/src/lib/libbsp/i960/rxgen960/timer/timer.c +++ b/c/src/lib/libbsp/i960/rxgen960/timer/timer.c @@ -27,10 +27,8 @@ */ -#include <rtems.h> #include <bsp.h> #include <stdlib.h> -#include <i960RP.h> #include <rtems/libio.h> diff --git a/c/src/lib/libbsp/i960/rxgen960/wrapup/Makefile.am b/c/src/lib/libbsp/i960/rxgen960/wrapup/Makefile.am index e3dd06fc1e..3cf65c86c2 100644 --- a/c/src/lib/libbsp/i960/rxgen960/wrapup/Makefile.am +++ b/c/src/lib/libbsp/i960/rxgen960/wrapup/Makefile.am @@ -19,7 +19,8 @@ BSP_PIECES = startup clock console timer $(BSP_MP_O_PIECES) # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS = $(foreach piece, $(BSP_PIECES), $(wildcard ../$(piece)/$(ARCH)/*.o)) \ - $(foreach piece, $(GENERIC_PIECES), ../../../$(piece)/$(ARCH)/$(piece).rel) + $(wildcard ../../../../libcpu/$(RTEMS_CPU)/$(RTEMS_CPU_MODEL)/$(ARCH)/*.o) \ + $(foreach piece, $(GENERIC_PIECES), ../../../$(piece)/$(ARCH)/$(piece).rel) LIB = $(ARCH)/libbsp.a # diff --git a/c/src/lib/libcpu/i960/Makefile.am b/c/src/lib/libcpu/i960/Makefile.am new file mode 100644 index 0000000000..1d871d2140 --- /dev/null +++ b/c/src/lib/libcpu/i960/Makefile.am @@ -0,0 +1,12 @@ +## +## $Id$ +## + +AUTOMAKE_OPTIONS = foreign 1.4 +ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal + +SUBDIRS = include @RTEMS_CPU_MODEL@ + +include $(top_srcdir)/../../../../../automake/subdirs.am +include $(top_srcdir)/../../../../../automake/local.am + diff --git a/c/src/lib/libcpu/i960/configure.in b/c/src/lib/libcpu/i960/configure.in new file mode 100644 index 0000000000..ac4e38eb20 --- /dev/null +++ b/c/src/lib/libcpu/i960/configure.in @@ -0,0 +1,40 @@ +dnl Process this file with autoconf to produce a configure script. +dnl +dnl $Id$ + +AC_PREREQ(2.13) +AC_INIT(i960ca) +RTEMS_TOP(../../../../..) +AC_CONFIG_AUX_DIR(../../../../..) + +RTEMS_CANONICAL_TARGET_CPU + +AM_INIT_AUTOMAKE(rtems-c-src-lib-libcpu-i960,$RTEMS_VERSION,no) +AM_MAINTAINER_MODE + +RTEMS_ENABLE_BARE +RTEMS_ENV_RTEMSBSP + +RTEMS_CHECK_CPU +RTEMS_CANONICAL_HOST + +RTEMS_PROJECT_ROOT + +RTEMS_PROG_CC_FOR_TARGET +RTEMS_CANONICALIZE_TOOLS + +RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP) +RTEMS_CHECK_BSP_CACHE(RTEMS_BSP) + +AM_CONDITIONAL(i960ca, test "$RTEMS_CPU_MODEL" = "i960ca") +AM_CONDITIONAL(i960ka, test "$RTEMS_CPU_MODEL" = "i960ka") +AM_CONDITIONAL(i960rp, test "$RTEMS_CPU_MODEL" = "i960rp") + +# Explicitly list all Makefiles here +AC_OUTPUT( +Makefile +i960ca/Makefile +i960ka/Makefile +i960rp/Makefile +include/Makefile) + diff --git a/c/src/lib/libcpu/i960/i960ca/Makefile.am b/c/src/lib/libcpu/i960/i960ca/Makefile.am new file mode 100644 index 0000000000..c37a3a0433 --- /dev/null +++ b/c/src/lib/libcpu/i960/i960ca/Makefile.am @@ -0,0 +1,27 @@ +## +## $Id$ +## + +AUTOMAKE_OPTIONS = foreign 1.4 + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(top_srcdir)/../../../../../automake/lib.am + +C_FILES = cpu_install_intr_stack.c cpu_install_raw_isr.c +C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) + +H_FILES = + +OBJS = $(C_O_FILES) + +# +# (OPTIONAL) Add local stuff here using += +# + +if i960ca +all-local: $(ARCH) $(OBJS) +endif + +EXTRA_DIST = cpu_install_intr_stack.c cpu_install_raw_isr.c + +include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/i960/i960ca/cpu_install_intr_stack.c b/c/src/lib/libcpu/i960/i960ca/cpu_install_intr_stack.c new file mode 100644 index 0000000000..bb0e491b49 --- /dev/null +++ b/c/src/lib/libcpu/i960/i960ca/cpu_install_intr_stack.c @@ -0,0 +1,30 @@ +/* + * Install interrupt stack i960ca + * + * $Id$ + */ + +#include <rtems.h> +#include <libcpu/i960CA.h> + +extern i960_PRCB *Prcb; + +void _CPU_Install_interrupt_stack( void ) +{ + i960_PRCB *prcb = Prcb; + unsigned32 level; + + /* + * Set the Interrupt Stack in the PRCB and force a reload of it. + * Interrupts are disabled for safety. + */ + + _CPU_ISR_Disable( level ); + + prcb->intr_stack = _CPU_Interrupt_stack_low; + + i960_soft_reset( prcb ); + + _CPU_ISR_Enable( level ); +} + diff --git a/c/src/lib/libcpu/i960/i960ca/cpu_install_raw_isr.c b/c/src/lib/libcpu/i960/i960ca/cpu_install_raw_isr.c new file mode 100644 index 0000000000..6e5f13952b --- /dev/null +++ b/c/src/lib/libcpu/i960/i960ca/cpu_install_raw_isr.c @@ -0,0 +1,38 @@ +/* + * Install raw interrupt vector for i960ca + * + * $Id$ + */ + +#include <rtems.h> +#include <libcpu/i960CA.h> + +#define i960_vector_caching_enabled( _prcb ) \ + ((_prcb)->control_tbl->icon & 0x2000) + +extern i960_PRCB *Prcb; + +void _CPU_ISR_install_raw_handler( + unsigned32 vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + i960_PRCB *prcb = Prcb; + proc_ptr *cached_intr_tbl = NULL; + + /* The i80960CA does not support vectors 0-7. The first 9 entries + * in the Interrupt Table are used to manage pending interrupts. + * Thus vector 8, the first valid vector number, is actually in + * slot 9 in the table. + */ + + *old_handler = prcb->intr_tbl[ vector + 1 ]; + + prcb->intr_tbl[ vector + 1 ] = new_handler; + + if ( i960_vector_caching_enabled( prcb ) ) + if ( (vector & 0xf) == 0x2 ) /* cacheable? */ + cached_intr_tbl[ vector >> 4 ] = new_handler; +} + diff --git a/c/src/lib/libcpu/i960/i960ka/Makefile.am b/c/src/lib/libcpu/i960/i960ka/Makefile.am new file mode 100644 index 0000000000..3c276d0b1c --- /dev/null +++ b/c/src/lib/libcpu/i960/i960ka/Makefile.am @@ -0,0 +1,27 @@ +## +## $Id$ +## + +AUTOMAKE_OPTIONS = foreign 1.4 + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(top_srcdir)/../../../../../automake/lib.am + +C_FILES = cpu_install_intr_stack.c cpu_install_raw_isr.c +C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) + +H_FILES = + +OBJS = $(C_O_FILES) + +# +# (OPTIONAL) Add local stuff here using += +# + +if i960ka +all-local: $(ARCH) $(OBJS) +endif + +EXTRA_DIST = cpu_install_intr_stack.c cpu_install_raw_isr.c + +include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/i960/i960ka/cpu_install_intr_stack.c b/c/src/lib/libcpu/i960/i960ka/cpu_install_intr_stack.c new file mode 100644 index 0000000000..5fe1d47332 --- /dev/null +++ b/c/src/lib/libcpu/i960/i960ka/cpu_install_intr_stack.c @@ -0,0 +1,30 @@ +/* + * Install interrupt stack i960ka + * + * $Id$ + */ + +#include <rtems.h> +#include <libcpu/i960KA.h> + +extern i960_PRCB *Prcb; + +void _CPU_Install_interrupt_stack( void ) +{ + i960_PRCB *prcb = Prcb; + unsigned32 level; + + /* + * Set the Interrupt Stack in the PRCB and force a reload of it. + * Interrupts are disabled for safety. + */ + + _CPU_ISR_Disable( level ); + + prcb->intr_stack = _CPU_Interrupt_stack_low; + + /* soft_reset( prcb ); XXX is there an action like this on the KA? */ + + _CPU_ISR_Enable( level ); +} + diff --git a/c/src/lib/libcpu/i960/i960ka/cpu_install_raw_isr.c b/c/src/lib/libcpu/i960/i960ka/cpu_install_raw_isr.c new file mode 100644 index 0000000000..a204046a72 --- /dev/null +++ b/c/src/lib/libcpu/i960/i960ka/cpu_install_raw_isr.c @@ -0,0 +1,39 @@ +/* + * Install raw interrupt vector for i960ka + * + * $Id$ + */ + +#include <rtems.h> +#include <libcpu/i960KA.h> + +/* this is from the CA and probably not right */ +#define i960_vector_caching_enabled( _prcb ) \ + ((_prcb)->control_tbl->icon & 0x2000) + +extern i960_PRCB *Prcb; + +void _CPU_ISR_install_raw_handler( + unsigned32 vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + i960_PRCB *prcb = Prcb; + proc_ptr *cached_intr_tbl = NULL; + + /* The i80960CA does not support vectors 0-7. The first 9 entries + * in the Interrupt Table are used to manage pending interrupts. + * Thus vector 8, the first valid vector number, is actually in + * slot 9 in the table. + */ + + *old_handler = prcb->intr_tbl[ vector + 1 ]; + + prcb->intr_tbl[ vector + 1 ] = new_handler; + + if ( i960_vector_caching_enabled( prcb ) ) + if ( (vector & 0xf) == 0x2 ) /* cacheable? */ + cached_intr_tbl[ vector >> 4 ] = new_handler; +} + diff --git a/c/src/lib/libcpu/i960/i960rp/Makefile.am b/c/src/lib/libcpu/i960/i960rp/Makefile.am new file mode 100644 index 0000000000..459716912c --- /dev/null +++ b/c/src/lib/libcpu/i960/i960rp/Makefile.am @@ -0,0 +1,27 @@ +## +## $Id$ +## + +AUTOMAKE_OPTIONS = foreign 1.4 + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(top_srcdir)/../../../../../automake/lib.am + +C_FILES = cpu_install_intr_stack.c cpu_install_raw_isr.c +C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) + +H_FILES = + +OBJS = $(C_O_FILES) + +# +# (OPTIONAL) Add local stuff here using += +# + +if i960rp +all-local: $(ARCH) $(OBJS) +endif + +EXTRA_DIST = cpu_install_intr_stack.c cpu_install_raw_isr.c + +include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/i960/i960rp/cpu_install_intr_stack.c b/c/src/lib/libcpu/i960/i960rp/cpu_install_intr_stack.c new file mode 100644 index 0000000000..9e1deca598 --- /dev/null +++ b/c/src/lib/libcpu/i960/i960rp/cpu_install_intr_stack.c @@ -0,0 +1,31 @@ +/* + * Install interrupt stack i960RP + * + * $Id$ + */ + +#include <rtems.h> +#include <libcpu/i960RP.h> + +extern i960_PRCB *Prcb; + +void _CPU_Install_interrupt_stack( void ) +{ + i960_PRCB *prcb = Prcb; + unsigned32 level; + unsigned32 *isp = (int *) ISP_ADDR; + + /* + * Set the Interrupt Stack in the on-CPU memory. + * Interrupts are disabled for safety. + */ + + _CPU_ISR_Disable( level ); + + prcb->intr_stack = _CPU_Interrupt_stack_low; + + *isp = (unsigned32) prcb->intr_stack; + + _CPU_ISR_Enable( level ); +} + diff --git a/c/src/lib/libcpu/i960/i960rp/cpu_install_raw_isr.c b/c/src/lib/libcpu/i960/i960rp/cpu_install_raw_isr.c new file mode 100644 index 0000000000..9ee56993a5 --- /dev/null +++ b/c/src/lib/libcpu/i960/i960rp/cpu_install_raw_isr.c @@ -0,0 +1,37 @@ +/* + * Install raw interrupt vector for i960RP + * + * $Id$ + */ + +#include <rtems.h> +#include <libcpu/i960RP.h> + +#define i960_vector_caching_enabled( _prcb ) \ + ((*((unsigned int *) ICON_ADDR)) & 0x2000) + +extern i960_PRCB *Prcb; + +void _CPU_ISR_install_raw_handler( + unsigned32 vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + i960_PRCB *prcb = &Prcb; + proc_ptr *cached_intr_tbl = NULL; + + /* The i80960RP does not support vectors 0-7. The first 9 entries + * in the Interrupt Table are used to manage pending interrupts. + * Thus vector 8, the first valid vector number, is actually in + * slot 9 in the table. + */ + + *old_handler = prcb->intr_tbl[ vector + 1 ]; + + prcb->intr_tbl[ vector + 1 ] = new_handler; + + if ( i960_vector_caching_enabled( prcb ) ) + if ( (vector & 0xf) == 0x2 ) /* cacheable? */ + cached_intr_tbl[ vector >> 4 ] = new_handler; +} diff --git a/c/src/lib/libcpu/i960/include/Makefile.am b/c/src/lib/libcpu/i960/include/Makefile.am new file mode 100644 index 0000000000..c4e2305cf0 --- /dev/null +++ b/c/src/lib/libcpu/i960/include/Makefile.am @@ -0,0 +1,25 @@ +## +## $Id$ +## + +AUTOMAKE_OPTIONS = foreign 1.4 + +H_FILES = i960CA.h i960HA.h i960KA.h i960RP.h i960JX_RP_common.h + +# NOTE: Unlike other CPUS, we install into a subdirectory to avoid +# file name conflicts + +$(PROJECT_INCLUDE)/libcpu: + $(mkinstalldirs) $@ + +$(PROJECT_INCLUDE)/libcpu/%.h: %.h + $(INSTALL_DATA) $< $@ + +TMPINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu \ + $(H_FILES:%=$(PROJECT_INCLUDE)/libcpu/%) + +all-local: $(TMPINSTALL_FILES) + +EXTRA_DIST = i960CA.h i960HA.h i960KA.h i960RP.h i960JX_RP_common.h + +include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/i960/include/i960CA.h b/c/src/lib/libcpu/i960/include/i960CA.h new file mode 100644 index 0000000000..b3f8971056 --- /dev/null +++ b/c/src/lib/libcpu/i960/include/i960CA.h @@ -0,0 +1,119 @@ +/* + * i960ca + * + * $Id$ + */ + +#ifndef __i960CA_h +#define __i960CA_h + + +/* i960CA control structures */ + +/* Intel i960CA Control Table */ + +typedef struct { + /* Control Group 0 */ + unsigned int ipb0; /* IP breakpoint 0 */ + unsigned int ipb1; /* IP breakpoint 1 */ + unsigned int dab0; /* data address breakpoint 0 */ + unsigned int dab1; /* data address breakpoint 1 */ + /* Control Group 1 */ + unsigned int imap0; /* interrupt map 0 */ + unsigned int imap1; /* interrupt map 1 */ + unsigned int imap2; /* interrupt map 2 */ + unsigned int icon; /* interrupt control */ + /* Control Group 2 */ + unsigned int mcon0; /* memory region 0 configuration */ + unsigned int mcon1; /* memory region 1 configuration */ + unsigned int mcon2; /* memory region 2 configuration */ + unsigned int mcon3; /* memory region 3 configuration */ + /* Control Group 3 */ + unsigned int mcon4; /* memory region 4 configuration */ + unsigned int mcon5; /* memory region 5 configuration */ + unsigned int mcon6; /* memory region 6 configuration */ + unsigned int mcon7; /* memory region 7 configuration */ + /* Control Group 4 */ + unsigned int mcon8; /* memory region 8 configuration */ + unsigned int mcon9; /* memory region 9 configuration */ + unsigned int mcon10; /* memory region 10 configuration */ + unsigned int mcon11; /* memory region 11 configuration */ + /* Control Group 5 */ + unsigned int mcon12; /* memory region 12 configuration */ + unsigned int mcon13; /* memory region 13 configuration */ + unsigned int mcon14; /* memory region 14 configuration */ + unsigned int mcon15; /* memory region 15 configuration */ + /* Control Group 6 */ + unsigned int reserved; /* reserved */ + unsigned int bpcon; /* breakpoint control */ + unsigned int tc; /* trace control */ + unsigned int bcon; /* bus configuration control */ +} i960ca_control_table; + +/* Intel i960CA Processor Control Block */ + +typedef struct { + unsigned int *fault_tbl; /* fault table base address */ + i960ca_control_table + *control_tbl; /* control table base address */ + unsigned int initial_ac; /* AC register initial value */ + unsigned int fault_config; /* fault configuration word */ + void **intr_tbl; /* interrupt table base address */ + void *sys_proc_tbl; /* system procedure table + base address */ + unsigned int reserved; /* reserved */ + unsigned int *intr_stack; /* interrupt stack pointer */ + unsigned int ins_cache_cfg; /* instruction cache + configuration word */ + unsigned int reg_cache_cfg; /* register cache configuration word */ +} i960ca_PRCB; + +typedef i960ca_control_table i960_control_table; +typedef i960ca_PRCB i960_PRCB; + +#define i960_unmask_intr( xint ) \ + { register unsigned int _mask= (1<<(xint)); \ + asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \ + } + +#define i960_mask_intr( xint ) \ + { register unsigned int _mask= (1<<(xint)); \ + asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \ + } + +#define i960_clear_intr( xint ) \ + { register unsigned int _xint=(xint); \ +asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \ + bbs %0,sf0, loop_til_cleared" \ + : "=d" (_xint) : "0" (_xint) ); \ + } + +static inline unsigned int i960_pend_intrs() +{ register unsigned int _intr=0; + asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) ); + return ( _intr ); +} + +static inline unsigned int i960_mask_intrs() +{ register unsigned int _intr=0; + asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) ); + return( _intr ); +} + +#define I960_SOFT_RESET_COMMAND 0x30000 + +#define i960_soft_reset( prcb ) \ + { register i960_PRCB *_prcb = (prcb); \ + register unsigned int *_next=0; \ + register unsigned int _cmd = I960_SOFT_RESET_COMMAND; \ + asm volatile( "lda next,%1; \ + sysctl %0,%1,%2; \ + next: mov g0,g0" \ + : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ + : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ + } + + + +#endif +/* end of include file */ diff --git a/c/src/lib/libcpu/i960/include/i960HA.h b/c/src/lib/libcpu/i960/include/i960HA.h new file mode 100644 index 0000000000..0afd911e75 --- /dev/null +++ b/c/src/lib/libcpu/i960/include/i960HA.h @@ -0,0 +1,91 @@ +/* + * i960ha + * + * $Id$ + */ + +#ifndef __i960HA_h +#define __i960HA_h + + + +/* i960HA control structures */ + +/* Intel i960HA Control Table */ + +typedef struct { + /* Control Group 0 */ + unsigned int ipb0; /* IP breakpoint 0 */ + unsigned int ipb1; /* IP breakpoint 1 */ + unsigned int dab0; /* data address breakpoint 0 */ + unsigned int dab1; /* data address breakpoint 1 */ + /* Control Group 1 */ + unsigned int imap0; /* interrupt map 0 */ + unsigned int imap1; /* interrupt map 1 */ + unsigned int imap2; /* interrupt map 2 */ + unsigned int icon; /* interrupt control */ + /* Control Group 2 */ + unsigned int mcon0; /* memory region 0 configuration */ + unsigned int mcon1; /* memory region 1 configuration */ + unsigned int mcon2; /* memory region 2 configuration */ + unsigned int mcon3; /* memory region 3 configuration */ + /* Control Group 3 */ + unsigned int mcon4; /* memory region 4 configuration */ + unsigned int mcon5; /* memory region 5 configuration */ + unsigned int mcon6; /* memory region 6 configuration */ + unsigned int mcon7; /* memory region 7 configuration */ + /* Control Group 4 */ + unsigned int mcon8; /* memory region 8 configuration */ + unsigned int mcon9; /* memory region 9 configuration */ + unsigned int mcon10; /* memory region 10 configuration */ + unsigned int mcon11; /* memory region 11 configuration */ + /* Control Group 5 */ + unsigned int mcon12; /* memory region 12 configuration */ + unsigned int mcon13; /* memory region 13 configuration */ + unsigned int mcon14; /* memory region 14 configuration */ + unsigned int mcon15; /* memory region 15 configuration */ + /* Control Group 6 */ + unsigned int reserved; /* reserved */ + unsigned int bpcon; /* breakpoint control */ + unsigned int tc; /* trace control */ + unsigned int bcon; /* bus configuration control */ +} i960ha_control_table; + +/* Intel i960HA Processor Control Block */ + +typedef struct { + unsigned int *fault_tbl; /* fault table base address */ + i960ha_control_table + *control_tbl; /* control table base address */ + unsigned int initial_ac; /* AC register initial value */ + unsigned int fault_config; /* fault configuration word */ + void **intr_tbl; /* interrupt table base address */ + void *sys_proc_tbl; /* system procedure table + base address */ + unsigned int reserved; /* reserved */ + unsigned int *intr_stack; /* interrupt stack pointer */ + unsigned int ins_cache_cfg; /* instruction cache + configuration word */ + unsigned int reg_cache_cfg; /* register cache configuration word */ +} i960ha_PRCB; + +typedef i960ha_control_table i960_control_table; +typedef i960ha_PRCB i960_PRCB; + +#define I960_SOFT_RESET_COMMAND 0x30000 + +#define i960_soft_reset( prcb ) \ + { register i960_PRCB *_prcb = (prcb); \ + register unsigned int *_next=0; \ + register unsigned int _cmd = I960_SOFT_RESET_COMMAND; \ + asm volatile( "lda next,%1; \ + sysctl %0,%1,%2; \ + next: mov g0,g0" \ + : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ + : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ + } + + + +#endif +/* end of include file */ diff --git a/c/src/lib/libcpu/i960/include/i960JX_RP_common.h b/c/src/lib/libcpu/i960/include/i960JX_RP_common.h new file mode 100644 index 0000000000..a5d5e4d087 --- /dev/null +++ b/c/src/lib/libcpu/i960/include/i960JX_RP_common.h @@ -0,0 +1,49 @@ +/* + * i960JX and RP Shared Definitions. + * + * $Id$ + */ + +#ifndef __I960JX_RP_COMMON_h +#define __I960JX_RP_COMMON_h + +/* Define JX Core memory mapped register addresses */ +/* Common to Jx and RP: */ +#define DLMCON_ADDR 0xff008100 +#define LMAR0_ADDR 0xff008108 +#define LMMR0_ADDR 0xff00810c +#define LMAR1_ADDR 0xff008110 +#define LMMR1_ADDR 0xff008114 +#define IPB0_ADDR 0xff008400 +#define IPB1_ADDR 0xff008404 +#define DAB0_ADDR 0xff008420 +#define DAB1_ADDR 0xff008424 +#define BPCON_ADDR 0xff008440 +#define IPND_ADDR 0xff008500 +#define IMSK_ADDR 0xff008504 +#define ICON_ADDR 0xff008510 +#define IMAP0_ADDR 0xff008520 +#define IMAP1_ADDR 0xff008524 +#define IMAP2_ADDR 0xff008528 +#define PMCON0_ADDR 0xff008600 +#define PMCON2_ADDR 0xff008608 +#define PMCON4_ADDR 0xff008610 +#define PMCON6_ADDR 0xff008618 +#define PMCON8_ADDR 0xff008620 +#define PMCON10_ADDR 0xff008628 +#define PMCON12_ADDR 0xff008630 +#define PMCON14_ADDR 0xff008638 +#define BCON_ADDR 0xff0086fc +#define PRCB_ADDR 0xff008700 +#define ISP_ADDR 0xff008704 +#define SSP_ADDR 0xff008708 +#define DEVID_ADDR 0xff008710 +#define TRR0_ADDR 0xff000300 +#define TCR0_ADDR 0xff000304 +#define TMR0_ADDR 0xff000308 +#define TRR1_ADDR 0xff000310 +#define TCR1_ADDR 0xff000314 +#define TMR1_ADDR 0xff000318 + +#endif +/* end of include file */ diff --git a/c/src/lib/libcpu/i960/include/i960KA.h b/c/src/lib/libcpu/i960/include/i960KA.h new file mode 100644 index 0000000000..1fc1db21bd --- /dev/null +++ b/c/src/lib/libcpu/i960/include/i960KA.h @@ -0,0 +1,75 @@ +/* + * i960ka.h -- hacked version of CA. Not checked on real hardware. + * + * $Id$ + */ + +#ifndef __i960KA_h +#define __i960KA_h + + +/* i960KA control structures */ + +/* Intel i960KA Control Table */ + +typedef struct { + /* Control Group 0 */ + unsigned int ipb0; /* IP breakpoint 0 */ + unsigned int ipb1; /* IP breakpoint 1 */ + unsigned int dab0; /* data address breakpoint 0 */ + unsigned int dab1; /* data address breakpoint 1 */ + /* Control Group 1 */ + unsigned int imap0; /* interrupt map 0 */ + unsigned int imap1; /* interrupt map 1 */ + unsigned int imap2; /* interrupt map 2 */ + unsigned int icon; /* interrupt control */ + /* Control Group 2 */ + unsigned int mcon0; /* memory region 0 configuration */ + unsigned int mcon1; /* memory region 1 configuration */ + unsigned int mcon2; /* memory region 2 configuration */ + unsigned int mcon3; /* memory region 3 configuration */ + /* Control Group 3 */ + unsigned int mcon4; /* memory region 4 configuration */ + unsigned int mcon5; /* memory region 5 configuration */ + unsigned int mcon6; /* memory region 6 configuration */ + unsigned int mcon7; /* memory region 7 configuration */ + /* Control Group 4 */ + unsigned int mcon8; /* memory region 8 configuration */ + unsigned int mcon9; /* memory region 9 configuration */ + unsigned int mcon10; /* memory region 10 configuration */ + unsigned int mcon11; /* memory region 11 configuration */ + /* Control Group 5 */ + unsigned int mcon12; /* memory region 12 configuration */ + unsigned int mcon13; /* memory region 13 configuration */ + unsigned int mcon14; /* memory region 14 configuration */ + unsigned int mcon15; /* memory region 15 configuration */ + /* Control Group 6 */ + unsigned int reserved; /* reserved */ + unsigned int bpcon; /* breakpoint control */ + unsigned int tc; /* trace control */ + unsigned int bcon; /* bus configuration control */ +} i960ka_control_table; + +/* Intel i960KA Processor Control Block */ + +typedef struct { + unsigned int *fault_tbl; /* fault table base address */ + i960ka_control_table + *control_tbl; /* control table base address */ + unsigned int initial_ac; /* AC register initial value */ + unsigned int fault_config; /* fault configuration word */ + void **intr_tbl; /* interrupt table base address */ + void *sys_proc_tbl; /* system procedure table + base address */ + unsigned int reserved; /* reserved */ + unsigned int *intr_stack; /* interrupt stack pointer */ + unsigned int ins_cache_cfg; /* instruction cache + configuration word */ + unsigned int reg_cache_cfg; /* register cache configuration word */ +} i960ka_PRCB; + +typedef i960ka_control_table i960_control_table; +typedef i960ka_PRCB i960_PRCB; + +#endif +/* end of include file */ diff --git a/c/src/exec/score/cpu/i960/i960RP.h b/c/src/lib/libcpu/i960/include/i960RP.h index 25ed29037a..f186db5095 100644 --- a/c/src/exec/score/cpu/i960/i960RP.h +++ b/c/src/lib/libcpu/i960/include/i960RP.h @@ -10,46 +10,74 @@ #ifndef __I960RP_h #define __I960RP_h -/*----------------------------------------------------------*/ -/* Example 6. Include File (evrp.h) */ -/*----------------------------------------------------------*/ -/* Define JX Core memory mapped register addresses */ -/* Common to Jx and RP: */ -#define DLMCON_ADDR 0xff008100 -#define LMAR0_ADDR 0xff008108 -#define LMMR0_ADDR 0xff00810c -#define LMAR1_ADDR 0xff008110 -#define LMMR1_ADDR 0xff008114 -#define IPB0_ADDR 0xff008400 -#define IPB1_ADDR 0xff008404 -#define DAB0_ADDR 0xff008420 -#define DAB1_ADDR 0xff008424 -#define BPCON_ADDR 0xff008440 -#define IPND_ADDR 0xff008500 -#define IMSK_ADDR 0xff008504 -#define ICON_ADDR 0xff008510 -#define IMAP0_ADDR 0xff008520 -#define IMAP1_ADDR 0xff008524 -#define IMAP2_ADDR 0xff008528 -#define PMCON0_ADDR 0xff008600 -#define PMCON2_ADDR 0xff008608 -#define PMCON4_ADDR 0xff008610 -#define PMCON6_ADDR 0xff008618 -#define PMCON8_ADDR 0xff008620 -#define PMCON10_ADDR 0xff008628 -#define PMCON12_ADDR 0xff008630 -#define PMCON14_ADDR 0xff008638 -#define BCON_ADDR 0xff0086fc -#define PRCB_ADDR 0xff008700 -#define ISP_ADDR 0xff008704 -#define SSP_ADDR 0xff008708 -#define DEVID_ADDR 0xff008710 -#define TRR0_ADDR 0xff000300 -#define TCR0_ADDR 0xff000304 -#define TMR0_ADDR 0xff000308 -#define TRR1_ADDR 0xff000310 -#define TCR1_ADDR 0xff000314 -#define TMR1_ADDR 0xff000318 +/* i960RP control structures */ + +/* Intel i960RP Control Table */ + +typedef struct { + /* Control Group 0 */ + unsigned int rsvd00; + unsigned int rsvd01; + unsigned int rsvd02; + unsigned int rsvd03; + /* Control Group 1 */ + unsigned int imap0; /* interrupt map 0 */ + unsigned int imap1; /* interrupt map 1 */ + unsigned int imap2; /* interrupt map 2 */ + unsigned int icon; /* interrupt control */ + /* Control Group 2 */ + unsigned int pmcon0; /* memory region 0 configuration */ + unsigned int rsvd1; + unsigned int pmcon2; /* memory region 2 configuration */ + unsigned int rsvd2; + /* Control Group 3 */ + unsigned int pmcon4; /* memory region 4 configuration */ + unsigned int rsvd3; + unsigned int pmcon6; /* memory region 6 configuration */ + unsigned int rsvd4; + /* Control Group 4 */ + unsigned int pmcon8; /* memory region 8 configuration */ + unsigned int rsvd5; + unsigned int pmcon10; /* memory region 10 configuration */ + unsigned int rsvd6; + /* Control Group 5 */ + unsigned int pmcon12; /* memory region 12 configuration */ + unsigned int rsvd7; + unsigned int pmcon14; /* memory region 14 configuration */ + unsigned int rsvd8; + /* Control Group 6 */ + unsigned int rsvd9; + unsigned int rsvd10; + unsigned int tc; /* trace control */ + unsigned int bcon; /* bus configuration control */ +} i960rp_control_table; + +/* Intel i960RP Processor Control Block */ + +/* Intel i960RP Processor Control Block */ + +typedef struct { + unsigned int *fault_tbl; /* fault table base address */ + i960rp_control_table + *control_tbl; /* control table base address */ + unsigned int initial_ac; /* AC register initial value */ + unsigned int fault_config; /* fault configuration word */ + void **intr_tbl; /* interrupt table base address */ + void *sys_proc_tbl; /* system procedure table + base address */ + unsigned int reserved; /* reserved */ + unsigned int *intr_stack; /* interrupt stack pointer */ + unsigned int ins_cache_cfg; /* instruction cache + configuration word */ + unsigned int reg_cache_cfg; /* register cache configuration word */ +} i960rp_PRCB; + +typedef i960rp_control_table i960_control_table; +typedef i960rp_PRCB i960_PRCB; + +/* Addresses shared with JX */ + +#include <libcpu/i960JX_RP_common.h> /* RP-only addresses: */ /* RP MMRs */ @@ -314,5 +342,65 @@ #define RP_SEC_MEM_WIND_BASE 0x88000000 #define RP_PRI_MEM_WIND_BASE 0x80000000 +#define i960_unmask_intr( xint ) \ + { register unsigned int _mask= (1<<(xint)); \ + register unsigned int *_imsk = (int * ) IMSK_ADDR; \ + register unsigned int _val= *_imsk; \ + asm volatile( "or %0,%2,%0; \ + st %0,(%1)" \ + : "=d" (_val), "=d" (_imsk), "=d" (_mask) \ + : "0" (_val), "1" (_imsk), "2" (_mask) ); \ + } + +#define i960_mask_intr( xint ) \ + { register unsigned int _mask= (1<<(xint)); \ + register unsigned int *_imsk = (int * ) IMSK_ADDR; \ + register unsigned int _val = *_imsk; \ + asm volatile( "andnot %2,%0,%0; \ + st %0,(%1)" \ + : "=d" (_val), "=d" (_imsk), "=d" (_mask) \ + : "0" (_val), "1" (_imsk), "2" (_mask) ); \ + } +#define i960_clear_intr( xint ) \ + { register unsigned int _xint=xint; \ + register unsigned int _mask=(1<<(xint)); \ + register unsigned int *_ipnd = (int * ) IPND_ADDR; \ + register unsigned int _rslt = 0; \ +asm volatile( "loop_til_cleared: mov 0, %0; \ + atmod %1, %2, %0; \ + bbs %3,%0, loop_til_cleared" \ + : "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \ + : "0" (_rslt), "1" (_ipnd), "2" (_mask), "3" (_xint) ); \ + } + +static inline unsigned int i960_pend_intrs() +{ register unsigned int _intr= *(unsigned int *) IPND_ADDR; + /*register unsigned int *_ipnd = (int * ) IPND_ADDR; \ + asm volatile( "mov (%0),%1" \ + : "=d" (_ipnd), "=d" (_mask) \ + : "0" (_ipnd), "1" (_mask) ); \ */ + return ( _intr ); +} + +static inline unsigned int i960_mask_intrs() +{ register unsigned int _intr= *(unsigned int *) IMSK_ADDR; + /*asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );*/ + return( _intr ); +} + +#define I960_SOFT_RESET_COMMAND 0x300 + +#define i960_soft_reset( prcb ) \ + { register i960_PRCB *_prcb = (prcb); \ + register unsigned int *_next=0; \ + register unsigned int _cmd = I960_SOFT_RESET_COMMAND; \ + asm volatile( "lda next,%1; \ + sysctl %0,%1,%2; \ + next: mov g0,g0" \ + : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ + : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ + } + + #endif /* end of include file */ diff --git a/c/src/lib/libcpu/i960/shared/soft_reset_asm.S b/c/src/lib/libcpu/i960/shared/soft_reset_asm.S new file mode 100644 index 0000000000..c178aa74bd --- /dev/null +++ b/c/src/lib/libcpu/i960/shared/soft_reset_asm.S @@ -0,0 +1,37 @@ +/* + * void __i960_soft_reset_asm + * + * Flush the register cache and save the important (fp, pfp, sp) registers, + * which are clobbered by the reinit operation. (Not documented, but it + * happens). + * + * This may not be used any longer but it is not being purged completely + * in the move to multilib things. + * + * $Id$ + */ + + .data + .align 4 +_soft_reset_reg_save: + .word 0 + .word 0 + .word 0 + .word 0 + + .globl __i960_soft_reset_asm +__i960_soft_reset_asm: + flushreg # flush register cache mov fp, r4 + mov pfp, r5 + mov sp, r6 + stt r4, _soft_reset_reg_save # save fp, pfp, sp + lda __i960_reset_done, r4 + ldconst 0x300, r5 + sysctl r5, r4, g0 # reinit: clobbers almost all registers +__i960_reset_done: + ldt _soft_reset_reg_save, r4 # restore fp, pfp, sp + mov r4, fp + mov r5, pfp + mov r6, sp + ret + |