diff options
Diffstat (limited to 'c/src')
-rw-r--r-- | c/src/exec/score/cpu/a29k/rtems/score/cpu_asm.h (renamed from c/src/exec/score/cpu/a29k/cpu_asm.h) | 0 | ||||
-rw-r--r-- | c/src/exec/score/cpu/i386/rtems/score/asm.h (renamed from c/src/exec/score/cpu/i386/asm.h) | 0 | ||||
-rw-r--r-- | c/src/exec/score/cpu/i960/rtems/score/asm.h (renamed from c/src/exec/score/cpu/i960/asm.h) | 0 | ||||
-rw-r--r-- | c/src/exec/score/cpu/m68k/rtems/score/asm.h (renamed from c/src/exec/score/cpu/m68k/asm.h) | 0 | ||||
-rw-r--r-- | c/src/exec/score/cpu/m68k/rtems/score/m68302.h (renamed from c/src/exec/score/cpu/m68k/m68302.h) | 0 | ||||
-rw-r--r-- | c/src/exec/score/cpu/m68k/rtems/score/m68360.h (renamed from c/src/exec/score/cpu/m68k/m68360.h) | 0 | ||||
-rw-r--r-- | c/src/exec/score/cpu/m68k/rtems/score/qsm.h (renamed from c/src/exec/score/cpu/m68k/qsm.h) | 0 | ||||
-rw-r--r-- | c/src/exec/score/cpu/m68k/rtems/score/sim.h (renamed from c/src/exec/score/cpu/m68k/sim.h) | 0 | ||||
-rw-r--r-- | c/src/exec/score/cpu/mips/rtems/score/mips.h (renamed from c/src/exec/score/cpu/mips64orion/mips64orion.h) | 0 | ||||
-rw-r--r-- | c/src/exec/score/cpu/mips/rtems/score/mips64orion.h | 74 | ||||
-rw-r--r-- | c/src/exec/score/cpu/mips64orion/asm.h | 102 | ||||
-rw-r--r-- | c/src/exec/score/cpu/mips64orion/cpu_asm.h | 115 | ||||
-rw-r--r-- | c/src/exec/score/cpu/mips64orion/rtems/score/asm.h (renamed from c/src/exec/score/cpu/mips/asm.h) | 0 | ||||
-rw-r--r-- | c/src/exec/score/cpu/mips64orion/rtems/score/cpu_asm.h (renamed from c/src/exec/score/cpu/mips/cpu_asm.h) | 0 | ||||
-rw-r--r-- | c/src/exec/score/cpu/mips64orion/rtems/score/mips64orion.h | 74 | ||||
-rw-r--r-- | c/src/exec/score/cpu/no_cpu/rtems/score/asm.h (renamed from c/src/exec/score/cpu/no_cpu/asm.h) | 0 | ||||
-rw-r--r-- | c/src/exec/score/cpu/no_cpu/rtems/score/cpu_asm.h (renamed from c/src/exec/score/cpu/no_cpu/cpu_asm.h) | 0 | ||||
-rw-r--r-- | c/src/exec/score/cpu/powerpc/rtems/score/asm.h | 275 | ||||
-rw-r--r-- | c/src/exec/score/cpu/powerpc/rtems/score/mpc860.h (renamed from c/src/exec/score/cpu/powerpc/mpc860.h) | 0 | ||||
-rw-r--r-- | c/src/exec/score/cpu/sh/rtems/score/asm.h (renamed from c/src/exec/score/cpu/sh/asm.h) | 0 | ||||
-rw-r--r-- | c/src/exec/score/cpu/sparc/rtems/score/asm.h (renamed from c/src/exec/score/cpu/sparc/asm.h) | 0 | ||||
-rw-r--r-- | c/src/exec/score/cpu/sparc/rtems/score/erc32.h (renamed from c/src/exec/score/cpu/sparc/erc32.h) | 0 | ||||
-rw-r--r-- | c/src/lib/libcpu/sparc/include/erc32.h | 521 |
23 files changed, 423 insertions, 738 deletions
diff --git a/c/src/exec/score/cpu/a29k/cpu_asm.h b/c/src/exec/score/cpu/a29k/rtems/score/cpu_asm.h index 65eaf29737..65eaf29737 100644 --- a/c/src/exec/score/cpu/a29k/cpu_asm.h +++ b/c/src/exec/score/cpu/a29k/rtems/score/cpu_asm.h diff --git a/c/src/exec/score/cpu/i386/asm.h b/c/src/exec/score/cpu/i386/rtems/score/asm.h index 9fe867c04c..9fe867c04c 100644 --- a/c/src/exec/score/cpu/i386/asm.h +++ b/c/src/exec/score/cpu/i386/rtems/score/asm.h diff --git a/c/src/exec/score/cpu/i960/asm.h b/c/src/exec/score/cpu/i960/rtems/score/asm.h index a9a0788925..a9a0788925 100644 --- a/c/src/exec/score/cpu/i960/asm.h +++ b/c/src/exec/score/cpu/i960/rtems/score/asm.h diff --git a/c/src/exec/score/cpu/m68k/asm.h b/c/src/exec/score/cpu/m68k/rtems/score/asm.h index 456b213cb2..456b213cb2 100644 --- a/c/src/exec/score/cpu/m68k/asm.h +++ b/c/src/exec/score/cpu/m68k/rtems/score/asm.h diff --git a/c/src/exec/score/cpu/m68k/m68302.h b/c/src/exec/score/cpu/m68k/rtems/score/m68302.h index 084ceac034..084ceac034 100644 --- a/c/src/exec/score/cpu/m68k/m68302.h +++ b/c/src/exec/score/cpu/m68k/rtems/score/m68302.h diff --git a/c/src/exec/score/cpu/m68k/m68360.h b/c/src/exec/score/cpu/m68k/rtems/score/m68360.h index fd78fa1104..fd78fa1104 100644 --- a/c/src/exec/score/cpu/m68k/m68360.h +++ b/c/src/exec/score/cpu/m68k/rtems/score/m68360.h diff --git a/c/src/exec/score/cpu/m68k/qsm.h b/c/src/exec/score/cpu/m68k/rtems/score/qsm.h index e1bf33bc12..e1bf33bc12 100644 --- a/c/src/exec/score/cpu/m68k/qsm.h +++ b/c/src/exec/score/cpu/m68k/rtems/score/qsm.h diff --git a/c/src/exec/score/cpu/m68k/sim.h b/c/src/exec/score/cpu/m68k/rtems/score/sim.h index d70f56d360..d70f56d360 100644 --- a/c/src/exec/score/cpu/m68k/sim.h +++ b/c/src/exec/score/cpu/m68k/rtems/score/sim.h diff --git a/c/src/exec/score/cpu/mips64orion/mips64orion.h b/c/src/exec/score/cpu/mips/rtems/score/mips.h index ec89a32a0d..ec89a32a0d 100644 --- a/c/src/exec/score/cpu/mips64orion/mips64orion.h +++ b/c/src/exec/score/cpu/mips/rtems/score/mips.h diff --git a/c/src/exec/score/cpu/mips/rtems/score/mips64orion.h b/c/src/exec/score/cpu/mips/rtems/score/mips64orion.h new file mode 100644 index 0000000000..ec89a32a0d --- /dev/null +++ b/c/src/exec/score/cpu/mips/rtems/score/mips64orion.h @@ -0,0 +1,74 @@ +/* mips64orion.h + * + * Author: Craig Lebakken <craigl@transition.com> + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/exec/score/cpu/no_cpu/no_cpu.h: + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ +/* @(#)mips64orion.h 08/29/96 1.3 */ + +#ifndef _INCLUDE_MIPS64ORION_h +#define _INCLUDE_MIPS64ORION_h + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the "no cpu" + * family when executing in protected mode. It does + * this by setting variables to indicate which implementation + * dependent features are present in a particular member + * of the family. + */ + +#if defined(R4650) + +#define CPU_MODEL_NAME "R4650" +#define MIPS64ORION_HAS_FPU 1 + +#elif defined(R4600) + +#define CPU_MODEL_NAME "R4600" +#define MIPS64ORION_HAS_FPU 1 + +#else + +#error "Unsupported CPU Model" + +#endif + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "MIPS R46xxx" + +#ifdef __cplusplus +} +#endif + +#endif /* ! _INCLUDE_MIPS64ORION_h */ +/* end of include file */ diff --git a/c/src/exec/score/cpu/mips64orion/asm.h b/c/src/exec/score/cpu/mips64orion/asm.h deleted file mode 100644 index 2d322c2339..0000000000 --- a/c/src/exec/score/cpu/mips64orion/asm.h +++ /dev/null @@ -1,102 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ -/* @(#)asm.h 03/15/96 1.1 */ - -#ifndef __NO_CPU_ASM_h -#define __NO_CPU_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/targopts.h> -#include <rtems/score/mips64orion.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/mips64orion/cpu_asm.h b/c/src/exec/score/cpu/mips64orion/cpu_asm.h deleted file mode 100644 index 5d78f39d7c..0000000000 --- a/c/src/exec/score/cpu/mips64orion/cpu_asm.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * cpu_asm.h - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.h: - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ -/* @(#)cpu_asm.h 08/20/96 1.2 */ - -#ifndef __CPU_ASM_h -#define __CPU_ASM_h - -/* pull in the generated offsets */ - -/* #include <rtems/score/offsets.h> */ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -#define R_FP0 0 -#define R_FP1 1 -#define R_FP2 2 -#define R_FP3 3 -#define R_FP4 4 -#define R_FP5 5 -#define R_FP6 6 -#define R_FP7 7 -#define R_FP8 8 -#define R_FP9 9 -#define R_FP10 10 -#define R_FP11 11 -#define R_FP12 12 -#define R_FP13 13 -#define R_FP14 14 -#define R_FP15 15 -#define R_FP16 16 -#define R_FP17 17 -#define R_FP18 18 -#define R_FP19 19 -#define R_FP20 20 -#define R_FP21 21 -#define R_FP22 22 -#define R_FP23 23 -#define R_FP24 24 -#define R_FP25 25 -#define R_FP26 26 -#define R_FP27 27 -#define R_FP28 28 -#define R_FP29 29 -#define R_FP30 30 -#define R_FP31 31 - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/c/src/exec/score/cpu/mips/asm.h b/c/src/exec/score/cpu/mips64orion/rtems/score/asm.h index 2d322c2339..2d322c2339 100644 --- a/c/src/exec/score/cpu/mips/asm.h +++ b/c/src/exec/score/cpu/mips64orion/rtems/score/asm.h diff --git a/c/src/exec/score/cpu/mips/cpu_asm.h b/c/src/exec/score/cpu/mips64orion/rtems/score/cpu_asm.h index 5d78f39d7c..5d78f39d7c 100644 --- a/c/src/exec/score/cpu/mips/cpu_asm.h +++ b/c/src/exec/score/cpu/mips64orion/rtems/score/cpu_asm.h diff --git a/c/src/exec/score/cpu/mips64orion/rtems/score/mips64orion.h b/c/src/exec/score/cpu/mips64orion/rtems/score/mips64orion.h new file mode 100644 index 0000000000..ec89a32a0d --- /dev/null +++ b/c/src/exec/score/cpu/mips64orion/rtems/score/mips64orion.h @@ -0,0 +1,74 @@ +/* mips64orion.h + * + * Author: Craig Lebakken <craigl@transition.com> + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/exec/score/cpu/no_cpu/no_cpu.h: + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ +/* @(#)mips64orion.h 08/29/96 1.3 */ + +#ifndef _INCLUDE_MIPS64ORION_h +#define _INCLUDE_MIPS64ORION_h + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the "no cpu" + * family when executing in protected mode. It does + * this by setting variables to indicate which implementation + * dependent features are present in a particular member + * of the family. + */ + +#if defined(R4650) + +#define CPU_MODEL_NAME "R4650" +#define MIPS64ORION_HAS_FPU 1 + +#elif defined(R4600) + +#define CPU_MODEL_NAME "R4600" +#define MIPS64ORION_HAS_FPU 1 + +#else + +#error "Unsupported CPU Model" + +#endif + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "MIPS R46xxx" + +#ifdef __cplusplus +} +#endif + +#endif /* ! _INCLUDE_MIPS64ORION_h */ +/* end of include file */ diff --git a/c/src/exec/score/cpu/no_cpu/asm.h b/c/src/exec/score/cpu/no_cpu/rtems/score/asm.h index 1ca7fd435b..1ca7fd435b 100644 --- a/c/src/exec/score/cpu/no_cpu/asm.h +++ b/c/src/exec/score/cpu/no_cpu/rtems/score/asm.h diff --git a/c/src/exec/score/cpu/no_cpu/cpu_asm.h b/c/src/exec/score/cpu/no_cpu/rtems/score/cpu_asm.h index ed58c331bc..ed58c331bc 100644 --- a/c/src/exec/score/cpu/no_cpu/cpu_asm.h +++ b/c/src/exec/score/cpu/no_cpu/rtems/score/cpu_asm.h diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/asm.h b/c/src/exec/score/cpu/powerpc/rtems/score/asm.h new file mode 100644 index 0000000000..af14c95665 --- /dev/null +++ b/c/src/exec/score/cpu/powerpc/rtems/score/asm.h @@ -0,0 +1,275 @@ +/* asm.h + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + * + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 1995. + * i-cubed ltd. + * + * COPYRIGHT (c) 1994. + * On-Line Applications Research Corporation (OAR). + * + * $Id$ + */ + +#ifndef __PPC_ASM_h +#define __PPC_ASM_h + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include <rtems/score/targopts.h> +#include <rtems/score/ppc.h> + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +#ifndef __FLOAT_REGISTER_PREFIX__ +#define __FLOAT_REGISTER_PREFIX__ __REGISTER_PREFIX__ +#endif + +#if (PPC_ABI == PPC_ABI_POWEROPEN) +#ifndef __PROC_LABEL_PREFIX__ +#define __PROC_LABEL_PREFIX__ . +#endif +#endif + +#ifndef __PROC_LABEL_PREFIX__ +#define __PROC_LABEL_PREFIX__ __USER_LABEL_PREFIX__ +#endif + +/* ANSI concatenation macros. */ + +#define CONCAT1(a, b) CONCAT2(a, b) +#define CONCAT2(a, b) a ## b + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for procedure labels. */ + +#define PROC(x) CONCAT1 (__PROC_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* Use the right prefix for floating point registers. */ + +#define FREG(x) CONCAT1 (__FLOAT_REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ +#define r0 REG(0) +#define r1 REG(1) +#define r2 REG(2) +#define r3 REG(3) +#define r4 REG(4) +#define r5 REG(5) +#define r6 REG(6) +#define r7 REG(7) +#define r8 REG(8) +#define r9 REG(9) +#define r10 REG(10) +#define r11 REG(11) +#define r12 REG(12) +#define r13 REG(13) +#define r14 REG(14) +#define r15 REG(15) +#define r16 REG(16) +#define r17 REG(17) +#define r18 REG(18) +#define r19 REG(19) +#define r20 REG(20) +#define r21 REG(21) +#define r22 REG(22) +#define r23 REG(23) +#define r24 REG(24) +#define r25 REG(25) +#define r26 REG(26) +#define r27 REG(27) +#define r28 REG(28) +#define r29 REG(29) +#define r30 REG(30) +#define r31 REG(31) +#define f0 FREG(0) +#define f1 FREG(1) +#define f2 FREG(2) +#define f3 FREG(3) +#define f4 FREG(4) +#define f5 FREG(5) +#define f6 FREG(6) +#define f7 FREG(7) +#define f8 FREG(8) +#define f9 FREG(9) +#define f10 FREG(10) +#define f11 FREG(11) +#define f12 FREG(12) +#define f13 FREG(13) +#define f14 FREG(14) +#define f15 FREG(15) +#define f16 FREG(16) +#define f17 FREG(17) +#define f18 FREG(18) +#define f19 FREG(19) +#define f20 FREG(20) +#define f21 FREG(21) +#define f22 FREG(22) +#define f23 FREG(23) +#define f24 FREG(24) +#define f25 FREG(25) +#define f26 FREG(26) +#define f27 FREG(27) +#define f28 FREG(28) +#define f29 FREG(29) +#define f30 FREG(30) +#define f31 FREG(31) + +/* + * Some special purpose registers (SPRs). + */ +#define srr0 0x01a +#define srr1 0x01b +#define srr2 0x3de /* IBM 400 series only */ +#define srr3 0x3df /* IBM 400 series only */ +#define sprg0 0x110 +#define sprg1 0x111 +#define sprg2 0x112 +#define sprg3 0x113 + + +/* the following SPR/DCR registers exist only in IBM 400 series */ +#define dear 0x3d5 +#define evpr 0x3d6 /* SPR: exception vector prefix register */ +#define iccr 0x3fb /* SPR: instruction cache control reg. */ +#define dccr 0x3fa /* SPR: data cache control reg. */ + +#define exisr 0x040 /* DCR: external interrupt status register */ +#define exier 0x042 /* DCR: external interrupt enable register */ +#define br0 0x080 /* DCR: memory bank register 0 */ +#define br1 0x081 /* DCR: memory bank register 1 */ +#define br2 0x082 /* DCR: memory bank register 2 */ +#define br3 0x083 /* DCR: memory bank register 3 */ +#define br4 0x084 /* DCR: memory bank register 4 */ +#define br5 0x085 /* DCR: memory bank register 5 */ +#define br6 0x086 /* DCR: memory bank register 6 */ +#define br7 0x087 /* DCR: memory bank register 7 */ +/* end of IBM400 series register definitions */ + +/* The following registers are for the MPC8x0 */ +#define der 0x095 /* Debug Enable Register */ +/* end of MPC8x0 registers */ + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC_VAR(sym) .globl SYM (sym) +#define EXTERN_VAR(sym) .extern SYM (sym) +#define PUBLIC_PROC(sym) .globl PROC (sym) +#define EXTERN_PROC(sym) .extern PROC (sym) + +/* Other potentially assembler specific operations */ +#if PPC_ASM == PPC_ASM_ELF +#define ALIGN(n,p) .align p +#define DESCRIPTOR(x) \ + .section .descriptors,"aw"; \ + PUBLIC_VAR (x); \ +SYM (x):; \ + .long PROC (x); \ + .long s.got; \ + .long 0 + +#define EXT_SYM_REF(x) .long x +#define EXT_PROC_REF(x) .long x + +/* + * Define macros to handle section beginning and ends. + */ + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA .data +#define END_DATA +#define BEGIN_BSS .bss +#define END_BSS +#define END + +#elif PPC_ASM == PPC_ASM_XCOFF +#define ALIGN(n,p) .align p +#define DESCRIPTOR(x) \ + .csect x[DS]; \ + .globl x[DS]; \ + .long PROC (x)[PR]; \ + .long TOC[tc0] + +#define EXT_SYM_REF(x) .long x[RW] +#define EXT_PROC_REF(x) .long x[DS] + +/* + * Define macros to handle section beginning and ends. + */ + +#define BEGIN_CODE_DCL .csect .text[PR] +#define END_CODE_DCL +#define BEGIN_DATA_DCL .csect .data[RW] +#define END_DATA_DCL +#define BEGIN_CODE .csect .text[PR] +#define END_CODE +#define BEGIN_DATA .csect .data[RW] +#define END_DATA +#define BEGIN_BSS .bss +#define END_BSS +#define END + +#else +#error "PPC_ASM_TYPE is not properly defined" +#endif +#ifndef PPC_ASM +#error "PPC_ASM_TYPE is not properly defined" +#endif + + +#endif +/* end of include file */ + + diff --git a/c/src/exec/score/cpu/powerpc/mpc860.h b/c/src/exec/score/cpu/powerpc/rtems/score/mpc860.h index 7daee45bf0..7daee45bf0 100644 --- a/c/src/exec/score/cpu/powerpc/mpc860.h +++ b/c/src/exec/score/cpu/powerpc/rtems/score/mpc860.h diff --git a/c/src/exec/score/cpu/sh/asm.h b/c/src/exec/score/cpu/sh/rtems/score/asm.h index f6fff9f40e..f6fff9f40e 100644 --- a/c/src/exec/score/cpu/sh/asm.h +++ b/c/src/exec/score/cpu/sh/rtems/score/asm.h diff --git a/c/src/exec/score/cpu/sparc/asm.h b/c/src/exec/score/cpu/sparc/rtems/score/asm.h index b9a3aabeea..b9a3aabeea 100644 --- a/c/src/exec/score/cpu/sparc/asm.h +++ b/c/src/exec/score/cpu/sparc/rtems/score/asm.h diff --git a/c/src/exec/score/cpu/sparc/erc32.h b/c/src/exec/score/cpu/sparc/rtems/score/erc32.h index aa0eef05d9..aa0eef05d9 100644 --- a/c/src/exec/score/cpu/sparc/erc32.h +++ b/c/src/exec/score/cpu/sparc/rtems/score/erc32.h diff --git a/c/src/lib/libcpu/sparc/include/erc32.h b/c/src/lib/libcpu/sparc/include/erc32.h deleted file mode 100644 index aa0eef05d9..0000000000 --- a/c/src/lib/libcpu/sparc/include/erc32.h +++ /dev/null @@ -1,521 +0,0 @@ -/* erc32.h - * - * This include file contains information pertaining to the ERC32. - * The ERC32 is a custom SPARC V7 implementation based on the Cypress - * 601/602 chipset. This CPU has a number of on-board peripherals and - * was developed by the European Space Agency to target space applications. - * - * NOTE: Other than where absolutely required, this version currently - * supports only the peripherals and bits used by the basic board - * support package. This includes at least significant pieces of - * the following items: - * - * + UART Channels A and B - * + General Purpose Timer - * + Real Time Clock - * + Watchdog Timer (so it can be disabled) - * + Control Register (so powerdown mode can be enabled) - * + Memory Control Register - * + Interrupt Control - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Ported to ERC32 implementation of the SPARC by On-Line Applications - * Research Corporation (OAR) under contract to the European Space - * Agency (ESA). - * - * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. - * European Space Agency. - * - * $Id$ - */ - -#ifndef _INCLUDE_ERC32_h -#define _INCLUDE_ERC32_h - -#include <rtems/score/sparc.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Interrupt Sources - * - * The interrupt source numbers directly map to the trap type and to - * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask, - * and the Interrupt Pending Registers. - */ - -#define ERC32_INTERRUPT_MASKED_ERRORS 1 -#define ERC32_INTERRUPT_EXTERNAL_1 2 -#define ERC32_INTERRUPT_EXTERNAL_2 3 -#define ERC32_INTERRUPT_UART_A_RX_TX 4 -#define ERC32_INTERRUPT_UART_B_RX_TX 5 -#define ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR 6 -#define ERC32_INTERRUPT_UART_ERROR 7 -#define ERC32_INTERRUPT_DMA_ACCESS_ERROR 8 -#define ERC32_INTERRUPT_DMA_TIMEOUT 9 -#define ERC32_INTERRUPT_EXTERNAL_3 10 -#define ERC32_INTERRUPT_EXTERNAL_4 11 -#define ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER 12 -#define ERC32_INTERRUPT_REAL_TIME_CLOCK 13 -#define ERC32_INTERRUPT_EXTERNAL_5 14 -#define ERC32_INTERRUPT_WATCHDOG_TIMEOUT 15 - -#ifndef ASM - -/* - * Trap Types for on-chip peripherals - * - * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments - * - * NOTE: The priority level for each source corresponds to the least - * significant nibble of the trap type. - */ - -#define ERC32_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) - -#define ERC32_TRAP_SOURCE( _trap ) ((_trap) - 0x10) - -#define ERC32_Is_MEC_Trap( _trap ) \ - ( (_trap) >= ERC32_TRAP_TYPE( ERC32_INTERRUPT_MASKED_ERRORS ) && \ - (_trap) <= ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ) ) - -/* - * Structure for ERC32 memory mapped registers. - * - * Source: Section 3.25.2 - Register Address Map - * - * NOTE: There is only one of these structures per CPU, its base address - * is 0x01f80000, and the variable MEC is placed there by the - * linkcmds file. - */ - -typedef struct { - volatile unsigned32 Control; /* offset 0x00 */ - volatile unsigned32 Software_Reset; /* offset 0x04 */ - volatile unsigned32 Power_Down; /* offset 0x08 */ - volatile unsigned32 Unimplemented_0; /* offset 0x0c */ - volatile unsigned32 Memory_Configuration; /* offset 0x10 */ - volatile unsigned32 IO_Configuration; /* offset 0x14 */ - volatile unsigned32 Wait_State_Configuration; /* offset 0x18 */ - volatile unsigned32 Unimplemented_1; /* offset 0x1c */ - volatile unsigned32 Memory_Access_0; /* offset 0x20 */ - volatile unsigned32 Memory_Access_1; /* offset 0x24 */ - volatile unsigned32 Unimplemented_2[ 7 ]; /* offset 0x28 */ - volatile unsigned32 Interrupt_Shape; /* offset 0x44 */ - volatile unsigned32 Interrupt_Pending; /* offset 0x48 */ - volatile unsigned32 Interrupt_Mask; /* offset 0x4c */ - volatile unsigned32 Interrupt_Clear; /* offset 0x50 */ - volatile unsigned32 Interrupt_Force; /* offset 0x54 */ - volatile unsigned32 Unimplemented_3[ 2 ]; /* offset 0x58 */ - /* offset 0x60 */ - volatile unsigned32 Watchdog_Program_and_Timeout_Acknowledge; - volatile unsigned32 Watchdog_Trap_Door_Set; /* offset 0x64 */ - volatile unsigned32 Unimplemented_4[ 6 ]; /* offset 0x68 */ - volatile unsigned32 Real_Time_Clock_Counter; /* offset 0x80 */ - volatile unsigned32 Real_Time_Clock_Scalar; /* offset 0x84 */ - volatile unsigned32 General_Purpose_Timer_Counter; /* offset 0x88 */ - volatile unsigned32 General_Purpose_Timer_Scalar; /* offset 0x8c */ - volatile unsigned32 Unimplemented_5[ 2 ]; /* offset 0x90 */ - volatile unsigned32 Timer_Control; /* offset 0x98 */ - volatile unsigned32 Unimplemented_6; /* offset 0x9c */ - volatile unsigned32 System_Fault_Status; /* offset 0xa0 */ - volatile unsigned32 First_Failing_Address; /* offset 0xa4 */ - volatile unsigned32 First_Failing_Data; /* offset 0xa8 */ - volatile unsigned32 First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */ - volatile unsigned32 Error_and_Reset_Status; /* offset 0xb0 */ - volatile unsigned32 Error_Mask; /* offset 0xb4 */ - volatile unsigned32 Unimplemented_7[ 2 ]; /* offset 0xb8 */ - volatile unsigned32 Debug_Control; /* offset 0xc0 */ - volatile unsigned32 Breakpoint; /* offset 0xc4 */ - volatile unsigned32 Watchpoint; /* offset 0xc8 */ - volatile unsigned32 Unimplemented_8; /* offset 0xcc */ - volatile unsigned32 Test_Control; /* offset 0xd0 */ - volatile unsigned32 Test_Data; /* offset 0xd4 */ - volatile unsigned32 Unimplemented_9[ 2 ]; /* offset 0xd8 */ - volatile unsigned32 UART_Channel_A; /* offset 0xe0 */ - volatile unsigned32 UART_Channel_B; /* offset 0xe4 */ - volatile unsigned32 UART_Status; /* offset 0xe8 */ -} ERC32_Register_Map; - -#endif - -/* - * The following constants are intended to be used ONLY in assembly - * language files. - * - * NOTE: The intended style of usage is to load the address of MEC - * into a register and then use these as displacements from - * that register. - */ - -#ifdef ASM - -#define ERC32_MEC_CONTROL_OFFSET 0x00 -#define ERC32_MEC_SOFTWARE_RESET_OFFSET 0x04 -#define ERC32_MEC_POWER_DOWN_OFFSET 0x08 -#define ERC32_MEC_UNIMPLEMENTED_0_OFFSET 0x0C -#define ERC32_MEC_MEMORY_CONFIGURATION_OFFSET 0x10 -#define ERC32_MEC_IO_CONFIGURATION_OFFSET 0x14 -#define ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET 0x18 -#define ERC32_MEC_UNIMPLEMENTED_1_OFFSET 0x1C -#define ERC32_MEC_MEMORY_ACCESS_0_OFFSET 0x20 -#define ERC32_MEC_MEMORY_ACCESS_1_OFFSET 0x24 -#define ERC32_MEC_UNIMPLEMENTED_2_OFFSET 0x28 -#define ERC32_MEC_INTERRUPT_SHAPE_OFFSET 0x44 -#define ERC32_MEC_INTERRUPT_PENDING_OFFSET 0x48 -#define ERC32_MEC_INTERRUPT_MASK_OFFSET 0x4C -#define ERC32_MEC_INTERRUPT_CLEAR_OFFSET 0x50 -#define ERC32_MEC_INTERRUPT_FORCE_OFFSET 0x54 -#define ERC32_MEC_UNIMPLEMENTED_3_OFFSET 0x58 -#define ERC32_MEC_WATCHDOG_PROGRAM_AND_TIMEOUT_ACKNOWLEDGE_OFFSET 0x60 -#define ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET 0x64 -#define ERC32_MEC_UNIMPLEMENTED_4_OFFSET 0x6C -#define ERC32_MEC_REAL_TIME_CLOCK_COUNTER_OFFSET 0x80 -#define ERC32_MEC_REAL_TIME_CLOCK_SCALAR_OFFSET 0x84 -#define ERC32_MEC_GENERAL_PURPOSE_TIMER_COUNTER_OFFSET 0x88 -#define ERC32_MEC_GENERAL_PURPOSE_TIMER_SCALAR_OFFSET 0x8C -#define ERC32_MEC_UNIMPLEMENTED_5_OFFSET 0x90 -#define ERC32_MEC_TIMER_CONTROL_OFFSET 0x98 -#define ERC32_MEC_UNIMPLEMENTED_6_OFFSET 0x9C -#define ERC32_MEC_SYSTEM_FAULT_STATUS_OFFSET 0xA0 -#define ERC32_MEC_FIRST_FAILING_ADDRESS_OFFSET 0xA4 -#define ERC32_MEC_FIRST_FAILING_DATA_OFFSET 0xA8 -#define ERC32_MEC_FIRST_FAILING_SYNDROME_AND_CHECK_BITS_OFFSET 0xAC -#define ERC32_MEC_ERROR_AND_RESET_STATUS_OFFSET 0xB0 -#define ERC32_MEC_ERROR_MASK_OFFSET 0xB4 -#define ERC32_MEC_UNIMPLEMENTED_7_OFFSET 0xB8 -#define ERC32_MEC_DEBUG_CONTROL_OFFSET 0xC0 -#define ERC32_MEC_BREAKPOINT_OFFSET 0xC4 -#define ERC32_MEC_WATCHPOINT_OFFSET 0xC8 -#define ERC32_MEC_UNIMPLEMENTED_8_OFFSET 0xCC -#define ERC32_MEC_TEST_CONTROL_OFFSET 0xD0 -#define ERC32_MEC_TEST_DATA_OFFSET 0xD4 -#define ERC32_MEC_UNIMPLEMENTED_9_OFFSET 0xD8 -#define ERC32_MEC_UART_CHANNEL_A_OFFSET 0xE0 -#define ERC32_MEC_UART_CHANNEL_B_OFFSET 0xE4 -#define ERC32_MEC_UART_STATUS_OFFSET 0xE8 - -#endif - -/* - * The following defines the bits in the Configuration Register. - */ - -#define ERC32_CONFIGURATION_POWER_DOWN_MASK 0x00000001 -#define ERC32_CONFIGURATION_POWER_DOWN_ALLOWED 0x00000001 -#define ERC32_CONFIGURATION_POWER_DOWN_DISABLED 0x00000000 - -#define ERC32_CONFIGURATION_SOFTWARE_RESET_MASK 0x00000002 -#define ERC32_CONFIGURATION_SOFTWARE_RESET_ALLOWED 0x00000002 -#define ERC32_CONFIGURATION_SOFTWARE_RESET_DISABLED 0x00000000 - -#define ERC32_CONFIGURATION_BUS_TIMEOUT_MASK 0x00000004 -#define ERC32_CONFIGURATION_BUS_TIMEOUT_ENABLED 0x00000004 -#define ERC32_CONFIGURATION_BUS_TIMEOUT_DISABLED 0x00000000 - -#define ERC32_CONFIGURATION_ACCESS_PROTECTION_MASK 0x00000008 -#define ERC32_CONFIGURATION_ACCESS_PROTECTION_ENABLED 0x00000008 -#define ERC32_CONFIGURATION_ACCESS_PROTECTION_DISABLED 0x00000000 - - -/* - * The following defines the bits in the Memory Configuration Register. - */ - -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001C00 -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_256K ( 0 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_512K ( 1 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_1MB ( 2 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_2MB ( 3 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_4MB ( 4 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_8MB ( 5 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_16MB ( 6 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB ( 7 << 10 ) - -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x001C0000 -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K ( 0 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K ( 1 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K ( 2 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M ( 3 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M ( 4 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M ( 5 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M ( 6 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M ( 7 << 18 ) - -/* - * The following defines the bits in the Timer Control Register. - */ - -#define ERC32_MEC_TIMER_CONTROL_GCR 0x00000001 /* 1 = reload at 0 */ - /* 0 = stop at 0 */ -#define ERC32_MEC_TIMER_CONTROL_GCL 0x00000002 /* 1 = load and start */ - /* 0 = no function */ -#define ERC32_MEC_TIMER_CONTROL_GSE 0x00000004 /* 1 = enable counting */ - /* 0 = hold scalar and counter */ -#define ERC32_MEC_TIMER_CONTROL_GSL 0x00000008 /* 1 = load scalar and start */ - /* 0 = no function */ - -#define ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100 /* 1 = reload at 0 */ - /* 0 = stop at 0 */ -#define ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200 /* 1 = load and start */ - /* 0 = no function */ -#define ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400 /* 1 = enable counting */ - /* 0 = hold scalar and counter */ -#define ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800 /* 1 = load scalar and start */ - /* 0 = no function */ - -/* - * The following defines the bits in the UART Control Registers. - * - */ - -#define ERC32_MEC_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ - -/* - * The following defines the bits in the MEC UART Control Registers. - */ - -#define ERC32_MEC_UART_STATUS_DR 0x00000001 /* Data Ready */ -#define ERC32_MEC_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ -#define ERC32_MEC_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ -#define ERC32_MEC_UART_STATUS_FE 0x00000010 /* RX Framing Error */ -#define ERC32_MEC_UART_STATUS_PE 0x00000020 /* RX Parity Error */ -#define ERC32_MEC_UART_STATUS_OE 0x00000040 /* RX Overrun Error */ -#define ERC32_MEC_UART_STATUS_CU 0x00000080 /* Clear Errors */ -#define ERC32_MEC_UART_STATUS_TXE 0x00000006 /* TX Empty */ -#define ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */ -#define ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */ -#define ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */ -#define ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */ - -#define ERC32_MEC_UART_STATUS_DRA (ERC32_MEC_UART_STATUS_DR << 0) -#define ERC32_MEC_UART_STATUS_TSEA (ERC32_MEC_UART_STATUS_TSE << 0) -#define ERC32_MEC_UART_STATUS_THEA (ERC32_MEC_UART_STATUS_THE << 0) -#define ERC32_MEC_UART_STATUS_FEA (ERC32_MEC_UART_STATUS_FE << 0) -#define ERC32_MEC_UART_STATUS_PEA (ERC32_MEC_UART_STATUS_PE << 0) -#define ERC32_MEC_UART_STATUS_OEA (ERC32_MEC_UART_STATUS_OE << 0) -#define ERC32_MEC_UART_STATUS_CUA (ERC32_MEC_UART_STATUS_CU << 0) -#define ERC32_MEC_UART_STATUS_TXEA (ERC32_MEC_UART_STATUS_TXE << 0) - -#define ERC32_MEC_UART_STATUS_DRB (ERC32_MEC_UART_STATUS_DR << 16) -#define ERC32_MEC_UART_STATUS_TSEB (ERC32_MEC_UART_STATUS_TSE << 16) -#define ERC32_MEC_UART_STATUS_THEB (ERC32_MEC_UART_STATUS_THE << 16) -#define ERC32_MEC_UART_STATUS_FEB (ERC32_MEC_UART_STATUS_FE << 16) -#define ERC32_MEC_UART_STATUS_PEB (ERC32_MEC_UART_STATUS_PE << 16) -#define ERC32_MEC_UART_STATUS_OEB (ERC32_MEC_UART_STATUS_OE << 16) -#define ERC32_MEC_UART_STATUS_CUB (ERC32_MEC_UART_STATUS_CU << 16) -#define ERC32_MEC_UART_STATUS_TXEB (ERC32_MEC_UART_STATUS_TXE << 16) - -#ifndef ASM - -/* - * This is used to manipulate the on-chip registers. - * - * The following symbol must be defined in the linkcmds file and point - * to the correct location. - */ - -extern ERC32_Register_Map ERC32_MEC; - -/* - * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, - * and the Interrupt Pending Registers. - * - * NOTE: For operations which are not atomic, this code disables interrupts - * to guarantee there are no intervening accesses to the same register. - * The operations which read the register, modify the value and then - * store the result back are vulnerable. - */ - -#define ERC32_Clear_interrupt( _source ) \ - do { \ - ERC32_MEC.Interrupt_Clear = (1 << (_source)); \ - } while (0) - -#define ERC32_Force_interrupt( _source ) \ - do { \ - unsigned32 _level; \ - \ - sparc_disable_interrupts( _level ); \ - ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \ - ERC32_MEC.Interrupt_Force = (1 << (_source)); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -#define ERC32_Is_interrupt_pending( _source ) \ - (ERC32_MEC.Interrupt_Pending & (1 << (_source))) - -#define ERC32_Is_interrupt_masked( _source ) \ - (ERC32_MEC.Interrupt_Masked & (1 << (_source))) - -#define ERC32_Mask_interrupt( _source ) \ - do { \ - unsigned32 _level; \ - \ - sparc_disable_interrupts( _level ); \ - ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -#define ERC32_Unmask_interrupt( _source ) \ - do { \ - unsigned32 _level; \ - \ - sparc_disable_interrupts( _level ); \ - ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -#define ERC32_Disable_interrupt( _source, _previous ) \ - do { \ - unsigned32 _level; \ - unsigned32 _mask = 1 << (_source); \ - \ - sparc_disable_interrupts( _level ); \ - (_previous) = ERC32_MEC.Interrupt_Mask; \ - ERC32_MEC.Interrupt_Mask = _previous | _mask; \ - sparc_enable_interrupts( _level ); \ - (_previous) &= _mask; \ - } while (0) - -#define ERC32_Restore_interrupt( _source, _previous ) \ - do { \ - unsigned32 _level; \ - unsigned32 _mask = 1 << (_source); \ - \ - sparc_disable_interrupts( _level ); \ - ERC32_MEC.Interrupt_Mask = \ - (ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -/* - * The following macros attempt to hide the fact that the General Purpose - * Timer and Real Time Clock Timer share the Timer Control Register. Because - * the Timer Control Register is write only, we must mirror it in software - * and insure that writes to one timer do not alter the current settings - * and status of the other timer. - * - * This code promotes the view that the two timers are completely independent. - * By exclusively using the routines below to access the Timer Control - * Register, the application can view the system as having a General Purpose - * Timer Control Register and a Real Time Clock Timer Control Register - * rather than the single shared value. - * - * Each logical timer control register is organized as follows: - * - * D0 - Counter Reload - * 1 = reload counter at zero and restart - * 0 = stop counter at zero - * - * D1 - Counter Load - * 1 = load counter with preset value and restart - * 0 = no function - * - * D2 - Enable - * 1 = enable counting - * 0 = hold scaler and counter - * - * D3 - Scaler Load - * 1 = load scalar with preset value and restart - * 0 = no function - * - * To insure the management of the mirror is atomic, we disable interrupts - * around updates. - */ - -#define ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000001 -#define ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 - -#define ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER 0x00000002 - -#define ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING 0x00000004 -#define ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 - -#define ERC32_MEC_TIMER_COUNTER_LOAD_SCALER 0x00000008 - -#define ERC32_MEC_TIMER_COUNTER_RELOAD_MASK 0x00000001 -#define ERC32_MEC_TIMER_COUNTER_ENABLE_MASK 0x00000004 - -#define ERC32_MEC_TIMER_COUNTER_DEFINED_MASK 0x0000000F -#define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000005 - -extern unsigned32 _ERC32_MEC_Timer_Control_Mirror; - -/* - * This macros manipulate the General Purpose Timer portion of the - * Timer Control register and promote the view that there are actually - * two independent Timer Control Registers. - */ - -#define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \ - do { \ - unsigned32 _level; \ - unsigned32 _control; \ - unsigned32 __value; \ - \ - __value = ((_value) & 0x0f); \ - sparc_disable_interrupts( _level ); \ - _control = _ERC32_MEC_Timer_Control_Mirror; \ - _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \ - _ERC32_MEC_Timer_Control_Mirror = _control | _value; \ - _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \ - _control |= __value; \ - /* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \ - ERC32_MEC.Timer_Control = _control; \ - sparc_enable_interrupts( _level ); \ - } while ( 0 ) - -#define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \ - do { \ - (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \ - } while ( 0 ) - -/* - * This macros manipulate the Real Timer Clock Timer portion of the - * Timer Control register and promote the view that there are actually - * two independent Timer Control Registers. - */ - -#define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \ - do { \ - unsigned32 _level; \ - unsigned32 _control; \ - unsigned32 __value; \ - \ - __value = ((_value) & 0x0f) << 8; \ - sparc_disable_interrupts( _level ); \ - _control = _ERC32_MEC_Timer_Control_Mirror; \ - _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \ - _ERC32_MEC_Timer_Control_Mirror = _control | __value; \ - _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \ - _control |= __value; \ - /* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \ - ERC32_MEC.Timer_Control = _control; \ - sparc_enable_interrupts( _level ); \ - } while ( 0 ) - -#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \ - do { \ - (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \ - } while ( 0 ) - - -#endif /* !ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* !_INCLUDE_ERC32_h */ -/* end of include file */ - |