diff options
Diffstat (limited to 'c/src')
21 files changed, 969 insertions, 476 deletions
diff --git a/c/src/lib/libbsp/powerpc/ep1a/ChangeLog b/c/src/lib/libbsp/powerpc/ep1a/ChangeLog index 26b4fd6f67..e25e3d21bb 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/ChangeLog +++ b/c/src/lib/libbsp/powerpc/ep1a/ChangeLog @@ -1,3 +1,16 @@ +2009-10-16 Jennifer Averett <jennifer@OARcorp.com> + + * Makefile.am, configure.ac, preinstall.am, console/alloc360.c, + console/config.c, console/console.c, console/m68360.h, + console/mc68360_scc.c, console/rsPMCQ1.c, console/rsPMCQ1.h, + include/bsp.h, irq/irq_init.c, irq/openpic_xxx_irq.c, start/start.S, + startup/bspstart.c, startup/linkcmds, vme/VMEConfig.h: + Updated and tested against RTEMS 4.9. Updated README file to latest + source status. Modified to use the shared irq source code. Turned off + debugging, cleaned up warnings, removed unused code. Tested with two + PMCQ1 serial cards. Tested MC68360 serial ports and VME using + external tests. + * README, irq/irq.h, vme/vmeconfig.c: New files. 2008-12-08 Ralf Corsépius <ralf.corsepius@rtems.org> * bsp_specs: Backport from CVS-HEAD. diff --git a/c/src/lib/libbsp/powerpc/ep1a/Makefile.am b/c/src/lib/libbsp/powerpc/ep1a/Makefile.am index 0777710acc..ebad7f5db0 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/Makefile.am +++ b/c/src/lib/libbsp/powerpc/ep1a/Makefile.am @@ -22,37 +22,38 @@ include_bspdir = $(includedir)/bsp dist_project_lib_DATA += startup/linkcmds startup_SOURCES = startup/bspstart.c ../../shared/bootcard.c \ - ../../shared/bsppost.c ../../shared/bsppredriverhook.c \ - ../../shared/bsplibc.c ../../powerpc/shared/startup/sbrk.c \ - ../../shared/bspclean.c ../../shared/gnatinstallhandler.c \ - ../../powerpc/shared/startup/pgtbl_setup.c \ - ../../powerpc/shared/startup/pgtbl_activate.c \ - ../../powerpc/shared/showbats.c + ../../shared/bspclean.c ../../shared/bsplibc.c \ + ../../shared/sbrk.c \ + ../../shared/gnatinstallhandler.c \ + ../../powerpc/shared/showbats.c \ + ../../shared/bsppost.c ../../shared/bsppredriverhook.c -pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c -include_bsp_HEADERS = ../../powerpc/shared/console/uart.h \ - ../../powerpc/shared/motorola/motorola.h \ - ../../powerpc/shared/residual/residual.h \ - ../../powerpc/shared/residual/pnp.h \ - ../../powerpc/shared/console/consoleIo.h console/rsPMCQ1.h +pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c console_SOURCES = console/console.c console/ns16550cfg.c \ console/mc68360_scc.c console/rsPMCQ1.c console/alloc360.c \ console/init68360.c -include_bsp_HEADERS += ../../powerpc/shared/openpic/openpic.h -openpic_SOURCES = ../../powerpc/shared/openpic/openpic.h \ - ../../powerpc/shared/openpic/openpic.c +include_bsp_HEADERS = ../../powerpc/shared/pci/pci.h \ + ../../powerpc/shared/motorola/motorola.h \ + ../../powerpc/shared/residual/residual.h \ + ../../powerpc/shared/residual/pnp.h \ + ../../powerpc/shared/console/consoleIo.h console/rsPMCQ1.h -include_bsp_HEADERS += ../../powerpc/shared/pci/pci.h pci_SOURCES = pci/no_host_bridge.c ../../powerpc/shared/pci/pci.c \ - ../../powerpc/shared/pci/pcifinddevice.c + ../../powerpc/shared/pci/pcifinddevice.c -include_bsp_HEADERS += ../../powerpc/shared/irq/irq.h \ +include_bsp_HEADERS += irq/irq.h \ ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h \ ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \ ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h -irq_SOURCES = irq/irq_init.c irq/openpic_xxx_irq.c ../../powerpc/shared/irq/i8259.c + +irq_SOURCES = irq/irq.h irq/irq_init.c irq/openpic_xxx_irq.c \ + ../../powerpc/shared/irq/i8259.c + +include_bsp_HEADERS += ../../powerpc/shared/openpic/openpic.h + +openpic_SOURCES = ../../powerpc/shared/openpic/openpic.c include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \ vme/VMEConfig.h \ @@ -64,7 +65,7 @@ include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \ vme_SOURCES = ../../shared/vmeUniverse/vmeUniverse.c \ ../../shared/vmeUniverse/bspVmeDmaList.c \ - ../shared/vme/vmeconfig.c \ + vme/vmeconfig.c \ ../shared/vme/vme_universe.c \ ../../shared/vmeUniverse/vme_am_defs.h @@ -78,9 +79,12 @@ rtems_crti.$(OBJEXT): ../../powerpc/shared/start/rtems_crti.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA += rtems_crti.$(OBJEXT) +EXTRA_DIST += README + noinst_LIBRARIES = libbsp.a -libbsp_a_SOURCES = $(startup_SOURCES) $(pclock_SOURCES) $(console_SOURCES) \ - $(openpic_SOURCES) $(pci_SOURCES) $(irq_SOURCES) $(vme_SOURCES) +libbsp_a_SOURCES = $(pclock_SOURCES) $(console_SOURCES) $(irq_SOURCES) \ + $(pci_SOURCES) $(vectors_SOURCES) $(startup_SOURCES) \ + $(openpic_SOURCES) $(vme_SOURCES) libbsp_a_LIBADD = \ ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \ diff --git a/c/src/lib/libbsp/powerpc/ep1a/README b/c/src/lib/libbsp/powerpc/ep1a/README new file mode 100644 index 0000000000..4a2e9e8166 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/ep1a/README @@ -0,0 +1,46 @@ +# +# $Id$ +# + +BSP NAME: ep1a +BOARD: RADSTONE EP1A +BUS: N/A +CPU FAMILY: ppc +CPU: PowerPC 8245 +COPROCESSORS: N/A +MODE: 32 bit mode + +DEBUG MONITOR: see note. + +PERIPHERALS +=========== +TIMERS: PPC internal Timebase register + RESOLUTION: +SERIAL PORTS: 1 onboard QUIC, optional 2 mezannes with QUIC chips +REAL-TIME CLOCK: xxx +DMA: none +VIDEO: none +SCSI: none +NETWORKING: none + +DRIVER INFORMATION +================== +CLOCK DRIVER: PPC internal +IOSUPP DRIVER: N/A +SHMSUPP: N/A +TIMER DRIVER: PPC internal +TTY DRIVER: PPC internal + +STDIO +===== +PORT: Console port 0 +ELECTRICAL: na +BAUD: 9600 +BITS PER CHARACTER: 8 +PARITY: n +STOP BITS: 1 + +Notes +===== +This bsp has been tested with an custom ep1a, which had two +PMCQ1 Daughter cards attached. diff --git a/c/src/lib/libbsp/powerpc/ep1a/configure.ac b/c/src/lib/libbsp/powerpc/ep1a/configure.ac index 3bed523245..81167084d4 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/configure.ac +++ b/c/src/lib/libbsp/powerpc/ep1a/configure.ac @@ -15,6 +15,21 @@ RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm]) RTEMS_CANONICALIZE_TOOLS RTEMS_PROG_CCAS +RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[1]) +RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS], +[whether using console interrupts]) + +RTEMS_BSPOPTS_SET([INITIALIZE_COM_PORTS],[*],[0]) +RTEMS_BSPOPTS_HELP([INITIALIZE_COM_PORTS], +[FIXME: Missing explanation]) + +RTEMS_BSPOPTS_SET([PPC_USE_SPRG],[*],[0]) +RTEMS_BSPOPTS_HELP([PPC_USE_SPRG], +[If defined, then the PowerPC specific code in RTEMS will use some +of the special purpose registers to slightly optimize interrupt +response time. The use of these registers can conflict with +other tools like debuggers.]) + RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[0]) RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE], [If defined, then the PowerPC specific code in RTEMS will use @@ -24,14 +39,10 @@ RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE], of PowerPC 603e revisions and emulator versions. The BSP actually contains the call that enables this.]) -RTEMS_BSPOPTS_SET([INSTRUCTION_CACHE_ENABLE],[*],[0]) -RTEMS_BSPOPTS_HELP([INSTRUCTION_CACHE_ENABLE], -[If defined, the instruction cache will be enabled after address translation - is turned on.]) - -RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[0]) -RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS], -[whether using console interrupts]) +RTEMS_BSPOPTS_SET([PPC_VECTOR_FILE_BASE],[*],[0x0100]) +RTEMS_BSPOPTS_HELP([PPC_VECTOR_FILE_BASE], +[This defines the base address of the exception table. + NOTE: Vectors are actually at 0xFFF00000 but file starts at offset.]) RTEMS_CHECK_NETWORKING AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes") diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/alloc360.c b/c/src/lib/libbsp/powerpc/ep1a/console/alloc360.c index 0d1b31b729..8db8a67ed3 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/console/alloc360.c +++ b/c/src/lib/libbsp/powerpc/ep1a/console/alloc360.c @@ -34,23 +34,40 @@ void M360SetupMemory( M68360_t ptr ){ #if DEBUG_PRINT printk("m360->mcr:0x%08x Q1_360_SIM_MCR:0x%08x\n", - (unsigned int)&(m360->mcr), ((unsigned int)m360+Q1_360_SIM_MCR)); + (uint32_t)&(m360->mcr), ((uint32_t)m360+Q1_360_SIM_MCR)); #endif - ptr->bdregions[0].base = (char *)&m360->dpram1[0]; + ptr->bdregions[0].base = (uint8_t *)&m360->dpram1[0]; ptr->bdregions[0].size = sizeof m360->dpram1; ptr->bdregions[0].used = 0; +#if DEBUG_PRINT +printk("%d) base 0x%x size %d used %d\n", 0, + (uint32_t)ptr->bdregions[0].base, ptr->bdregions[0].size, ptr->bdregions[0].used ); +#endif - ptr->bdregions[1].base = (char *)&m360->dpram3[0]; + ptr->bdregions[1].base = (uint8_t *)&m360->dpram3[0]; ptr->bdregions[1].size = sizeof m360->dpram3; ptr->bdregions[1].used = 0; +#if DEBUG_PRINT +printk("%d) base 0x%x size %d used %d\n", 1, + (uint32_t)ptr->bdregions[1].base, ptr->bdregions[1].size, ptr->bdregions[1].used ); +#endif - ptr->bdregions[2].base = (char *)&m360->dpram0[0]; + ptr->bdregions[2].base = (uint8_t *)&m360->dpram0[0]; ptr->bdregions[2].size = sizeof m360->dpram0; ptr->bdregions[2].used = 0; +#if DEBUG_PRINT +printk("%d) base 0x%x size %d used %d\n", 2, + (uint32_t)ptr->bdregions[2].base, ptr->bdregions[2].size, ptr->bdregions[2].used ); +#endif - ptr->bdregions[3].base = (char *)&m360->dpram2[0]; + ptr->bdregions[3].base = (uint8_t *)&m360->dpram2[0]; ptr->bdregions[3].size = sizeof m360->dpram2; ptr->bdregions[3].used = 0; +#if DEBUG_PRINT +printk("%d) base 0x%x size %d used %d\n", 3, + (uint32_t)ptr->bdregions[3].base, ptr->bdregions[3].size, ptr->bdregions[3].used ); +#endif + } @@ -60,11 +77,11 @@ printk("m360->mcr:0x%08x Q1_360_SIM_MCR:0x%08x\n", void * M360AllocateBufferDescriptors (M68360_t ptr, int count) { - unsigned int i; + uint32_t i; ISR_Level level; void *bdp = NULL; - unsigned int want = count * sizeof(m360BufferDescriptor_t); - int have; + uint32_t want = count * sizeof(m360BufferDescriptor_t); + uint32_t have; /* * Running with interrupts disabled is usually considered bad @@ -81,15 +98,27 @@ M360AllocateBufferDescriptors (M68360_t ptr, int count) * less dual-port RAM. */ if (ptr->bdregions[i].used == 0) { - volatile unsigned char *cp = ptr->bdregions[i].base; + volatile uint8_t *cp = ptr->bdregions[i].base; + uint8_t data; + *cp = 0xAA; - if (*cp != 0xAA) { + data = *cp; + if (data != 0xAA) { ptr->bdregions[i].used = ptr->bdregions[i].size; +#if DEBUG_PRINT +printk("%d) base 0x%x used %d expected 0xAA read 0x%x\n",i, + (uint32_t)ptr->bdregions[i].base, ptr->bdregions[0].used, data ); +#endif continue; } *cp = 0x55; - if (*cp != 0x55) { + data = *cp; + if (data != 0x55) { ptr->bdregions[i].used = ptr->bdregions[i].size; +#if DEBUG_PRINT +printk("%d) base 0x%x used %d expected 0x55 read 0x%x\n",i, + (uint32_t)ptr->bdregions[i].base, ptr->bdregions[0].used, data ); +#endif continue; } *cp = 0x0; diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/config.c b/c/src/lib/libbsp/powerpc/ep1a/console/config.c index 923f9f8ef5..a33bdc7279 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/console/config.c +++ b/c/src/lib/libbsp/powerpc/ep1a/console/config.c @@ -1,7 +1,7 @@ /* * This file contains the TTY driver table for the EP1A * - * COPYRIGHT (c) 1989-1999. + * COPYRIGHT (c) 1989-2009. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -21,7 +21,12 @@ * or interrupt driven IO. */ +#if 1 #define NS16550_FUNCTIONS &ns16550_fns_polled +#else +#define NS16550_FUNCTIONS &ns16550_fns +#endif + #define MC68360_SCC_FUNCTIONS &mc68360_scc_fns /* @@ -122,6 +127,7 @@ console_tbl Console_Port_Tbl[] = { 7372800, /* ulClock */ 0 /* ulIntVector */ }, + /* * Up to 12 serial ports are provided by MC68360 SCC ports. * EP1A may have one MC68360 providing 4 ports (A,B,C,D). @@ -431,3 +437,8 @@ static bool config_68360_scc_base_probe_12( int minor ) { return config_68360_scc_base_probe( minor, 0, 15, 4); } + +void Force_mc8360_interrupt( int d ) { + mc68360_sccInterruptHandler( M68360_chips->next ); +} + diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/console.c b/c/src/lib/libbsp/powerpc/ep1a/console/console.c index 8c0367c7f6..6cb81a5938 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/console/console.c +++ b/c/src/lib/libbsp/powerpc/ep1a/console/console.c @@ -1,4 +1,4 @@ -/*XXX +/* * This file contains the TTY driver for the ep1a * * This driver uses the termios pseudo driver. @@ -212,6 +212,11 @@ rtems_device_driver console_initialize( Console_Port_Tbl[minor].pDeviceFns->deviceInitialize( Console_Port_Minor); + /* + * NOTE: We must probe ALL possible devices, which initializes + * the address information in the config.c tables. + */ + for(minor++;minor<Console_Port_Count;minor++) { /* @@ -241,83 +246,6 @@ rtems_device_driver console_initialize( return RTEMS_SUCCESSFUL; } -#if 0 -/* PAGE - * - * DEBUG_puts - * - * This should be safe in the event of an error. It attempts to ensure - * that no TX empty interrupts occur while it is doing polled IO. Then - * it restores the state of that external interrupt. - * - * Input parameters: - * string - pointer to debug output string - * - * Output parameters: NONE - * - * Return values: NONE - */ - -void DEBUG_puts( - char *string -) -{ - char *s; - unsigned32 Irql; - - rtems_interrupt_disable(Irql); - - for ( s = string ; *s ; s++ ) - { - Console_Port_Tbl[Console_Port_Minor].pDeviceFns-> - deviceWritePolled(Console_Port_Minor, *s); - } - - rtems_interrupt_enable(Irql); -} - -/* PAGE - * - * DEBUG_puth - * - * This should be safe in the event of an error. It attempts to ensure - * that no TX empty interrupts occur while it is doing polled IO. Then - * it restores the state of that external interrupt. - * - * Input parameters: - * ulHexNum - value to display - * - * Output parameters: NONE - * - * Return values: NONE - */ -void -DEBUG_puth( - unsigned32 ulHexNum - ) -{ - unsigned long i,d; - unsigned32 Irql; - - rtems_interrupt_disable(Irql); - - Console_Port_Tbl[Console_Port_Minor].pDeviceFns-> - deviceWritePolled(Console_Port_Minor, '0'); - Console_Port_Tbl[Console_Port_Minor].pDeviceFns-> - deviceWritePolled(Console_Port_Minor, 'x'); - - for(i=32;i;) - { - i-=4; - d=(ulHexNum>>i)&0xf; - Console_Port_Tbl[Console_Port_Minor].pDeviceFns-> - deviceWritePolled(Console_Port_Minor, - (d<=9) ? d+'0' : d+'a'-0xa); - } - - rtems_interrupt_enable(Irql); -} -#endif /* const char arg to be compatible with BSP_output_char decl. */ void diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/m68360.h b/c/src/lib/libbsp/powerpc/ep1a/console/m68360.h index c1077f482e..b3f37f4c00 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/console/m68360.h +++ b/c/src/lib/libbsp/powerpc/ep1a/console/m68360.h @@ -16,7 +16,7 @@ * eric@skatter.usask.ca * * - * COPYRIGHT (c) 1989-1999. + * COPYRIGHT (c) 1989-2009. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -935,9 +935,9 @@ typedef struct m360_ { } m360_t; struct bdregions_t { - char *base; - unsigned int size; - unsigned int used; + uint8_t *base; + uint32_t size; + uint32_t used; }; #define M68360_RX_BUF_SIZE 1 @@ -977,6 +977,8 @@ void *M360AllocateBufferDescriptors (M68360_t ptr, int count); void M360ExecuteRISC( volatile m360_t *m360, uint16_t command); int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector ); +void mc68360_sccInterruptHandler( void *ptr); + #if 0 extern volatile m360_t *m360; #endif diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/mc68360_scc.c b/c/src/lib/libbsp/powerpc/ep1a/console/mc68360_scc.c index 975e9a6104..532da1875d 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/console/mc68360_scc.c +++ b/c/src/lib/libbsp/powerpc/ep1a/console/mc68360_scc.c @@ -1,7 +1,7 @@ /* This file contains the termios TTY driver for the * Motorola MC68360 SCC ports. * - * COPYRIGHT (c) 1989-2008. + * COPYRIGHT (c) 1989-2009. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -25,7 +25,7 @@ #include <rtems/bspIo.h> #include <string.h> -#if 0 +#if 0 #define DEBUG_360 #endif @@ -77,10 +77,10 @@ void scc_write8( uint8_t value ) { + *address = value; #ifdef DEBUG_360 printk( "WR8 %s 0x%08x 0x%02x\n", name, address, value ); #endif - *address = value; } @@ -108,10 +108,10 @@ void scc_write16( uint16_t value ) { + *address = value; #ifdef DEBUG_360 printk( "WR16 %s 0x%08x 0x%04x\n", name, address, value ); #endif - *address = value; } @@ -139,10 +139,11 @@ void scc_write32( uint32_t value ) { + *address = value; + Processor_Synchronize(); #ifdef DEBUG_360 printk( "WR32 %s 0x%08x 0x%08x\n", name, address, value ); #endif - *address = value; } void mc68360_sccShow_Regs(int minor){ @@ -155,9 +156,9 @@ void mc68360_sccShow_Regs(int minor){ } #define TX_BUFFER_ADDRESS( _ptr ) \ - ((char *)ptr->txBuf - (char *)ptr->chip->board_data->baseaddr) + ((uint8_t *)ptr->txBuf - (uint8_t *)ptr->chip->board_data->baseaddr) #define RX_BUFFER_ADDRESS( _ptr ) \ - ((char *)ptr->rxBuf - (char *)ptr->chip->board_data->baseaddr) + ((uint8_t *)ptr->rxBuf - (uint8_t *)ptr->chip->board_data->baseaddr) /************************************************************************** @@ -239,8 +240,9 @@ mc68360_sccBRGC(int baud, int m360_clock_rate) * none * * * **************************************************************************/ -void mc68360_sccInterruptHandler( M68360_t chip ) +void mc68360_sccInterruptHandler( void *ptr) { + M68360_t chip = ptr; volatile m360_t *m360; int port; uint16_t status; @@ -250,8 +252,8 @@ void mc68360_sccInterruptHandler( M68360_t chip ) int clear_isr; -#ifdef DEBUG_360 - printk("mc68360_sccInterruptHandler\n"); +#ifdef DEBUG_360 + printk("mc68360_sccInterruptHandler with 0x%x \n", ptr); #endif for (port=0; port<4; port++) { @@ -275,8 +277,8 @@ void mc68360_sccInterruptHandler( M68360_t chip ) while ((status & M360_BD_EMPTY) == 0) { length= scc_read16("sccRxBd->length",&chip->port[port].sccRxBd->length); -if (length > 1) - EP1A_READ_LENGTH_GREATER_THAN_1 = length; + if (length > 1) + EP1A_READ_LENGTH_GREATER_THAN_1 = length; for (i=0;i<length;i++) { data= chip->port[port].rxBuf[i]; @@ -302,21 +304,19 @@ if (length > 1) if ((status & M360_BD_EMPTY) == 0) { scc_write16("sccTxBd->status",&chip->port[port].sccTxBd->status,0); -#if 1 rtems_termios_dequeue_characters( Console_Port_Data[chip->port[port].minor].termios_data, - chip->port[port].sccTxBd->length); -#else - mc68360_scc_write_support_int(chip->port[port].minor,"*****", 5); -#endif + chip->port[port].sccTxBd->length + ); } } /* * Clear SCC interrupt-in-service bit. */ - if ( clear_isr ) + if ( clear_isr ) { scc_write32( "cisr", &m360->cisr, (0x80000000 >> chip->port[port].channel) ); + } } } @@ -339,10 +339,9 @@ int mc68360_scc_open( uint32_t data; #ifdef DEBUG_360 - printk("mc68360_scc_open %d\n", minor); + printk("mc68360_scc_open %s (%d)\n", Console_Port_Tbl[minor].sDeviceName, minor); #endif - ptr = Console_Port_Tbl[minor].pDeviceParams; m360 = ptr->chip->m360; @@ -368,8 +367,8 @@ int mc68360_scc_open( uint32_t mc68360_scc_calculate_pbdat( M68360_t chip ) { - uint32_t i; - uint32_t pbdat_data; + int i; + uint32_t pbdat_data = 0x03; int minor; uint32_t type422data[4] = { 0x00440, 0x00880, 0x10100, 0x20200 @@ -378,13 +377,15 @@ uint32_t mc68360_scc_calculate_pbdat( M68360_t chip ) pbdat_data = 0x3; for (i=0; i<4; i++) { minor = chip->port[i].minor; - if mc68360_scc_Is_422( minor ) + if mc68360_scc_Is_422( minor ){ pbdat_data |= type422data[i]; + } } return pbdat_data; } + /* * mc68360_scc_initialize_interrupts * @@ -400,7 +401,7 @@ void mc68360_scc_initialize_interrupts(int minor) uint32_t buffers_start; uint32_t tmp_u32; -#ifdef DEBUG_360 +#ifdef DEBUG_360 printk("mc68360_scc_initialize_interrupts: minor %d\n", minor ); printk("Console_Port_Tbl[minor].pDeviceParams 0x%08x\n", Console_Port_Tbl[minor].pDeviceParams ); @@ -409,7 +410,7 @@ void mc68360_scc_initialize_interrupts(int minor) ptr = Console_Port_Tbl[minor].pDeviceParams; m360 = ptr->chip->m360; -#ifdef DEBUG_360 +#ifdef DEBUG_360 printk("m360 0x%08x baseaddr 0x%08x\n", m360, ptr->chip->board_data->baseaddr); #endif @@ -464,6 +465,7 @@ void mc68360_scc_initialize_interrupts(int minor) /* * XXX */ + scc_write16( "papar", &m360->papar, 0xffff ); scc_write16( "padir", &m360->padir, 0x5500 ); /* From Memo */ scc_write16( "paodr", &m360->paodr, 0x0000 ); @@ -664,6 +666,11 @@ int mc68360_scc_write_support_int( rtems_interrupt_level Irql; M68360_serial_ports_t ptr; +#ifdef DEBUG_360 + printk("mc68360_scc_write_support_int: char 0x%x length %d\n", + (unsigned int)*buf, len ); +#endif + #if 1 mc68360_length_array[ mc68360_length_count ] = len; mc68360_length_count++; @@ -682,17 +689,12 @@ int mc68360_scc_write_support_int( return 0; /* - * - */ -#ifdef DEBUG_360 - printk("mc68360_scc_write_support_int: char 0x%x length %d\n", - (unsigned int)*buf, len ); -#endif - /* * We must copy the data from the global memory space to MC68360 space */ - rtems_interrupt_disable(Irql); +#ifdef DEBUG_360 + printk("mc68360_scc_write_support_int: disable irq 0x%x\n", Irql ); +#endif scc_write16( "sccTxBd->status", &ptr->sccTxBd->status, 0 ); memcpy((void *) ptr->txBuf, buf, len); @@ -702,6 +704,9 @@ int mc68360_scc_write_support_int( scc_write16( "sccTxBd->status", &ptr->sccTxBd->status, (M360_BD_READY | M360_BD_WRAP | M360_BD_INTERRUPT) ); +#ifdef DEBUG_360 + printk("mc68360_scc_write_support_int: enable irq 0x%x\n", Irql ); +#endif rtems_interrupt_enable(Irql); return len; @@ -897,12 +902,14 @@ int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector ) * XXX - Note Does this need to be moved up to if a QUICC is fitted * section? */ - if ((chip = malloc(sizeof(struct _m68360_per_chip))) == NULL) + + if ((chip = calloc( 1, sizeof(struct _m68360_per_chip))) == NULL) { printk("Error Unable to allocate memory for _m68360_per_chip\n"); return RTEMS_IO_ERROR; + } else { + printk("Allocate memory for _m68360_per_chip at 0x%x\n", chip ); } - chip->next = M68360_chips; chip->m360 = (void *)BoardData->baseaddr; chip->m360_interrupt = int_vector; @@ -945,7 +952,6 @@ int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector ) /* * Allocate buffer descriptors. */ - chip->port[i-1].sccRxBd = M360AllocateBufferDescriptors(chip, 1); chip->port[i-1].sccTxBd = M360AllocateBufferDescriptors(chip, 1); } @@ -957,7 +963,6 @@ int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector ) &mc68360_sccInterruptHandler, chip ); - return RTEMS_SUCCESSFUL; } diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c b/c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c index 764ab53eb1..c8f9b1c48d 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c +++ b/c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c @@ -27,7 +27,7 @@ These functions are responsible for scanning for PMCQ1's and setting up the Motorola MC68360's if present. USAGE -call rsPMCQ1Init() to perform ba sic initialisation of the PMCQ1's. +call rsPMCQ1Init() to perform basic initialisation of the PMCQ1's. */ /* includes */ @@ -41,8 +41,8 @@ call rsPMCQ1Init() to perform ba sic initialisation of the PMCQ1's. #include "m68360.h" /* defines */ -#if 1 -#define DEBUG_360 +#if 0 +#define DEBUG_360 TRUE #endif /* Local data */ @@ -82,27 +82,61 @@ static unsigned char rsPMCQ1eeprom[] = void MsDelay(void) { - printk("."); + printk(".."); } void write8( int addr, int data ){ - out_8((void *)addr, (unsigned char)data); + out_8((volatile void *)addr, (unsigned char)data); + Processor_Synchronize(); } void write16( int addr, int data ) { - out_be16((void *)addr, (short)data ); + out_be16((volatile void *)addr, (short)data ); + Processor_Synchronize(); } void write32( int addr, int data ) { - out_be32((unsigned int *)addr, data ); + out_be32((volatile unsigned int *)addr, data ); + Processor_Synchronize(); } int read32( int addr){ - return in_be32((unsigned int *)addr); + int value = in_be32((volatile unsigned int *)addr); + Processor_Synchronize(); + return value; } +void rsPMCQ1_scc_On(const struct __rtems_irq_connect_data__ *ptr) +{ + +} + +void rsPMCQ1_scc_Off(const struct __rtems_irq_connect_data__ *ptr) +{ + +} + +int rsPMCQ1_scc_except_always_enabled(const struct __rtems_irq_connect_data__ *ptr) +{ + return TRUE; +} + + +void rsPMCQ1ShowIntrStatus(void ) +{ + unsigned long status; + unsigned long mask; + PPMCQ1BoardData boardData; + + for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext) + { + + status = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS ); + mask = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_MASK ); + printk("rsPMCQ1ShowIntrStatus: interrupt status 0x%x) 0x%x with mask: 0x%x\n", boardData->quiccInt, status, mask); + } +} -void rsPMCQ1_scc_nullFunc(void) {} /******************************************************************************* * rsPMCQ1Int - handle a PMCQ1 interrupt @@ -116,48 +150,57 @@ void rsPMCQ1_scc_nullFunc(void) {} void rsPMCQ1Int( void *ptr ) { unsigned long status; - unsigned long status1; + static unsigned long status1; unsigned long mask; uint32_t data; PPMCQ1BoardData boardData = ptr; + volatile unsigned long *hrdwr; + unsigned long value; status = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS ); mask = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_MASK ); - if (((mask & PMCQ1_INT_MASK_QUICC) == 0) && (status & PMCQ1_INT_STATUS_QUICC)) + + if (((mask & PMCQ1_INT_MASK_QUICC) == 0) && ((status & PMCQ1_INT_STATUS_QUICC) != 0 )) { /* If there is a handler call it otherwise mask the interrupt */ if (boardData->quiccInt) { boardData->quiccInt(boardData->quiccArg); } else { - *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC; + printk("No handler - Masking interrupt\n"); + hrdwr = (volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK); + value = (*hrdwr) | PMCQ1_INT_MASK_QUICC; + *hrdwr = value; } } if (((mask & PMCQ1_INT_MASK_MA) == 0) && (status & PMCQ1_INT_STATUS_MA)) { + /* If there is a handler call it otherwise mask the interrupt */ if (boardData->maInt) { boardData->maInt(boardData->maArg); - data = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS ); - data &= (~PMCQ1_INT_STATUS_MA); + data = data & (~PMCQ1_INT_STATUS_MA); PMCQ1_Write_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS, data ); - - } else { - *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA; + } else { + printk("No handler - Masking interrupt\n"); + hrdwr = (volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK); + value = (*hrdwr) | PMCQ1_INT_MASK_MA; + *hrdwr = value; } } RTEMS_COMPILER_MEMORY_BARRIER(); /* Clear Interrupt on QSPAN */ - *(volatile unsigned long *)(boardData->bridgeaddr + 0x600) = 0x00001000; + hrdwr = (volatile unsigned long *)(boardData->bridgeaddr + 0x600); + *hrdwr = 0x00001000; /* read back the status register to ensure that the pci write has completed */ - status1 = *(volatile unsigned long *)(boardData->bridgeaddr + 0x600); - RTEMS_COMPILER_MEMORY_BARRIER(); + status1 = *hrdwr; + RTEMS_COMPILER_MEMORY_BARRIER(); } @@ -175,8 +218,8 @@ unsigned int rsPMCQ1MaIntConnect ( unsigned long busNo, /* Pci Bus number of PMCQ1 */ unsigned long slotNo, /* Pci Slot number of PMCQ1 */ unsigned long funcNo, /* Pci Function number of PMCQ1 */ - FUNCION_PTR routine,/* interrupt routine */ - int arg /* argument to pass to interrupt routine */ + PMCQ1_FUNCTION_PTR routine,/* interrupt routine */ + void * arg /* argument to pass to interrupt routine */ ) { PPMCQ1BoardData boardData; @@ -231,7 +274,7 @@ unsigned int rsPMCQ1MaIntDisconnect( (boardData->funcNo == funcNo)) { boardData->maInt = NULL; - *(unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA; + *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA; status = RTEMS_SUCCESSFUL; break; } @@ -251,11 +294,11 @@ unsigned int rsPMCQ1MaIntDisconnect( */ unsigned int rsPMCQ1QuiccIntConnect( - unsigned long busNo, /* Pci Bus number of PMCQ1 */ - unsigned long slotNo, /* Pci Slot number of PMCQ1 */ - unsigned long funcNo, /* Pci Function number of PMCQ1 */ - FUNCION_PTR routine,/* interrupt routine */ - int arg /* argument to pass to interrupt routine */ + unsigned long busNo, /* Pci Bus number of PMCQ1 */ + unsigned long slotNo, /* Pci Slot number of PMCQ1 */ + unsigned long funcNo, /* Pci Function number of PMCQ1 */ + PMCQ1_FUNCTION_PTR routine, /* interrupt routine */ + void * arg /* argument to pass to interrupt routine */ ) { PPMCQ1BoardData boardData; @@ -300,7 +343,7 @@ unsigned int rsPMCQ1QuiccIntDisconnect( (boardData->funcNo == funcNo)) { boardData->quiccInt = NULL; - *(unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC; + *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC; status = RTEMS_SUCCESSFUL; break; } @@ -323,25 +366,22 @@ unsigned int rsPMCQ1Init(void) { int busNo; int slotNo; - unsigned int baseaddr = 0; - unsigned int bridgeaddr = 0; + uint32_t baseaddr = 0; + uint32_t bridgeaddr = 0; unsigned long pbti0_ctl; int i; unsigned char int_vector; int fun; - int temp; + uint32_t temp; PPMCQ1BoardData boardData; - rtems_irq_connect_data IrqData = {0, - rsPMCQ1Int, - rsPMCQ1_scc_nullFunc, - rsPMCQ1_scc_nullFunc, - rsPMCQ1_scc_nullFunc, - NULL}; + rtems_irq_connect_data *IrqData = NULL; if (rsPMCQ1Initialized) { + printk("rsPMCQ1Init: Already Initialized\n"); return RTEMS_SUCCESSFUL; - } + } + for (i=0;;i++){ if ( pci_find_device(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1, i, &busNo, &slotNo, &fun) != 0 ) break; @@ -349,17 +389,17 @@ unsigned int rsPMCQ1Init(void) pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_2, &baseaddr); pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_0, &bridgeaddr); #ifdef DEBUG_360 - printk("PMCQ1 baseaddr 0x%08x bridgeaddr 0x%08x\n", baseaddr, bridgeaddr ); + printk("rsPMCQ1Init: PMCQ1 baseaddr 0x%08x bridgeaddr 0x%08x\n", baseaddr, bridgeaddr ); #endif /* Set function code to normal mode and enable window */ - pbti0_ctl = *(unsigned long *)(bridgeaddr + 0x100) & 0xff0fffff; + pbti0_ctl = (*(unsigned long *)(bridgeaddr + 0x100)) & 0xff0fffff; eieio(); - *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080; + *(volatile unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080; eieio(); /* Assert QBUS reset */ - *(unsigned long *)(bridgeaddr + 0x800) |= 0x00000080; + *(volatile unsigned long *)(bridgeaddr + 0x800) |= 0x00000080; eieio(); /* @@ -368,7 +408,7 @@ unsigned int rsPMCQ1Init(void) MsDelay(); /* Take QBUS out of reset */ - *(unsigned long *)(bridgeaddr + 0x800) &= ~0x00000080; + *(volatile unsigned long *)(bridgeaddr + 0x800) &= ~0x00000080; eieio(); MsDelay(); @@ -377,19 +417,19 @@ unsigned int rsPMCQ1Init(void) if (PMCQ1_Read_EPLD(baseaddr, PMCQ1_BUILD_OPTION) & PMCQ1_QUICC_FITTED) { #ifdef DEBUG_360 - printk(" Found QUICC busNo %d slotNo %d\n", busNo, slotNo); + printk("rsPMCQ1Init: Found QUICC busNo %d slotNo %d\n", busNo, slotNo); #endif /* Initialise MBAR (must use function code of 7) */ - *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00700080; + *(volatile unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00700080; eieio(); /* place internal 8K SRAM and registers at address 0x0 */ - *(unsigned long *)(baseaddr + Q1_360_MBAR) = 0x1; + *(volatile unsigned long *)(baseaddr + Q1_360_MBAR) = 0x1; eieio(); /* Set function code to normal mode */ - *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080; + *(volatile unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080; eieio(); /* Disable the SWT and perform basic initialisation */ @@ -425,15 +465,15 @@ unsigned int rsPMCQ1Init(void) */ pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_3, &temp); if (temp) { - *(unsigned long *)(bridgeaddr + 0x110) |= 0x00500880; + *(volatile unsigned long *)(bridgeaddr + 0x110) |= 0x00500880; } /* * Create descriptor structure for this card */ - if ((boardData = malloc(sizeof(struct _PMCQ1BoardData))) == NULL) + if ((boardData = calloc(1, sizeof(struct _PMCQ1BoardData))) == NULL) { - printk("Error Unable to allocate memory for _PMCQ1BoardData\n"); + printk("rsPMCQ1Init: Error Unable to allocate memory for _PMCQ1BoardData\n"); return(RTEMS_IO_ERROR); } @@ -446,6 +486,7 @@ unsigned int rsPMCQ1Init(void) boardData->quiccInt = NULL; boardData->maInt = NULL; pmcq1BoardData = boardData; + mc68360_scc_create_chip( boardData, int_vector ); /* @@ -453,11 +494,22 @@ unsigned int rsPMCQ1Init(void) */ pci_read_config_byte(busNo, slotNo, 0, 0x3c, &int_vector); #ifdef DEBUG_360 - printk("PMCQ1 int_vector %d\n", int_vector); + printk("rsPMCQ1Init: PMCQ1 int_vector %d\n", int_vector); #endif - IrqData.name = ((unsigned int)BSP_PCI_IRQ0 + int_vector); - IrqData.handle = boardData; - if (!BSP_install_rtems_shared_irq_handler (&IrqData)) { + + if ((IrqData = calloc( 1, sizeof(rtems_irq_connect_data) )) == NULL ) + { + printk("rsPMCQ1Init: Error Unable to allocate memory for rtems_irq_connect_data\n"); + return(RTEMS_IO_ERROR); + } + IrqData->name = ((unsigned int)BSP_PCI_IRQ0 + int_vector); + IrqData->hdl = rsPMCQ1Int; + IrqData->handle = boardData; + IrqData->on = rsPMCQ1_scc_On; + IrqData->off = rsPMCQ1_scc_Off; + IrqData->isOn = rsPMCQ1_scc_except_always_enabled; + + if (!BSP_install_rtems_shared_irq_handler (IrqData)) { printk("Error installing interrupt handler!\n"); rtems_fatal_error_occurred(1); } @@ -465,11 +517,10 @@ unsigned int rsPMCQ1Init(void) /* * Enable PMCQ1 Interrupts from QSPAN-II */ - - *(unsigned long *)(bridgeaddr + 0x600) = 0x00001000; + *(volatile unsigned long *)(bridgeaddr + 0x600) = 0x00001000; eieio(); - *(unsigned long *)(bridgeaddr + 0x604) |= 0x00001000; - + Processor_Synchronize(); + *(volatile unsigned long *)(bridgeaddr + 0x604) |= 0x00001000; eieio(); } @@ -512,9 +563,9 @@ unsigned int rsPMCQ1Commission( unsigned long busNo, unsigned long slotNo ) * A real PMCQ1 also has the sub vendor ID set up. */ if ((busNo == 0) && (slotNo == 1)) { - *(unsigned long *)rsPMCQ1eeprom = 0; + *(volatile unsigned long *)rsPMCQ1eeprom = 0; } else { - *(unsigned long *)rsPMCQ1eeprom = PCI_ID(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1); + *(volatile unsigned long *)rsPMCQ1eeprom = PCI_ID(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1); } for (i = 0; i < 23; i++) { @@ -558,20 +609,27 @@ unsigned int rsPMCQ1Commission( unsigned long busNo, unsigned long slotNo ) uint32_t PMCQ1_Read_EPLD( uint32_t base, uint32_t reg ) { - uint32_t data; + uint32_t data; + volatile uint32_t *ptr; - data = ( *((unsigned long *) (base + reg)) ); + Processor_Synchronize(); + ptr = (volatile uint32_t *)(base + reg); + data = *ptr ; #ifdef DEBUG_360 - printk("EPLD Read 0x%x: 0x%08x\n", reg + base, data ); + printk("EPLD Read 0x%x: 0x%08x\n", ptr, data ); #endif return data; } void PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data ) { - *((unsigned long *) (base + reg)) = data; + volatile uint32_t *ptr; + + ptr = (volatile uint32_t *) (base + reg); + *ptr = data; + Processor_Synchronize(); #ifdef DEBUG_360 - printk("EPLD Write 0x%x: 0x%08x\n", reg+base, data ); + printk("EPLD Write 0x%x: 0x%08x\n", ptr, data ); #endif } diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.h b/c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.h index c6ba7d05bb..4032d5ecbe 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.h +++ b/c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.h @@ -30,8 +30,8 @@ 01a,20Dec00,jpb created */ -#ifndef __INCPMCQ1H -#define __INCPMCQ1H +#ifndef __RSPMCQ1_H +#define __RSPMCQ1_H /* * PMCQ1 definitions @@ -95,10 +95,6 @@ #define PMCQ1_MINIACE_MEM 0x00100000 #define PMCQ1_RAM 0x00200000 -/* -#define PMCQ1_Read_EPLD( _base, _reg ) ( *((unsigned long *) ((unsigned32)_base + _reg)) ) -#define PMCQ1_Write_EPLD( _base, _reg, _data ) *((unsigned long *) ((unsigned32)_base + _reg)) = _data -*/ uint32_t PMCQ1_Read_EPLD( uint32_t base, uint32_t reg ); void PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data ); @@ -108,7 +104,7 @@ void PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data ); #define QSPAN2_INT_STATUS 0x00000600 -typedef void (*FUNCION_PTR) (int); +typedef void (*PMCQ1_FUNCTION_PTR) (void *); #define PCI_ID(v, d) ((d << 16) | v) @@ -125,16 +121,16 @@ typedef void (*FUNCION_PTR) (int); typedef struct _PMCQ1BoardData { - struct _PMCQ1BoardData *pNext; - unsigned long busNo; - unsigned long slotNo; - unsigned long funcNo; - unsigned long baseaddr; - unsigned long bridgeaddr; - FUNCION_PTR quiccInt; - int quiccArg; - FUNCION_PTR maInt; - int maArg; + struct _PMCQ1BoardData *pNext; + unsigned long busNo; + unsigned long slotNo; + unsigned long funcNo; + unsigned long baseaddr; + unsigned long bridgeaddr; + PMCQ1_FUNCTION_PTR quiccInt; + void * quiccArg; + PMCQ1_FUNCTION_PTR maInt; + void * maArg; } PMCQ1BoardData, *PPMCQ1BoardData; extern PPMCQ1BoardData pmcq1BoardData; @@ -146,16 +142,18 @@ extern unsigned int rsPMCQ1QuiccIntConnect( unsigned long busNo, unsigned long slotNo, unsigned long funcNo, - FUNCION_PTR routine, - int arg + PMCQ1_FUNCTION_PTR routine, + void * arg ); unsigned int rsPMCQ1Init(); unsigned int rsPMCQ1MaIntConnect ( unsigned long busNo, /* Pci Bus number of PMCQ1 */ unsigned long slotNo, /* Pci Slot number of PMCQ1 */ unsigned long funcNo, /* Pci Function number of PMCQ1 */ - FUNCION_PTR routine,/* interrupt routine */ - int arg /* argument to pass to interrupt routine */ + PMCQ1_FUNCTION_PTR routine,/* interrupt routine */ + void * arg /* argument to pass to interrupt routine */ ); -#endif /* __INCPMCQ1H */ +void rsPMCQ1ShowIntrStatus(void ); + +#endif /* __RSPMCQ1_H */ diff --git a/c/src/lib/libbsp/powerpc/ep1a/include/bsp.h b/c/src/lib/libbsp/powerpc/ep1a/include/bsp.h index 96699dcfe3..be6b012007 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/ep1a/include/bsp.h @@ -1,6 +1,6 @@ /* * - * COPYRIGHT (c) 1989-1999. + * COPYRIGHT (c) 1989-2009. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -13,6 +13,9 @@ #ifndef _BSP_H #define _BSP_H + +#define BSP_ZERO_WORKSPACE_AUTOMATICALLY TRUE + #include <bspopts.h> #include <rtems.h> diff --git a/c/src/lib/libbsp/powerpc/ep1a/irq/irq.h b/c/src/lib/libbsp/powerpc/ep1a/irq/irq.h new file mode 100644 index 0000000000..1c0d225ccd --- /dev/null +++ b/c/src/lib/libbsp/powerpc/ep1a/irq/irq.h @@ -0,0 +1,110 @@ +/* + * + * This include file describe the data structure and the functions implemented + * by RTEMS to write interrupt handlers. + * + * Copyright (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * <http://www.chorus.com/Documentation/index.html> by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef BSP_POWERPC_IRQ_H +#define BSP_POWERPC_IRQ_H + +#define BSP_SHARED_HANDLER_SUPPORT 1 +#include <rtems/irq.h> + +/* PIC's command and mask registers */ +#define PIC_MASTER_COMMAND_IO_PORT 0x20 /* Master PIC command register */ +#define PIC_SLAVE_COMMAND_IO_PORT 0xa0 /* Slave PIC command register */ +#define PIC_MASTER_IMR_IO_PORT 0x21 /* Master PIC Interrupt Mask Register */ +#define PIC_SLAVE_IMR_IO_PORT 0xa1 /* Slave PIC Interrupt Mask Register */ + +/* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */ +#define PIC_EOSI 0x60 /* End of Specific Interrupt (EOSI) */ +#define SLAVE_PIC_EOSI 0x62 /* End of Specific Interrupt (EOSI) for cascade */ +#define PIC_EOI 0x20 /* Generic End of Interrupt (EOI) */ + +#ifndef ASM +#ifdef __cplusplus +extern "C" { +#endif + +/* + * rtems_irq_number Definitions + */ + +/* + * ISA IRQ handler related definitions + */ +#define BSP_ISA_IRQ_NUMBER (16) +#define BSP_ISA_IRQ_LOWEST_OFFSET (0) +#define BSP_ISA_IRQ_MAX_OFFSET \ + (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1) +/* + * PCI IRQ handlers related definitions + * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE + */ +#define BSP_PCI_IRQ_NUMBER (26) +#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER) +#define BSP_PCI_IRQ_MAX_OFFSET \ + (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) + +/* + * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt + * handler might be connected + */ +#define BSP_PROCESSOR_IRQ_NUMBER (1) +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET \ + (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) +/* + * Misc vectors for OPENPIC irqs (IPI, timers) + */ +#define BSP_MISC_IRQ_NUMBER (8) +#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1) +#define BSP_MISC_IRQ_MAX_OFFSET \ + (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) +/* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) +#define BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET) +#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) + + +/* + * Some PCI IRQ symbolic name definition + */ +#define BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET) + +/* + * Some Processor execption handled as RTEMS IRQ symbolic name definition + */ +#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) + +/* + * Type definition for RTEMS managed interrupts + */ +typedef unsigned short rtems_i8259_masks; +extern volatile rtems_i8259_masks i8259s_cache; + +/* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */ +#include <bsp/irq_supp.h> + +#ifdef __cplusplus +}; +#endif + +#endif +#endif diff --git a/c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c b/c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c index b9ed2ccc47..d45e6ded12 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c +++ b/c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c @@ -5,13 +5,13 @@ * * CopyRight (C) 1999 valette@crf.canon.fr * - * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com> - * to make it valid for MVME2300 Motorola boards. + * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com> + * to make it valid for MVME2300 Motorola boards. * - * Till Straumann <strauman@slac.stanford.edu>, 12/20/2001: - * Use the new interface to openpic_init + * Till Straumann <strauman@slac.stanford.edu>, 12/20/2001: + * Use the new interface to openpic_init * - * COPYRIGHT (c) 1989-1999. + * COPYRIGHT (c) 1989-2009. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -32,74 +32,91 @@ #include <bsp/motorola.h> #include <rtems/bspIo.h> -/* -#define SHOW_ISA_PCI_BRIDGE_SETTINGS -*/ -#define TRACE_IRQ_INIT +#if 0 +#define TRACE_IRQ_INIT 1 /* XXX */ +#endif -/* - * default on/off function - */ -static void nop_func(void){} -/* - * default isOn function - */ -static int not_connected(void) {return 0;} -/* - * default possible isOn function - */ -static int connected(void) {return 1;} +typedef struct { + unsigned char bus; /* few chance the PCI/ISA bridge is not on first bus but ... */ + unsigned char device; + unsigned char function; +} pci_isa_bridge_device; +pci_isa_bridge_device* via_82c586 = 0; +#if 0 +static pci_isa_bridge_device bridge; +#endif + + + +extern unsigned int external_exception_vector_prolog_code_size[]; +extern void external_exception_vector_prolog_code(); +extern unsigned int decrementer_exception_vector_prolog_code_size[]; +extern void decrementer_exception_vector_prolog_code(); + + +static void IRQ_Default_rtems_irq_hdl( rtems_irq_hdl_param ptr ) { printk("IRQ_Default_rtems_irq_hdl\n"); } +static void IRQ_Default_rtems_irq_enable (const struct __rtems_irq_connect_data__ *ptr) {} +static void IRQ_Default_rtems_irq_disable(const struct __rtems_irq_connect_data__ *ptr) {} +static int IRQ_Default_rtems_irq_is_enabled(const struct __rtems_irq_connect_data__ *ptr){ return 1; } static rtems_irq_connect_data rtemsIrq[BSP_IRQ_NUMBER]; static rtems_irq_global_settings initial_config; static rtems_irq_connect_data defaultIrq = { - /* vectorIdex, hdl , handle , on , off , isOn */ - 0, nop_func , NULL , nop_func , nop_func , not_connected +/*name, hdl handle on off isOn */ + 0, IRQ_Default_rtems_irq_hdl, NULL, IRQ_Default_rtems_irq_enable, IRQ_Default_rtems_irq_disable, IRQ_Default_rtems_irq_is_enabled }; + + +/* + * If the BSP_IRQ_NUMBER changes the following if will force the tables to be corrected. + */ +#if ( (BSP_ISA_IRQ_NUMBER == 16) && \ + (BSP_PCI_IRQ_NUMBER == 26) && \ + (BSP_PROCESSOR_IRQ_NUMBER == 1) && \ + (BSP_MISC_IRQ_NUMBER == 8) ) + + static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={ /* - * actual rpiorities for interrupt : - * 0 means that only current interrupt is masked - * 255 means all other interrupts are masked - */ - /* * ISA interrupts. - * The second entry has a priority of 255 because - * it is the slave pic entry and is should always remain - * unmasked. */ - 0,0, - 255, + 0, 0, + (OPENPIC_NUM_PRI-1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* * PCI Interrupts */ - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */ + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + /* * Processor exceptions handled as interrupts */ - 0 + 8, + + 8, 8, 8, 8, 8, 8, 8, 8 }; -static unsigned char mcp750_openpic_initpolarities[] = { +static unsigned char mpc8245_openpic_initpolarities[] = { 1, /* 0 8259 cascade */ - 0, /* 1 all the rest of them */ - 0, /* 2 all the rest of them */ - 0, /* 3 all the rest of them */ - 0, /* 4 all the rest of them */ - 0, /* 5 all the rest of them */ - 0, /* 6 all the rest of them */ - 0, /* 7 all the rest of them */ - 0, /* 8 all the rest of them */ - 0, /* 9 all the rest of them */ - 0, /* 10 all the rest of them */ - 0, /* 11 all the rest of them */ - 0, /* 12 all the rest of them */ - 0, /* 13 all the rest of them */ - 0, /* 14 all the rest of them */ - 0, /* 15 all the rest of them */ - 0, /* 16 all the rest of them */ - 0, /* 17 all the rest of them */ + 0, /* 1 */ + 0, /* 2 */ + 0, /* 3 */ + 0, /* 4 */ + 0, /* 5 */ + 0, /* 6 */ + 0, /* 7 */ + 0, /* 8 */ + 0, /* 9 */ + 0, /* 10 */ + 0, /* 11 */ + 0, /* 12 */ + 0, /* 13 */ + 0, /* 14 */ + 0, /* 15 */ + 0, /* 16 */ + 0, /* 17 */ 1, /* 18 all the rest of them */ 1, /* 19 all the rest of them */ 1, /* 20 all the rest of them */ @@ -108,25 +125,78 @@ static unsigned char mcp750_openpic_initpolarities[] = { 1, /* 23 all the rest of them */ 1, /* 24 all the rest of them */ 1, /* 25 all the rest of them */ + 1, /* 26 all the rest of them */ + 1, /* 27 all the rest of them */ + 1, /* 28 all the rest of them */ + 1, /* 29 all the rest of them */ + 1, /* 30 all the rest of them */ + 1, /* 31 all the rest of them */ + 1, /* 32 all the rest of them */ + 1, /* 33 all the rest of them */ + 1, /* 34 all the rest of them */ + 1, /* 35 all the rest of them */ + 1, /* 36 all the rest of them */ + 1, /* 37 all the rest of them */ + 1, /* 38 all the rest of them */ + 1, /* 39 all the rest of them */ + 1, /* 40 all the rest of them */ + 1, /* 41 all the rest of them */ + 1, /* 42 all the rest of them */ + 1, /* 43 all the rest of them */ + 1, /* 44 all the rest of them */ + 1, /* 45 all the rest of them */ + 1, /* 46 all the rest of them */ + 1, /* 47 all the rest of them */ + 1, /* 48 all the rest of them */ + 1, /* 49 all the rest of them */ + 1, /* 50 all the rest of them */ + 1, /* 51 all the rest of them */ + }; -static unsigned char mcp750_openpic_initsenses[] = { - 1, /* 0 MCP750_INT_PCB(8259) */ - 0, /* 1 MCP750_INT_FALCON_ECC_ERR */ - 1, /* 2 MCP750_INT_PCI_ETHERNET */ - 1, /* 3 MCP750_INT_PCI_PMC */ - 1, /* 4 MCP750_INT_PCI_WATCHDOG_TIMER1 */ - 1, /* 5 MCP750_INT_PCI_PRST_SIGNAL */ - 1, /* 6 MCP750_INT_PCI_FALL_SIGNAL */ - 1, /* 7 MCP750_INT_PCI_DEG_SIGNAL */ - 1, /* 8 MCP750_INT_PCI_BUS1_INTA */ - 1, /* 9 MCP750_INT_PCI_BUS1_INTB */ - 1, /*10 MCP750_INT_PCI_BUS1_INTC */ - 1, /*11 MCP750_INT_PCI_BUS1_INTD */ - 1, /*12 MCP750_INT_PCI_BUS2_INTA */ - 1, /*13 MCP750_INT_PCI_BUS2_INTB */ - 1, /*14 MCP750_INT_PCI_BUS2_INTC */ - 1, /*15 MCP750_INT_PCI_BUS2_INTD */ +static unsigned char mpc8245_openpic_initsenses[] = { + 1, /* 0 */ + 0, /* 1 */ + 1, /* 2 */ + 1, /* 3 */ + 1, /* 4 */ + 1, /* 5 */ + 1, /* 6 */ + 1, /* 7 */ + 1, /* 8 */ + 1, /* 9 */ + 1, /*10 */ + 1, /*11 */ + 1, /*12 */ + 1, /*13 */ + 1, /*14 */ + 1, /*15 */ + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, 1, 1, 1, @@ -138,6 +208,7 @@ static unsigned char mcp750_openpic_initsenses[] = { 1, 1 }; +#endif /* * This code assumes the exceptions management setup has already @@ -147,24 +218,41 @@ static unsigned char mcp750_openpic_initsenses[] = { */ void BSP_rtems_irq_mng_init(unsigned cpuId) { - int i; + int i; /* * First initialize the Interrupt management hardware */ #ifdef TRACE_IRQ_INIT - printk("Going to initialize openpic compliant device\n"); -#endif + uint32_t msr; + + _CPU_MSR_GET( msr ); + printk("BSP_rtems_irq_mng_init: Initialize openpic compliant device with MSR %x \n", msr); + printk(" BSP_ISA_IRQ_NUMBER %d\n",BSP_ISA_IRQ_NUMBER ); + printk(" BSP_ISA_IRQ_LOWEST_OFFSET %d\n",BSP_ISA_IRQ_LOWEST_OFFSET ); + printk(" BSP_ISA_IRQ_MAX_OFFSET %d\n", BSP_ISA_IRQ_MAX_OFFSET); + printk(" BSP_PCI_IRQ_NUMBER %d\n",BSP_PCI_IRQ_NUMBER ); + printk(" BSP_PCI_IRQ_LOWEST_OFFSET %d\n",BSP_PCI_IRQ_LOWEST_OFFSET ); + printk(" BSP_PCI_IRQ_MAX_OFFSET %d\n",BSP_PCI_IRQ_MAX_OFFSET ); + printk(" BSP_PROCESSOR_IRQ_NUMBER %d\n",BSP_PROCESSOR_IRQ_NUMBER ); + printk(" BSP_PROCESSOR_IRQ_LOWEST_OFFSET %d\n",BSP_PROCESSOR_IRQ_LOWEST_OFFSET ); + printk(" BSP_PROCESSOR_IRQ_MAX_OFFSET %d\n", BSP_PROCESSOR_IRQ_MAX_OFFSET); + printk(" BSP_MISC_IRQ_NUMBER %d\n", BSP_MISC_IRQ_NUMBER); + printk(" BSP_MISC_IRQ_LOWEST_OFFSET %d\n", BSP_MISC_IRQ_LOWEST_OFFSET); + printk(" BSP_MISC_IRQ_MAX_OFFSET %d\n",BSP_MISC_IRQ_MAX_OFFSET ); + printk(" BSP_IRQ_NUMBER %d\n",BSP_IRQ_NUMBER ); + printk(" BSP_LOWEST_OFFSET %d\n",BSP_LOWEST_OFFSET ); + printk(" BSP_MAX_OFFSET %d\n",BSP_MAX_OFFSET ); +#endif + /* FIXME (t.s.): we should probably setup the EOI delay by * passing a non-zero 'epic_freq' argument (frequency of the * EPIC serial interface) but I don't know the value on this * board (8245 SDRAM freq, IIRC)... + * + * When tested this appears to work correctly. */ - openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses, 0, 16, 0 /* epic_freq */); - -#ifdef TRACE_IRQ_INIT - printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n"); -#endif + openpic_init(1, mpc8245_openpic_initpolarities, mpc8245_openpic_initsenses, 0, 0, 0); /* * Initialize Rtems management interrupt table @@ -175,7 +263,11 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) for (i = 0; i < BSP_IRQ_NUMBER; i++) { rtemsIrq[i] = defaultIrq; rtemsIrq[i].name = i; +#ifdef BSP_SHARED_HANDLER_SUPPORT + rtemsIrq[i].next_handler = NULL; +#endif } + /* * Init initial Interrupt management config */ @@ -185,14 +277,20 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) initial_config.irqBase = BSP_LOWEST_OFFSET; initial_config.irqPrioTbl = irqPrioTable; -printk("Call BSP_rtems_irq_mngt_set\n"); + +#ifdef TRACE_IRQ_INIT + _CPU_MSR_GET( msr ); + printk("BSP_rtems_irq_mng_init: Set initial configuration with MSR %x\n", msr); +#endif if (!BSP_rtems_irq_mngt_set(&initial_config)) { /* * put something here that will show the failure... */ BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); + } else { + printk(" Initialized RTEMS Interrupt Manager\n"); } - + #ifdef TRACE_IRQ_INIT printk("RTEMS IRQ management is now operationnal\n"); #endif diff --git a/c/src/lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c b/c/src/lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c index 791500083b..61be6b78ef 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c +++ b/c/src/lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c @@ -23,7 +23,7 @@ #include <bsp/vectors.h> #include <stdlib.h> -#include <rtems/bspIo.h> /* for printk */ +#include <rtems/bspIo.h> #define RAVEN_INTR_ACK_REG 0xfeff0030 #ifdef BSP_PCI_ISA_BRIDGE_IRQ @@ -41,28 +41,31 @@ rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_NUMBER]; /* * default handler connected on each irq after bsp initialization */ -static rtems_irq_connect_data default_rtems_entry; +static rtems_irq_connect_data default_rtems_entry; +static rtems_irq_connect_data* rtems_hdl_tbl; -static rtems_irq_connect_data* rtems_hdl_tbl; - -#ifdef BSP_PCI_ISA_BRIDGE_IRQ /* * Check if IRQ is an ISA IRQ */ static inline int is_isa_irq(const rtems_irq_number irqLine) { - return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) & + if ( BSP_ISA_IRQ_NUMBER == 0 ) + return FALSE; + + return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) && ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET) ); } -#endif /* * Check if IRQ is an OPENPIC IRQ */ static inline int is_pci_irq(const rtems_irq_number irqLine) { - return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) & + if ( BSP_PCI_IRQ_NUMBER == 0 ) + return FALSE; + + return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) && ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET) ); } @@ -98,46 +101,34 @@ static void compute_i8259_masks_from_prio (rtems_irq_global_settings* config) } #endif -void -BSP_enable_irq_at_pic(const rtems_irq_number name) +void BSP_enable_irq_at_pic(const rtems_irq_number name) { -#ifdef BSP_PCI_ISA_BRIDGE_IRQ - if (is_isa_irq(name)) { - /* - * Enable interrupt at PIC level - */ -printk("ERROR BSP_irq_enable_at_i8259s Being Called for %d\n", (int)name); - BSP_irq_enable_at_i8259s ((int) name); - } -#endif - - if (is_pci_irq(name)) { - /* - * Enable interrupt at OPENPIC level - */ -printk(" openpic_enable_irq %d\n", (int)name ); - openpic_enable_irq ((int) name); - } + if (is_isa_irq(name)) { + printk("BSP_enable_irq_at_pic: called with isa irq\n"); + } + if (is_pci_irq(name)) { + /* + * enable interrupt at OPENPIC level. + */ + openpic_enable_irq ( ((int)name - BSP_PCI_IRQ_LOWEST_OFFSET) + 16 ); + } } -int -BSP_disable_irq_at_pic(const rtems_irq_number name) +int BSP_disable_irq_at_pic(const rtems_irq_number name) { -#ifdef BSP_PCI_ISA_BRIDGE_IRQ if (is_isa_irq(name)) { /* * disable interrupt at PIC level */ - return BSP_irq_disable_at_i8259s ((int) name); + printk("BSP_disable_irq_at_pic: called with isa irq\n"); } -#endif if (is_pci_irq(name)) { /* * disable interrupt at OPENPIC level */ - return openpic_disable_irq ((int) name ); + return openpic_disable_irq (((int) name - BSP_PCI_IRQ_LOWEST_OFFSET) + 16 ); } - return -1; + return -1; } /* @@ -146,23 +137,23 @@ BSP_disable_irq_at_pic(const rtems_irq_number name) int BSP_setup_the_pic(rtems_irq_global_settings* config) { int i; + /* * Store various code accelerators */ default_rtems_entry = config->defaultEntry; - rtems_hdl_tbl = config->irqHdlTbl; - + rtems_hdl_tbl = config->irqHdlTbl; + /* * set up internal tables used by rtems interrupt prologue */ -#if 0 #ifdef BSP_PCI_ISA_BRIDGE_IRQ /* * start with ISA IRQ */ compute_i8259_masks_from_prio (config); - for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) { + for (i=BSP_ISA_IRQ_LOWEST_OFFSET; (i < (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER)); i++) { if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { BSP_irq_enable_at_i8259s (i); } @@ -178,7 +169,6 @@ int BSP_setup_the_pic(rtems_irq_global_settings* config) BSP_irq_enable_at_i8259s (2); } #endif -#endif /* * continue with PCI IRQ @@ -190,27 +180,26 @@ int BSP_setup_the_pic(rtems_irq_global_settings* config) openpic_set_source_priority(i - BSP_PCI_IRQ_LOWEST_OFFSET, config->irqPrioTbl[i]); if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { - openpic_enable_irq ((int) i ); + openpic_enable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET); } else { - openpic_disable_irq ((int) i ); + openpic_disable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET); } } #ifdef BSP_PCI_ISA_BRIDGE_IRQ if ( BSP_ISA_IRQ_NUMBER > 0 ) { - /* - * Must enable PCI/ISA bridge IRQ - */ - openpic_enable_irq (0); + /* + * Must enable PCI/ISA bridge IRQ + */ + openpic_enable_irq (0); } #endif - + return 1; } int _BSP_vme_bridge_irq = -1; - unsigned BSP_spuriousIntr = 0; /* @@ -224,29 +213,24 @@ int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum) register unsigned oldMask = 0; /* old isa pic masks */ register unsigned newMask; /* new isa pic masks */ #endif - if (excNum == ASM_DEC_VECTOR) { -/* printk("ASM_DEC_VECTOR\n"); */ - bsp_irq_dispatch_list(rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_entry.hdl); - + bsp_irq_dispatch_list_base(rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_entry.hdl); return 0; } irq = openpic_irq(0); if (irq == OPENPIC_VEC_SPURIOUS) { -/* printk("OPENPIC_VEC_SPURIOUS interrupt %d\n", OPENPIC_VEC_SPURIOUS ); */ - ++BSP_spuriousIntr; + printk("OPENPIC_VEC_SPURIOUS interrupt %d\n", OPENPIC_VEC_SPURIOUS ); + ++BSP_spuriousIntr; return 0; } /* some BSPs might want to use a different numbering... */ - irq = irq - OPENPIC_VEC_SOURCE + BSP_PCI_IRQ_LOWEST_OFFSET; -/* printk("OpenPic Irq: %d\n", irq); */ + irq = irq - OPENPIC_VEC_SOURCE ; #ifdef BSP_PCI_ISA_BRIDGE_IRQ isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ); if (isaIntr) { -/* printk("BSP_PCI_ISA_BRIDGE_IRQ\n"); */ /* * Acknowledge and read 8259 vector */ @@ -264,30 +248,28 @@ int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum) } #endif - /* dispatch handlers */ -/* printk("dispatch\n"); */ -irq -=16; - bsp_irq_dispatch_list(rtems_hdl_tbl, irq, default_rtems_entry.hdl); -/* printk("Back from dispatch\n"); */ + bsp_irq_dispatch_list_base(rtems_hdl_tbl, irq, default_rtems_entry.hdl); #ifdef BSP_PCI_ISA_BRIDGE_IRQ - if (isaIntr) {\ + if (isaIntr) { i8259s_cache = oldMask; outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); } else #endif + { #ifdef BSP_PCI_VME_DRIVER_DOES_EOI - /* leave it to the VME bridge driver to do EOI, so + /* leave it to the VME bridge driver to do EOI, so * it can re-enable the openpic while handling * VME interrupts (-> VME priorities in software) - */ - if (_BSP_vme_bridge_irq != irq) + */ + if (_BSP_vme_bridge_irq != irq) #endif - openpic_eoi(0); + openpic_eoi(0); } return 0; + } diff --git a/c/src/lib/libbsp/powerpc/ep1a/preinstall.am b/c/src/lib/libbsp/powerpc/ep1a/preinstall.am index 8afeb3b549..b4b5eb3468 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/preinstall.am +++ b/c/src/lib/libbsp/powerpc/ep1a/preinstall.am @@ -57,9 +57,9 @@ $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds -$(PROJECT_INCLUDE)/bsp/uart.h: ../../powerpc/shared/console/uart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart.h +$(PROJECT_INCLUDE)/bsp/pci.h: ../../powerpc/shared/pci/pci.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pci.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pci.h $(PROJECT_INCLUDE)/bsp/motorola.h: ../../powerpc/shared/motorola/motorola.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/motorola.h @@ -81,15 +81,7 @@ $(PROJECT_INCLUDE)/bsp/rsPMCQ1.h: console/rsPMCQ1.h $(PROJECT_INCLUDE)/bsp/$(dir $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/rsPMCQ1.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/rsPMCQ1.h -$(PROJECT_INCLUDE)/bsp/openpic.h: ../../powerpc/shared/openpic/openpic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/openpic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/openpic.h - -$(PROJECT_INCLUDE)/bsp/pci.h: ../../powerpc/shared/pci/pci.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pci.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pci.h - -$(PROJECT_INCLUDE)/bsp/irq.h: ../../powerpc/shared/irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) +$(PROJECT_INCLUDE)/bsp/irq.h: irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h @@ -105,6 +97,10 @@ $(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bsps $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h +$(PROJECT_INCLUDE)/bsp/openpic.h: ../../powerpc/shared/openpic/openpic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/openpic.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/openpic.h + $(PROJECT_INCLUDE)/bsp/vmeUniverse.h: ../../shared/vmeUniverse/vmeUniverse.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vmeUniverse.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vmeUniverse.h diff --git a/c/src/lib/libbsp/powerpc/ep1a/start/start.S b/c/src/lib/libbsp/powerpc/ep1a/start/start.S index bdf971f73f..3e98fd11ae 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/start/start.S +++ b/c/src/lib/libbsp/powerpc/ep1a/start/start.S @@ -114,6 +114,10 @@ __rtems_entry_point: lis sp,__stack@h ori sp,sp,__stack@l + lis r13,_SDA_BASE_@ha + la r13,_SDA_BASE_@l(r13) /* Read-write small data */ + + /* set up initial stack frame */ addi sp,sp,-4 /* make sure we don't overwrite debug mem */ lis r0,0 diff --git a/c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c b/c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c index 5f82b3fe54..084204d2f3 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c @@ -4,7 +4,7 @@ * The generic CPU dependent initialization has been performed * before this routine is invoked. * - * COPYRIGHT (c) 1989-2007. + * COPYRIGHT (c) 1989-2009. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -14,7 +14,7 @@ * $Id$ */ -#warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c). +#define SHOW_MORE_INIT_SETTINGS #include <string.h> @@ -33,6 +33,7 @@ #include <libcpu/cpuIdent.h> #include <bsp/vectors.h> #include <rtems/powerpc/powerpc.h> +#include <bsp/ppc_exc_bspsupp.h> extern unsigned long __rtems_end[]; extern void L1_caches_enables(void); @@ -94,6 +95,13 @@ extern int RAM_END; unsigned int BSP_mem_size = (unsigned int)&RAM_END; /* + * Where the heap starts; is used by bsp_pretasking_hook; + */ +unsigned int BSP_heap_start; +uint32_t BSP_intrStackStart; +uint32_t BSP_intrStackSize; + +/* * PCI Bus Frequency */ unsigned int BSP_bus_frequency; @@ -105,13 +113,15 @@ unsigned int BSP_processor_frequency; /* * Time base divisior (how many tick for 1 second). + * Calibrated by outputing a 20 ms pulse. */ -unsigned int BSP_time_base_divisor = 1000; /* XXX - Just a guess */ +unsigned int BSP_time_base_divisor = 1320; /* * system init stack */ -#define INIT_STACK_SIZE 0x1000 +#define INIT_STACK_SIZE 0x2000 +#define INTR_STACK_SIZE rtems_configuration_get_interrupt_stack_size() void BSP_panic(char *s) { @@ -170,6 +180,38 @@ void BSP_FLASH_set_page( void bsp_libc_init( void *, uint32_t, int ); + +void ShowMemoryLayout(){ + extern unsigned long __bss_start[], __SBSS_START__[], __SBSS_END__[]; + extern unsigned long __SBSS2_START__[], __SBSS2_END__[]; + extern unsigned long __bss_start[]; + extern unsigned long __bss_end[]; + extern unsigned long __stack[]; + extern unsigned long __stackLow[]; + extern uint32_t end; + /* extern uint32_t BSP_intrStackStart; */ + /* extern uint32_t BSP_intrStackSize; */ + /* Configuration.work_space_start */ + /* rtems_configuration_get_work_space_size() */ + printk(" bss start: 0x%x\n", __bss_start); + printk(" bss end: 0x%x\n", __bss_end); + printk(" rtems end: 0x%x\n", __rtems_end); + printk(" stack : 0x%x\n", __stack); + printk(" stack Low: 0x%x\n", __stackLow); + printk(" end : 0x%x\n", &end); + printk(" Intr Stack: 0x%x\n", BSP_intrStackStart); + printk(" Intr Stack Size: 0x%x\n", BSP_intrStackSize); + printk(" Heap start: %x\n", BSP_heap_start); + + printk(" workspace start: 0x%x\n", Configuration.work_space_start); + printk(" workspace size: 0x%x\n", rtems_configuration_get_work_space_size() ); + +} + + + + + /* * Function: bsp_pretasking_hook * Created: 95/03/10 @@ -186,28 +228,30 @@ void bsp_libc_init( void *, uint32_t, int ); void bsp_pretasking_hook(void) { - uint32_t heap_start; + uint32_t heap_start = BSP_heap_start; uint32_t heap_size; uint32_t heap_sbrk_spared; - extern uint32_t _bsp_sbrk_init(uint32_t, uint32_t*); - - heap_start = ((uint32_t) __rtems_end) + - INIT_STACK_SIZE + rtems_configuration_get_interrupt_stack_size(); - if (heap_start & (CPU_ALIGNMENT-1)) - heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); + extern uint32_t end; - heap_size = (BSP_mem_size - heap_start) - rtems_configuration_get_work_space_size(); + heap_start = (BSP_heap_start + CPU_ALIGNMENT - 1) & ~(CPU_ALIGNMENT-1); + heap_size = (uint32_t) &RAM_END; + heap_size = heap_size - heap_start - Configuration.work_space_size; + heap_size &= 0xfffffff0; /* keep it as a multiple of 16 bytes */ - heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size); +#if 0 /*XXXXXXX */ + heap_size = Configuration.work_space_start - (void *)&end; + heap_size &= 0xfffffff0; /* keep it as a multiple of 16 bytes */ +#endif #ifdef SHOW_MORE_INIT_SETTINGS - printk(" HEAP start %x size %x (%x bytes spared for sbrk)\n", - heap_start, heap_size, heap_sbrk_spared); + printk(" HEAP start 0x%x size %x \n", + heap_start, heap_size, 0 ); #endif - bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared); + bsp_libc_init((void *)heap_start, heap_size, 0); rsPMCQ1Init(); + ShowMemoryLayout(); } void zero_bss() @@ -232,21 +276,8 @@ void save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_op unsigned int EUMBBAR; unsigned int get_eumbbar() { - register int a, e; - - asm volatile( "lis %0,0xfec0; ori %0,%0,0x0000": "=r" (a) ); - asm volatile("sync"); - - asm volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) ); - asm volatile("stwbrx %0,0x0,%1": "=r"(e): "r"(a)); - asm volatile("sync"); - - asm volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) ); - asm volatile("sync"); - - asm volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a)); - asm volatile("isync"); - return e; + out_le32( (uint32_t*)0xfec00000, 0x80000078 ); + return in_le32( (uint32_t*)0xfee00000 ); } void Read_ep1a_config_registers( ppc_cpu_id_t myCpu ) { @@ -317,6 +348,7 @@ void Read_ep1a_config_registers( ppc_cpu_id_t myCpu ) { BSP_bus_frequency = 33000000; break; } + printk("Processor Frequency %d Bus Frequency: %d\n", BSP_processor_frequency, BSP_bus_frequency ); } /* @@ -328,8 +360,6 @@ void Read_ep1a_config_registers( ppc_cpu_id_t myCpu ) { void bsp_start( void ) { unsigned char *stack; - uint32_t intrStackStart; - uint32_t intrStackSize; unsigned char *work_space_start; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; @@ -346,15 +376,22 @@ void bsp_start( void ) EUMBBAR = get_eumbbar(); printk("EUMBBAR 0x%08x\n", EUMBBAR ); + /* + * Init MMU block address translation to enable hardware + * access + */ + setdbat(1, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE); + setdbat(2, 0x80000000, 0x80000000, 0x10000000, IO_PAGE); + setdbat(3, 0x90000000, 0x90000000, 0x10000000, IO_PAGE); +ShowBATS(); + /* * Note this sets BSP_processor_frequency based upon register settings. * It must be done prior to setting up hooks. */ Read_ep1a_config_registers( myCpu ); - bsp_clicks_per_usec = BSP_processor_frequency/(BSP_time_base_divisor * 1000); -ShowBATS(); #if 0 /* XXX - Add back in cache enable when we get this up and running!! */ /* * enables L1 Cache. Note that the L1_caches_enables() codes checks for @@ -364,40 +401,34 @@ ShowBATS(); #endif /* - * the initial stack has aready been set to this value in start.S - * so there is no need to set it in r1 again... It is just for info - * so that It can be printed without accessing R1. - */ - stack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE - PPC_MINIMUM_STACK_FRAME_SIZE; - - /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */ - *((uint32_t *)stack) = 0; - - /* * Initialize the interrupt related settings. */ - intrStackStart = (uint32_t) __rtems_end + INIT_STACK_SIZE; - intrStackSize = rtems_configuration_get_interrupt_stack_size(); + BSP_intrStackStart = (uint32_t) __rtems_end + INIT_STACK_SIZE; + BSP_intrStackSize = rtems_configuration_get_interrupt_stack_size(); + BSP_heap_start = BSP_intrStackStart + BSP_intrStackSize; + printk("Interrupt Stack Start: 0x%x Size: 0x%x Heap Start: 0x%x\n", + BSP_intrStackStart, BSP_intrStackSize, BSP_heap_start + ); + + /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */ + *((uint32_t *)BSP_intrStackStart) = 0; /* * Initialize default raw exception hanlders. */ + +#ifdef SHOW_MORE_INIT_SETTINGS + printk("bsp_start: Initialize Exceptions\n"); +#endif + ppc_exc_cache_wb_check = 0; ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, - intrStackStart, - intrStackSize + BSP_intrStackStart, + BSP_intrStackSize ); - /* - * Init MMU block address translation to enable hardware - * access - */ - setdbat(1, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE); - setdbat(3, 0x90000000, 0x90000000, 0x10000000, IO_PAGE); - - #ifdef SHOW_MORE_INIT_SETTINGS - printk("Going to start PCI buses scanning and initialization\n"); + printk("bsp_start: Going to start PCI buses scanning and initialization\n"); #endif pci_initialize(); @@ -405,7 +436,7 @@ ShowBATS(); printk("Number of PCI buses found is : %d\n", pci_bus_count()); #endif #ifdef TEST_RAW_EXCEPTION_CODE - printk("Testing exception handling Part 1\n"); + printk("bsp_start: Testing exception handling Part 1\n"); /* * Cause a software exception @@ -415,28 +446,45 @@ ShowBATS(); /* * Check we can still catch exceptions and returned coorectly. */ - printk("Testing exception handling Part 2\n"); + printk("bsp_start: Testing exception handling Part 2\n"); __asm__ __volatile ("sc"); #endif #ifdef SHOW_MORE_INIT_SETTINGS - printk("rtems_configuration_get_work_space_size() = %x\n", + printk("bsp_start: rtems_configuration_get_work_space_size() = %x\n", rtems_configuration_get_work_space_size()); #endif work_space_start = - (unsigned char *)BSP_mem_size - rtems_configuration_get_work_space_size(); - + (unsigned char *)&RAM_END - rtems_configuration_get_work_space_size(); if ( work_space_start <= ((unsigned char *)__rtems_end) + INIT_STACK_SIZE + rtems_configuration_get_interrupt_stack_size()) { printk( "bspstart: Not enough RAM!!!\n" ); bsp_cleanup(); } - Configuration.work_space_start = work_space_start; +#ifdef SHOW_MORE_INIT_SETTINGS + printk("bsp_start: workspace_start = 0x%x\n", + work_space_start); +#endif + + #if ( PPC_USE_DATA_CACHE ) + #if DEBUG + printk("bsp_start: cache_enable\n"); + #endif + instruction_cache_enable (); + data_cache_enable (); + #if DEBUG + printk("bsp_start: END PPC_USE_DATA_CACHE\n"); + #endif + #endif + /* * Initalize RTEMS IRQ system */ +#ifdef SHOW_MORE_INIT_SETTINGS + printk("bspstart: Call BSP_rtems_irq_mng_init\n"); +#endif BSP_rtems_irq_mng_init(0); /* Activate the page table mappings only after @@ -445,7 +493,7 @@ ShowBATS(); */ if (pt) { #ifdef SHOW_MORE_INIT_SETTINGS - printk("Page table setup finished; will activate it NOW...\n"); + printk("bspstart: Page table setup finished; will activate it NOW...\n"); #endif BSP_pgtbl_activate(pt); } @@ -455,7 +503,7 @@ ShowBATS(); * and IRQ subsystems... */ #ifdef SHOW_MORE_INIT_SETTINGS - printk("Going to initialize VME bridge\n"); + printk("bspstart: Going to initialize VME bridge\n"); #endif /* VME initialization is in a separate file so apps which don't use * VME or want a different configuration may link against a customized diff --git a/c/src/lib/libbsp/powerpc/ep1a/startup/linkcmds b/c/src/lib/libbsp/powerpc/ep1a/startup/linkcmds index 8a1885224e..bec0230d66 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/startup/linkcmds +++ b/c/src/lib/libbsp/powerpc/ep1a/startup/linkcmds @@ -152,7 +152,9 @@ SECTIONS *(COMMON) PROVIDE (__bss_end = .); } - . = ALIGN(8) + 0x8000; + . = ALIGN(0x100); + PROVIDE (__stackLow = .); + . += 0x8000; PROVIDE (__stack = .); _end = . ; __rtems_end = . ; diff --git a/c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h b/c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h index 8492733a2d..79610cccf5 100644 --- a/c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h +++ b/c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h @@ -77,7 +77,8 @@ * at _VME_DRAM_OFFSET */ #undef _VME_DRAM_OFFSET -#define _VME_DRAM_OFFSET 0xc0000000 +/* #define _VME_DRAM_OFFSET 0xc0000000 */ + #define _VME_DRAM_32_OFFSET1 0x20000000 #define _VME_DRAM_32_OFFSET2 0x20b00000 #define _VME_DRAM_24_OFFSET1 0x00000000 diff --git a/c/src/lib/libbsp/powerpc/ep1a/vme/vmeconfig.c b/c/src/lib/libbsp/powerpc/ep1a/vme/vmeconfig.c new file mode 100644 index 0000000000..c350547f2f --- /dev/null +++ b/c/src/lib/libbsp/powerpc/ep1a/vme/vmeconfig.c @@ -0,0 +1,144 @@ +/* $Id$ */ + +/* Default VME bridge configuration - note that this file + * is independent of the bridge driver/chip + */ + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 3/2002, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include <bsp.h> +#include <bsp/VME.h> +#include <bsp/VMEConfig.h> +#ifdef BSP_VME_BAT_IDX +#include <libcpu/bat.h> +#endif +#include <rtems/bspIo.h> + +extern int BSP_VMEInit(void); +extern int BSP_VMEIrqMgrInstall(void); + +/* Use a weak alias for the VME configuration. + * This permits individual applications to override + * this routine. + * They may even create an 'empty' + * + * void BSP_vme_config(void) {} + * + * which will avoid linking in the Universe driver + * at all :-). + */ + +void BSP_vme_config(void) + __attribute__ (( weak, alias("__BSP_EP1A_vme_config") )); + +void __BSP_EP1A_vme_config(void) +{ + if ( BSP_VMEInit() ) { + printk("Skipping VME initialization...\n"); + return; + } + +#ifdef BSP_VME_BAT_IDX + printk("BSP_VME_BAT_IDX\n"); + /* setup a PCI area to map the VME bus */ + setdbat(BSP_VME_BAT_IDX, + PCI_MEM_BASE + _VME_A32_WIN0_ON_PCI, + PCI_MEM_BASE + _VME_A32_WIN0_ON_PCI, + 0x10000000, + IO_PAGE); +#endif + + /* map VME address ranges */ + BSP_VMEOutboundPortCfg( + 0, + VME_AM_EXT_SUP_DATA, + _VME_A32_WIN0_ON_VME, + _VME_A32_WIN0_ON_PCI, + 0x0f000000); + BSP_VMEOutboundPortCfg( + 1, + VME_AM_STD_SUP_DATA, + 0x00000000, + _VME_A24_ON_PCI, + 0x00ff0000); + BSP_VMEOutboundPortCfg( + 2, + VME_AM_SUP_SHORT_IO, + 0x00000000, + _VME_A16_ON_PCI, + 0x00010000); + +#ifdef _VME_CSR_ON_PCI + /* Map VME64 CSR */ + printk("_VME_CSR_ON_PCI\n"); + BSP_VMEOutboundPortCfg( + 7, + VME_AM_CSR, + 0, + _VME_CSR_ON_PCI, + 0x01000000); +#endif + + +#ifdef _VME_DRAM_OFFSET + printk("_VME_DRAM_OFFSET"); + /* map our memory to VME giving the driver a hint that it's ordinary memory + * so they can enable decoupled cycles which should give better performance... + */ + BSP_VMEInboundPortCfg( + 0, + VME_AM_EXT_SUP_DATA | VME_AM_IS_MEMORY, + _VME_DRAM_OFFSET, + PCI_DRAM_OFFSET, + BSP_mem_size); +#endif + + /* stdio is not yet initialized; the driver will revert to printk */ + BSP_VMEOutboundPortsShow(0); + BSP_VMEInboundPortsShow(0); + + BSP_VMEIrqMgrInstall(); +} |