diff options
Diffstat (limited to 'c/src/lib')
| -rw-r--r-- | c/src/lib/libbsp/m68k/gen68302/README | 154 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/gen68302/clock/ckinit.c | 94 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/gen68302/console/console.c | 241 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/gen68302/include/bsp.h | 105 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/gen68302/include/coverhd.h | 115 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/gen68302/start/start302.s | 273 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/gen68302/start302/start302.s | 273 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/gen68302/startup/bspclean.c | 26 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/gen68302/startup/bspstart.c | 169 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/gen68302/timer/timer.c | 130 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s | 28 | ||||
| -rw-r--r-- | c/src/lib/libmisc/stackchk/check.c | 2 |
12 files changed, 1609 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/m68k/gen68302/README b/c/src/lib/libbsp/m68k/gen68302/README new file mode 100644 index 0000000000..0261083479 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/README @@ -0,0 +1,154 @@ +# +# $Id$ +# + +BSP NAME: gen68302 +BOARD: proprietary (see below for relevant information) +BUS: none +CPU FAMILY: MC68000 +COPROCESSORS: 68302 communications co-processor +MODE: not applicable + +DEBUG MONITOR: none + +PERIPHERALS +=========== +TIMERS: two 68302 timers, one 68302 watchdog timer + RESOLUTION: ? +SERIAL PORTS: three 68302 SCCs +REAL-TIME CLOCK: +DMA: built-in 68302, not used +VIDEO: none +SCSI: none +NETWORKING: none + +DRIVER INFORMATION +================== +CLOCK DRIVER: 68302 (TIMER1) +IOSUPP DRIVER: 68302 SCC2 +SHMSUPP: none +TIMER DRIVER: 68302 TIMER2 + +STDIO +===== +PORT: ? +ELECTRICAL: EIA-232 +BAUD: 9600 +BITS PER CHARACTER: 8 +PARITY: None +STOP BITS: 1 + +NOTES +===== + +Board description +----------------- +clock rate: 16 MHz +bus width: 16 bits +ROM: 128 kbyte (flash, 0 wait states, chip select 0) +RAM: 256 kbyte (static, 0 wait states, chip select 1) + +The 68302's built-in DRAM refresh controller circuitry is neither used +nor configured at startup. + +Host System +----------- +HP 9000/715, HP-UX 9.05 +gcc-2.6.3 +binutils-2.5.2 + + +Verification +------------ +The 1-ms clock ISR rate was verified with an in-circuit emulator. + +Single processor tests: +Multi-processort tests: not applicable +Timing tests: see results in c/src/tests/tmtests/times + +Note: The board has 256 kbyte RAM, so the timing tests would not run +with the standard executive RAM size configuration of 256 K. +Modifying the conftbl.h files to specify 160 kbyte for workspace +seemed to work. + +* Porting + +** Mod c/src/tests/tmtests/*/conftbl.h + +Modified to use 160 kbyte for executive RAM size. + +** Add c/make/custom/gen68302.cfg + +Based on m68k_no_bsp.cfg. Turned off multiprocessor support. Had to +use a BSP-specific compiler configuration file in order to link the +proper startup file. + +** Mod c/make/compilers/gcc-m68000.cfg + +Added "-m68000" to the AS macro so that non-68000 instructions are +neither generated nor allowed (remember that the GNU assembler +supports pseudo-assembler instructions (e.g. jbsr) that will be +"intelligently" assembled.) Added "m68000/" before libgcc.a so that +non-68000 instructions aren't included. + +** Add c/make/compilers/gcc-gen68302.cfg + +Based on modified gcc-m68000.cfg. + +Changed make-exe define to produce IEEE-695 output files for loading +into the emulator. + +The board has no debug monitor, so I had to create a 68302-specific +startup file (c/src/lib/libbsp/m68k/gen68302/start302/start302.s) to +override the c/src/lib/start/m68k/start.s. START_FILE entry was +modified to causes start302.s to be linked first (in lieu of start.s). + +** Mod c/src/exec/cpu/m68k/cpu.h + +Turned off software and hardware interrupt stack support. Added +support in _CPU_Bitfield_Find_first_bit() and +_CPU_Priority_Bits_index() to replace the bfffo instruction. + +TODO: add software-maintained interrupt stack. + +TODO: optimize things so that subtracting _priority from 15 isn't +required in _CPU_Priority_Bits_index(). + +** Mod c/src/exec/cpu/m68k/cpu.c + +Added the log base 2 table (__log2table) that's required by the BFFFO +replacement in cpu.h. + +** Mod c/src/exec/cpu/m68k/cpu_asm.s + +Added _ISR_Exit that's currently used in TBD.... Added ifdef wrapper +around ISR exit code that accessed the format nibble. Added some code +to restore the status register and call _Thread_Dispatch. + +TODO: add software-maintained interrupt stack. + +** Mod c/src/exec/cpu/m68k/m68k.h + +Changed "typedef char signed8" to "typedef signed char signed8". + +** Add c/src/lib/libbsp/m68k/gen68302/... +*** clock/ + +TODO: Add set_vector support. Figure out what to do with Clock_exit(). +TODO: Pre-compute (BSP_Configuration.microseconds_per_tick/1000) so that +it doesn't have to be re-computed on each Clock_isr(). + +*** console/ + +These files assume SCC2, but it shouldn't be too difficult to re-write +these to use any of the other SCCs. + +*** include/ +*** start302/ + +This contains the start302.s file that does some fairly tricky memory +re-mapping so that RAM ends up at 0 and ROM ends up at 0xc00000. + +*** startup/ +*** timer/ +*** wrapup/ diff --git a/c/src/lib/libbsp/m68k/gen68302/clock/ckinit.c b/c/src/lib/libbsp/m68k/gen68302/clock/ckinit.c new file mode 100644 index 0000000000..be3cf6ab21 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/clock/ckinit.c @@ -0,0 +1,94 @@ +/* Clock_init() + * + * This routine initializes Timer 1 for an MC68302. + * The tick frequency is 1 millisecond. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include <stdlib.h> /* for atexit() */ + +#include <rtems.h> +#include <bsp.h> +#include <clockdrv.h> +#include "m68302.h" + + +#define TMR1_VAL ( RBIT_TMR_RST /* software reset the timer */\ + | RBIT_TMR_ICLK_MASTER16 /* master clock divided by 16 */\ + | RBIT_TMR_FRR /* restart timer after ref reached */\ + | RBIT_TMR_ORI) /* enable interrupt when ref reached */ +#define TRR1_VAL 1000 /* 1000 ticks @ 16MHz/16 + * = 1 millisecond tick. + */ + +/* + * Clock_driver_ticks is a monotonically increasing counter of the + * number of clock ticks since the driver was initialized. + */ +volatile rtems_unsigned32 Clock_driver_ticks; + +/* + * Clock_isrs is the number of clock ISRs until the next invocation of + * the RTEMS clock tick routine. The clock tick device driver + * gets an interrupt once a millisecond and counts down until the + * length of time between the user configured microseconds per tick + * has passed. + */ +rtems_unsigned32 Clock_isrs; + + +rtems_device_driver Clock_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp, + rtems_id tid, + rtems_unsigned32 *rval +) +{ + Install_clock( Clock_isr ); +} + + +void Install_clock( + rtems_isr_entry clock_isr +) +{ + + Clock_driver_ticks = 0; + Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000; + + if ( BSP_Configuration.ticks_per_timeslice ) { +/* set_vector( clock_isr, 137, 1 );*/ + + m302.reg.trr1 = TRR1_VAL; /* set timer reference register */ + m302.reg.tmr1 = TMR1_VAL; /* set timer mode register & enable */ + /* + * Enable TIMER1 interrupts only. + */ + m302.reg.imr = RBIT_IMR_TIMER1; /* set 68302 int-mask to allow ints */ + + atexit( Clock_exit ); + } +} + + +void Clock_exit( void ) +{ + if ( BSP_Configuration.ticks_per_timeslice ) { + /* TODO: figure out what to do here */ + /* do not restore old vector */ + } +} diff --git a/c/src/lib/libbsp/m68k/gen68302/console/console.c b/c/src/lib/libbsp/m68k/gen68302/console/console.c new file mode 100644 index 0000000000..7f488c5cfd --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/console/console.c @@ -0,0 +1,241 @@ +/* + * Initialize the MC68302 SCC2 for console IO board support package. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#define GEN68302_INIT + +#include <rtems.h> +#include "console.h" +#include <bsp.h> + +#include "m68302.h" + +/* console_initialize + * + * This routine initializes the console IO driver. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: + */ + +rtems_device_driver console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg, + rtems_id self, + rtems_unsigned32 *status +) +{ + volatile m302_dualPortRAM_t *p = &m302; + + p->reg.pacnt |= 0x0003; /* enable RXD2 and TXD2 signals */ + /* + * TODO: Check assembly code. I think gcc's volatile semantics force + * this to not use a CLR. + */ + p->reg.simode = 0; /* NMSI mode */ + + p->reg.scc[1].scon = 0x00d8; /* 9600 baud */ + p->reg.scc[1].scm = 0x01b1; + + p->scc2.parm.rfcr = 0x50; /* Rx buffers in supervisor data */ + p->scc2.parm.tfcr = 0x50; /* Tx buffers in supervisor data */ + p->scc2.parm.mrblr = 0x0001; /* Max Rx buffer length is 1 byte */ + + p->scc2.prot.uart.max_idl = 0x0000; /* 0 = maximum timeout value */ + p->scc2.prot.uart.brkcr = 0x0001; /* send 1 break char on STOP TX cmd */ + p->scc2.prot.uart.parec = 0x0000; /* reset parity error counter */ + p->scc2.prot.uart.frmec = 0x0000; /* reset framing error counter */ + p->scc2.prot.uart.nosec = 0x0000; /* reset noise error counter */ + p->scc2.prot.uart.brkec = 0x0000; /* reset break condition counter */ + + p->scc2.prot.uart.character[0] = 0x0003; /* use <ctrl>c as control char */ + p->scc2.prot.uart.character[1] = 0x8000; /* set end of cntrl char table */ + + p->scc2.bd.rx[0].status = 0xA000; /* RxBD0 empty, wrap, no intr */ + p->scc2.bd.rx[0].length = 0x0000; + p->scc2.bd.rx[0].buffer = + (rtems_unsigned8 *) &m302.scc2.bd.rx[1]; /* RxBD1 is Rx buffer */ + + p->reg.scc[1].dsr = 0x7000; /* set full-length last stop bit */ + + p->scc2.bd.tx[0].status = 0x3000; /* TxBD0 not ready, wrap, intr */ + p->scc2.bd.tx[0].length = 0x0001; + p->scc2.bd.tx[0].buffer = + (rtems_unsigned8 *) &m302.scc2.bd.tx[1]; /* TxBD1 is Tx buffer */ + + p->reg.scc[1].scce = 0xFF; /* clear all SCC event flags */ + p->reg.scc[1].sccm = 0x03; /* enable only Tx & Rx interrupts */ + p->reg.scc[1].scm = 0x01BD; + + *status = RTEMS_SUCCESSFUL; +} + + +/* is_character_ready + * + * Check to see if a character is available on the MC68302's SCC2. If so, + * then return a TRUE (along with the character). Otherwise return FALSE. + * + * Input parameters: pointer to location in which to return character + * + * Output parameters: character (if available) + * + * Return values: TRUE - character available + * FALSE - no character available + */ + +rtems_boolean is_character_ready( + char *ch /* -> character */ +) +{ +#define RXS (m302.scc2.bd.rx[0].status) +#define RXD (* ((volatile char *) m302.scc2.bd.rx[0].buffer)) + + for (;;) { + if (RXS & RBIT_HDLC_EMPTY_BIT) + return FALSE; + + *ch = RXD; + RXS = RBIT_HDLC_EMPTY_BIT | RBIT_HDLC_WRAP_BIT; + if ( *ch >= ' ' && *ch <= '~' ) + return TRUE; + } +} + + +/* inbyte + * + * Receive a character from the MC68302's SCC2. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: character read + */ + +char inbyte( void ) +{ + char ch; + +#define RXS (m302.scc2.bd.rx[0].status) +#define RXD (* ((volatile char *) m302.scc2.bd.rx[0].buffer)) + + do { + while (RXS & RBIT_HDLC_EMPTY_BIT) + /* Wait until character received */ ; + + ch = RXD; + RXS = RBIT_HDLC_EMPTY_BIT | RBIT_HDLC_WRAP_BIT; + + if (ch == '\r' || ch == '\n') + break; + } while (ch < ' ' || ch > '~'); + + return ch; +} + + +/* outbyte + * + * Transmit a character out on the MC68302's SCC2. + * It may support XON/XOFF flow control. + * + * Input parameters: + * ch - character to be transmitted + * + * Output parameters: NONE + */ + +void outbyte( + char ch +) +{ +#define TXS (m302.scc2.bd.tx[0].status) +#define TXD (* ((volatile char *) m302.scc2.bd.tx[0].buffer)) + +#define RXS (m302.scc2.bd.rx[0].status) +#define RXD (* ((volatile char *) m302.scc2.bd.rx[0].buffer)) + + while (TXS & RBIT_HDLC_READY_BIT) + /* Wait until okay to transmit */ ; + + /* + * Check for flow control requests and process. + */ + while ( ! (RXS & RBIT_HDLC_EMPTY_BIT)) { + if (RXD == XOFF) + do { + RXS = RBIT_HDLC_EMPTY_BIT | RBIT_HDLC_WRAP_BIT; + while (RXS & RBIT_HDLC_EMPTY_BIT) + /* Wait until character received */ ; + } while (RXD != XON); + RXS = RBIT_HDLC_EMPTY_BIT | RBIT_HDLC_WRAP_BIT; + } + + TXD = ch; + TXS = RBIT_HDLC_READY_BIT | RBIT_HDLC_WRAP_BIT; + if (ch == '\n') + outbyte('\r'); +} + +/* + * __read -- read bytes from the serial port. Ignore fd, since + * we only have stdin. + */ + +int __read( + int fd, + char *buf, + int nbytes +) +{ + int i = 0; + + for (i = 0; i < nbytes; i++) { + *(buf + i) = inbyte(); + if ((*(buf + i) == '\n') || (*(buf + i) == '\r')) { + (*(buf + i++)) = '\n'; + (*(buf + i)) = 0; + break; + } + } + return (i); +} + +/* + * __write -- write bytes to the serial port. Ignore fd, since + * stdout and stderr are the same. Since we have no filesystem, + * open will only return an error. + */ + +int __write( + int fd, + char *buf, + int nbytes +) +{ + int i; + + for (i = 0; i < nbytes; i++) { + if (*(buf + i) == '\n') { + outbyte ('\r'); + } + outbyte (*(buf + i)); + } + return (nbytes); +} diff --git a/c/src/lib/libbsp/m68k/gen68302/include/bsp.h b/c/src/lib/libbsp/m68k/gen68302/include/bsp.h new file mode 100644 index 0000000000..04745e01d6 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/include/bsp.h @@ -0,0 +1,105 @@ +/* bsp.h + * + * This include file contains all board IO definitions. + * + * XXX : put yours in here + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#ifndef __GEN68302_BSP_h +#define __GEN68302_BSP_h + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rtems.h> +#include <iosupp.h> + +/* + * Define the time limits for RTEMS Test Suite test durations. + * Long test and short test duration limits are provided. These + * values are in seconds and need to be converted to ticks for the + * application. + * + */ + +#define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ +#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 0, 1 ) + +#define Cause_tm27_intr() + +#define Clear_tm27_intr() + +#define Lower_tm27_intr() + +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + */ + +#define delay( microseconds ) \ + { register rtems_unsigned32 _delay=(microseconds); \ + register rtems_unsigned32 _tmp=123; \ + asm volatile( "0: \ + nbcd %0 ; \ + nbcd %0 ; \ + dbf %1,0b" \ + : "=d" (_tmp), "=d" (_delay) \ + : "0" (_tmp), "1" (_delay) ); \ + } + +/* Constants */ + +#define RAM_START 0 +#define RAM_END 0x040000 + +/* Structures */ + +#ifdef GEN68302_INIT +#undef EXTERN +#define EXTERN +#else +#undef EXTERN +#define EXTERN extern +#endif + +/* miscellaneous stuff assumed to exist */ + +extern rtems_configuration_table BSP_Configuration; + +extern m68k_isr_entry M68Kvec[]; /* vector table address */ + +/* functions */ + +void bsp_cleanup( void ); + +m68k_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/m68k/gen68302/include/coverhd.h b/c/src/lib/libbsp/m68k/gen68302/include/coverhd.h new file mode 100644 index 0000000000..e41c72bf33 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/include/coverhd.h @@ -0,0 +1,115 @@ +/* coverhd.h + * + * This include file has defines to represent the overhead associated + * with calling a particular directive from C. These are used in the + * Timing Test Suite to ignore the overhead required to pass arguments + * to directives. On some CPUs and/or target boards, this overhead + * is significant and makes it difficult to distinguish internal + * RTEMS execution time from that used to call the directive. + * This file should be updated after running the C overhead timing + * test. Once this update has been performed, the RTEMS Time Test + * Suite should be rebuilt to account for these overhead times in the + * timing results. + * + * NOTE: If these are all zero, then the times reported include all + * all calling overhead including passing of arguments. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#ifndef __COVERHD_h +#define __COVERHD_h + +#ifdef __cplusplus +extern "C" { +#endif + +#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 14 +#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 11 +#define CALLING_OVERHEAD_TASK_CREATE 22 +#define CALLING_OVERHEAD_TASK_IDENT 17 +#define CALLING_OVERHEAD_TASK_START 18 +#define CALLING_OVERHEAD_TASK_RESTART 15 +#define CALLING_OVERHEAD_TASK_DELETE 12 +#define CALLING_OVERHEAD_TASK_SUSPEND 12 +#define CALLING_OVERHEAD_TASK_RESUME 12 +#define CALLING_OVERHEAD_TASK_SET_PRIORITY 16 +#define CALLING_OVERHEAD_TASK_MODE 15 +#define CALLING_OVERHEAD_TASK_GET_NOTE 16 +#define CALLING_OVERHEAD_TASK_SET_NOTE 16 +#define CALLING_OVERHEAD_TASK_WAKE_WHEN 31 +#define CALLING_OVERHEAD_TASK_WAKE_AFTER 11 +#define CALLING_OVERHEAD_INTERRUPT_CATCH 17 +#define CALLING_OVERHEAD_CLOCK_GET 32 +#define CALLING_OVERHEAD_CLOCK_SET 31 +#define CALLING_OVERHEAD_CLOCK_TICK 8 + +#define CALLING_OVERHEAD_TIMER_CREATE 13 +#define CALLING_OVERHEAD_TIMER_IDENT 12 +#define CALLING_OVERHEAD_TIMER_DELETE 14 +#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 19 +#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 39 +#define CALLING_OVERHEAD_TIMER_RESET 12 +#define CALLING_OVERHEAD_TIMER_CANCEL 12 +#define CALLING_OVERHEAD_SEMAPHORE_CREATE 18 +#define CALLING_OVERHEAD_SEMAPHORE_IDENT 12 +#define CALLING_OVERHEAD_SEMAPHORE_DELETE 17 +#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 17 +#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 12 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 18 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 17 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 12 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 14 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 14 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 17 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 19 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 14 + +#define CALLING_OVERHEAD_EVENT_SEND 15 +#define CALLING_OVERHEAD_EVENT_RECEIVE 18 +#define CALLING_OVERHEAD_SIGNAL_CATCH 14 +#define CALLING_OVERHEAD_SIGNAL_SEND 14 +#define CALLING_OVERHEAD_PARTITION_CREATE 23 +#define CALLING_OVERHEAD_PARTITION_IDENT 17 +#define CALLING_OVERHEAD_PARTITION_DELETE 12 +#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 15 +#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 15 +#define CALLING_OVERHEAD_REGION_CREATE 23 +#define CALLING_OVERHEAD_REGION_IDENT 14 +#define CALLING_OVERHEAD_REGION_DELETE 12 +#define CALLING_OVERHEAD_REGION_GET_SEGMENT 21 +#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 15 +#define CALLING_OVERHEAD_PORT_CREATE 20 +#define CALLING_OVERHEAD_PORT_IDENT 14 +#define CALLING_OVERHEAD_PORT_DELETE 12 +#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 18 +#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 18 + +#define CALLING_OVERHEAD_IO_INITIALIZE 18 +#define CALLING_OVERHEAD_IO_OPEN 18 +#define CALLING_OVERHEAD_IO_CLOSE 18 +#define CALLING_OVERHEAD_IO_READ 18 +#define CALLING_OVERHEAD_IO_WRITE 18 +#define CALLING_OVERHEAD_IO_CONTROL 18 +#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 11 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 13 +#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 14 +#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 12 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 12 +#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 14 +#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 8 + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/m68k/gen68302/start/start302.s b/c/src/lib/libbsp/m68k/gen68302/start/start302.s new file mode 100644 index 0000000000..2682066e84 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/start/start302.s @@ -0,0 +1,273 @@ +/* entry.s + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include "asm.h" + + .set BAR, 0xF2 | Base Address Register location + .set SCR, 0xF4 | System Control Register location + .set BAR_VAL, 0x0f7f | BAR value + .set SCR_VAL, 0x00080f00 | SCR value + .set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN). + .set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address + + .set oSYSRAM, 0x000 | 576 bytes of internal system RAM + + .set oGIMR, 0x812 + + .set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg + .set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg + .set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg + .set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg + .set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg + .set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg + .set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg + .set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg + + .set tmpSRAM_BASE, 0x400000 | start of temporary SRAM + .set FLASH_BASE, 0xc00000 | start of FLASH''s normal location + + +BEGIN_CODE + PUBLIC (M68Kvec) | Vector Table +SYM (M68Kvec): | standard location for vectors +V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP +V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC +V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error +V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error + .space 240 | reserve space for reset of vectors + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) +SYM (lowintstack): + .space 4092 | reserve for interrupt stack +SYM (hiintstack): + .space 4 | end of interrupt stack +#endif + + PUBLIC (start) | Default entry point for GNU +SYM (start): + move.w #0x2700,sr | Disable all interrupts + move.w #BAR_VAL,BAR | Set Base Address Register + move.l #SCR_VAL,SCR | Set System Control Register + lea BaseAddr,a5 + move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register + +| +| Set up chip select registers for the remapping process. +| + +| +| 0 X x x x x +| 0 000 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH) + move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS + +| +| X x x x x x +| 0 100 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM) + move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS + +| +| Copy the initial boot FLASH area to the temporary SRAM location. +| + moveq #0,d0 + movea.l d0,a0 | a0 -> start of FLASH + lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM +| moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy + moveq #127,d0 +cpy_flash: move.l (a0)+,(a1)+ | copy + subq.l #1,d0 + bne cpy_flash + +| +| Copy remap code to 68302''s internal system RAM. +| + movea.w #begRemap-V___ISSP,a0 | a0 -> remap code + lea a5@(oSYSRAM),a1 | a1 -> internal system RAM +| moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy + moveq #11,d0 +cpy_remap: move.w (a0)+,(a1)+ | copy + dbra d0,cpy_remap + +| +| Jump to the remap code in the 68302''s internal system RAM. +| + jmp a5@(oSYSRAM) | (effectively a jmp begRemap) + +| +| This remap code, when executed from the 68302''s internal system RAM +| will 1) remap CS1 so that SRAM is at 0 +| 2) remap CS0 so that FLASH is at FLASH_BASE +| and 3) jump to executable code in the remapped FLASH. +| +begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM) + move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH) + lea FLASH_BASE,a0 + jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH +endRemap: +| +| Now set up the remaining chip select registers. +| + +| +| 4 0 x x x x +| 1 000 1 111 0 000 0--- ---- ---- +| x xxx x xxx x xx +| + move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM) + move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS + +| +| 8 X x x x x +| 1 000 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO) + move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS + +endPreBoot: + + move.b #0x30,0x800001 | set status LED amber + + .set oPIOB_Ctrl, 0x824 + .set oPIOB_DDR, 0x826 + .set oPIOB_Data, 0x828 + + .set oPIOA_Ctrl, 0x81e + .set oPIOA_DDR, 0x820 + .set oPIOA_Data, 0x822 + + move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors. + move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output. + move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated + | peripheral pins. + + move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors. + move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output. + move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated + | peripheral pins. + +| +| Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4 +| are not set because they are the 68302''s BAR and SCR. +| + movea.w #0x010,a0 + moveq #(0x0f0-0x010)/4-1,d0 + move.l #Bad,d1 +cpy_Bad: move.l d1,(a0)+ + dbra d0,cpy_Bad + + .set vbase, 0x0200 + + lea vbase,a0 + moveq #31,d0 +cpy_Bad1: move.l d1,(a0)+ + dbra d0,cpy_Bad1 + +| +| Fill in special locations to configure OS +| + move.l #Bad,0x008 | Bus Error + move.l #Bad,0x00c | Address Error + move.l #Bad,0x024 | Trace +| move.l #KE_IRET,$0b4 | pSOS+ RET_I Call + +| move.l #_cnsl_isr,vbase+0x028 | SCC2 + move.l #timerisr,vbase+0x018 | Timer ISR + move.l #RTC_ISR,vbase+0x024 | Real Time Clock ISR + + | + | zero out uninitialized data area + | +zerobss: + moveal # SYM (end),a0 | find end of .bss + moveal # SYM (bss_start),a1 | find beginning of .bss + moveq #0,d0 + +loop: movel d0,a1@+ | to zero out uninitialized + cmpal a0,a1 + jlt loop | loop until _end reached + + movel # SYM (end),d0 | d0 = end of bss/start of heap + addl # SYM (heap_size),d0 | d0 = end of heap + movel d0, SYM (stack_start) | Save for brk() routine + addl # SYM (stack_size),d0 | make room for stack + andl #0xffffffc0,d0 | align it on 16 byte boundary + movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! + movel d0,a7 | set master stack pointer + movel d0,a6 | set base pointer + + /* + * RTEMS should maintiain a separate interrupt stack on CPUs + * without one in hardware. This is currently not supported + * on versions of the m68k without a HW intr stack. + */ + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + lea SYM (hiintstack),a0 | a0 = high end of intr stack + movec a0,isp | set interrupt stack +#endif + + jsr SYM (bsp_start) + + nop +Bad: bra Bad + + nop +RTC_ISR: + movem.l d0-d1/a0-a1,a7@- | save d0-d1,a0-a1 + addql #1,_ISR_Nest_level | one nest level deeper + addql #1,_Thread_Dispatch_disable_level + | disable multitasking + + jbsr Clock_isr | invoke the user ISR + jmp _ISR_Exit +END_CODE + + +BEGIN_DATA + + PUBLIC (start_frame) +SYM (start_frame): + .space 4,0 + + PUBLIC (stack_start) +SYM (stack_start): + .space 4,0 +END_DATA + +BEGIN_BSS + + PUBLIC (environ) + .align 2 +SYM (environ): + .long 0 + + PUBLIC (heap_size) + .set SYM (heap_size),0x2000 + + PUBLIC (stack_size) + .set SYM (stack_size),0x1000 + + +END_DATA +END diff --git a/c/src/lib/libbsp/m68k/gen68302/start302/start302.s b/c/src/lib/libbsp/m68k/gen68302/start302/start302.s new file mode 100644 index 0000000000..2682066e84 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/start302/start302.s @@ -0,0 +1,273 @@ +/* entry.s + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include "asm.h" + + .set BAR, 0xF2 | Base Address Register location + .set SCR, 0xF4 | System Control Register location + .set BAR_VAL, 0x0f7f | BAR value + .set SCR_VAL, 0x00080f00 | SCR value + .set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN). + .set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address + + .set oSYSRAM, 0x000 | 576 bytes of internal system RAM + + .set oGIMR, 0x812 + + .set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg + .set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg + .set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg + .set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg + .set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg + .set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg + .set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg + .set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg + + .set tmpSRAM_BASE, 0x400000 | start of temporary SRAM + .set FLASH_BASE, 0xc00000 | start of FLASH''s normal location + + +BEGIN_CODE + PUBLIC (M68Kvec) | Vector Table +SYM (M68Kvec): | standard location for vectors +V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP +V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC +V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error +V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error + .space 240 | reserve space for reset of vectors + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) +SYM (lowintstack): + .space 4092 | reserve for interrupt stack +SYM (hiintstack): + .space 4 | end of interrupt stack +#endif + + PUBLIC (start) | Default entry point for GNU +SYM (start): + move.w #0x2700,sr | Disable all interrupts + move.w #BAR_VAL,BAR | Set Base Address Register + move.l #SCR_VAL,SCR | Set System Control Register + lea BaseAddr,a5 + move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register + +| +| Set up chip select registers for the remapping process. +| + +| +| 0 X x x x x +| 0 000 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH) + move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS + +| +| X x x x x x +| 0 100 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM) + move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS + +| +| Copy the initial boot FLASH area to the temporary SRAM location. +| + moveq #0,d0 + movea.l d0,a0 | a0 -> start of FLASH + lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM +| moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy + moveq #127,d0 +cpy_flash: move.l (a0)+,(a1)+ | copy + subq.l #1,d0 + bne cpy_flash + +| +| Copy remap code to 68302''s internal system RAM. +| + movea.w #begRemap-V___ISSP,a0 | a0 -> remap code + lea a5@(oSYSRAM),a1 | a1 -> internal system RAM +| moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy + moveq #11,d0 +cpy_remap: move.w (a0)+,(a1)+ | copy + dbra d0,cpy_remap + +| +| Jump to the remap code in the 68302''s internal system RAM. +| + jmp a5@(oSYSRAM) | (effectively a jmp begRemap) + +| +| This remap code, when executed from the 68302''s internal system RAM +| will 1) remap CS1 so that SRAM is at 0 +| 2) remap CS0 so that FLASH is at FLASH_BASE +| and 3) jump to executable code in the remapped FLASH. +| +begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM) + move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH) + lea FLASH_BASE,a0 + jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH +endRemap: +| +| Now set up the remaining chip select registers. +| + +| +| 4 0 x x x x +| 1 000 1 111 0 000 0--- ---- ---- +| x xxx x xxx x xx +| + move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM) + move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS + +| +| 8 X x x x x +| 1 000 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO) + move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS + +endPreBoot: + + move.b #0x30,0x800001 | set status LED amber + + .set oPIOB_Ctrl, 0x824 + .set oPIOB_DDR, 0x826 + .set oPIOB_Data, 0x828 + + .set oPIOA_Ctrl, 0x81e + .set oPIOA_DDR, 0x820 + .set oPIOA_Data, 0x822 + + move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors. + move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output. + move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated + | peripheral pins. + + move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors. + move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output. + move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated + | peripheral pins. + +| +| Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4 +| are not set because they are the 68302''s BAR and SCR. +| + movea.w #0x010,a0 + moveq #(0x0f0-0x010)/4-1,d0 + move.l #Bad,d1 +cpy_Bad: move.l d1,(a0)+ + dbra d0,cpy_Bad + + .set vbase, 0x0200 + + lea vbase,a0 + moveq #31,d0 +cpy_Bad1: move.l d1,(a0)+ + dbra d0,cpy_Bad1 + +| +| Fill in special locations to configure OS +| + move.l #Bad,0x008 | Bus Error + move.l #Bad,0x00c | Address Error + move.l #Bad,0x024 | Trace +| move.l #KE_IRET,$0b4 | pSOS+ RET_I Call + +| move.l #_cnsl_isr,vbase+0x028 | SCC2 + move.l #timerisr,vbase+0x018 | Timer ISR + move.l #RTC_ISR,vbase+0x024 | Real Time Clock ISR + + | + | zero out uninitialized data area + | +zerobss: + moveal # SYM (end),a0 | find end of .bss + moveal # SYM (bss_start),a1 | find beginning of .bss + moveq #0,d0 + +loop: movel d0,a1@+ | to zero out uninitialized + cmpal a0,a1 + jlt loop | loop until _end reached + + movel # SYM (end),d0 | d0 = end of bss/start of heap + addl # SYM (heap_size),d0 | d0 = end of heap + movel d0, SYM (stack_start) | Save for brk() routine + addl # SYM (stack_size),d0 | make room for stack + andl #0xffffffc0,d0 | align it on 16 byte boundary + movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! + movel d0,a7 | set master stack pointer + movel d0,a6 | set base pointer + + /* + * RTEMS should maintiain a separate interrupt stack on CPUs + * without one in hardware. This is currently not supported + * on versions of the m68k without a HW intr stack. + */ + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + lea SYM (hiintstack),a0 | a0 = high end of intr stack + movec a0,isp | set interrupt stack +#endif + + jsr SYM (bsp_start) + + nop +Bad: bra Bad + + nop +RTC_ISR: + movem.l d0-d1/a0-a1,a7@- | save d0-d1,a0-a1 + addql #1,_ISR_Nest_level | one nest level deeper + addql #1,_Thread_Dispatch_disable_level + | disable multitasking + + jbsr Clock_isr | invoke the user ISR + jmp _ISR_Exit +END_CODE + + +BEGIN_DATA + + PUBLIC (start_frame) +SYM (start_frame): + .space 4,0 + + PUBLIC (stack_start) +SYM (stack_start): + .space 4,0 +END_DATA + +BEGIN_BSS + + PUBLIC (environ) + .align 2 +SYM (environ): + .long 0 + + PUBLIC (heap_size) + .set SYM (heap_size),0x2000 + + PUBLIC (stack_size) + .set SYM (stack_size),0x1000 + + +END_DATA +END diff --git a/c/src/lib/libbsp/m68k/gen68302/startup/bspclean.c b/c/src/lib/libbsp/m68k/gen68302/startup/bspclean.c new file mode 100644 index 0000000000..ca498e7806 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/startup/bspclean.c @@ -0,0 +1,26 @@ +/* bsp_cleanup() + * + * This routine normally is part of start.s and usually returns + * control to a monitor. + * + * INPUT: NONE + * + * OUTPUT: NONE + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> + +void bsp_cleanup( void ) +{ +} diff --git a/c/src/lib/libbsp/m68k/gen68302/startup/bspstart.c b/c/src/lib/libbsp/m68k/gen68302/startup/bspstart.c new file mode 100644 index 0000000000..976046cf9f --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/startup/bspstart.c @@ -0,0 +1,169 @@ +/* bsp_start() + * + * This routine starts the application. It includes application, + * board, and monitor specific initialization and configuration. + * The generic CPU dependent initialization has been performed + * before this routine is invoked. + * + * INPUT: NONE + * + * OUTPUT: NONE + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> +#include <libcsupport.h> + + +/* + * The original table from the application and our copy of it with + * some changes. + */ + +extern rtems_configuration_table Configuration; +rtems_configuration_table BSP_Configuration; + +rtems_cpu_table Cpu_table; + +/* Initialize whatever libc we are using + * called from postdriver hook + */ + +void bsp_libc_init() +{ + extern int end; + rtems_unsigned32 heap_start; + + heap_start = (rtems_unsigned32) &end; + if (heap_start & (CPU_ALIGNMENT-1)) + heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); + + /* + * The last parameter to RTEMS_Malloc_Initialize is the "chunk" + * size which a multiple of will be requested on each sbrk() + * call by malloc(). A value of 0 indicates that sbrk() should + * not be called to extend the heap. + */ + + RTEMS_Malloc_Initialize((void *) heap_start, 64 * 1024, 0); + + /* + * Set up for the libc handling. + */ + + if (BSP_Configuration.ticks_per_timeslice > 0) + libc_init(1); /* reentrant if possible */ + else + libc_init(0); /* non-reentrant */ + + /* + * Initialize the stack bounds checker + */ + +#ifdef STACK_CHECKER_ON + Stack_check_Initialize(); +#endif +} + + +int bsp_start( + int argc, + char **argv, + char **environp +) +{ + /* + * Allocate the memory for the RTEMS Work Space. This can come from + * a variety of places: hard coded address, malloc'ed from outside + * RTEMS world (e.g. simulator or primitive memory manager), or (as + * typically done by stock BSPs) by subtracting the required amount + * of work space from the last physical address on the CPU board. + */ +#if 0 +a Cpu_table.interrupt_vector_table = (mc68000_isr *) 0/*&M68Kvec*/; +#endif + + + /* + * Copy the Configuration Table .. so we can change it + */ + + BSP_Configuration = Configuration; + + /* + * Add 1 region for the RTEMS Malloc + */ + + BSP_Configuration.maximum_regions++; + + /* + * Add 1 extension for newlib libc + */ + +#ifdef RTEMS_NEWLIB + BSP_Configuration.maximum_extensions++; +#endif + + /* + * Add another extension if using the stack checker + */ + +#ifdef STACK_CHECKER_ON + BSP_Configuration.maximum_extensions++; +#endif + + /* + * Need to "allocate" the memory for the RTEMS Workspace and + * tell the RTEMS configuration where it is. This memory is + * not malloc'ed. It is just "pulled from the air". + */ + + BSP_Configuration.work_space_start = (void *) + (RAM_END - BSP_Configuration.work_space_size); + + /* + * initialize the CPU table for this BSP + */ + + /* + * we do not use the pretasking_hook + */ + + Cpu_table.pretasking_hook = NULL; + + Cpu_table.predriver_hook = bsp_libc_init; /* RTEMS resources available */ + + Cpu_table.postdriver_hook = NULL; + + Cpu_table.idle_task = NULL; /* do not override system IDLE task */ + + Cpu_table.do_zero_of_workspace = TRUE; + + Cpu_table.interrupt_stack_size = 4096; + + Cpu_table.extra_system_initialization_stack = 0; + + /* + * Don't forget the other CPU Table entries. + */ + + /* + * Start RTEMS + */ + + rtems_initialize_executive( &BSP_Configuration, &Cpu_table ); + + bsp_cleanup(); + + return 0; +} diff --git a/c/src/lib/libbsp/m68k/gen68302/timer/timer.c b/c/src/lib/libbsp/m68k/gen68302/timer/timer.c new file mode 100644 index 0000000000..4d60b6a82b --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/timer/timer.c @@ -0,0 +1,130 @@ +/* Timer_init() + * + * This routine initializes TIMER 2 for an MC68302. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * NOTE: It is important that the timer start/stop overhead be + * determined when porting or modifying this code. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + + +#include <rtems.h> +#include <bsp.h> +#include "m68302.h" + + +#define TMR2_VAL 0x071b /* Timer mode register + * (section 3.5.2.1 in 68302 manual) + * 15-8: "7" prescaler divide by 8 (x+1) + * 7-6: 00 dis. intr. on capture event + * 5: 0 active-low pulse + * 4: 1 intr. on reaching reference + * 3: 1 restart counter on reference + * 2-1: 01 master clock input source + * 0: 1 enable timer + */ +#define TRR2_VAL 2000 /* Timer reference register + * (section 3.5.2.2 in 68302 manual) + * 2000 ticks @ (16MHz/1)/8 = 1-ms count + */ + +rtems_unsigned32 Timer_interrupts; + +rtems_boolean Timer_driver_Find_average_overhead; + +rtems_isr timerisr(); + +void Timer_initialize( void ) +{ + m302.reg.tmr2 = 0; /* disable timer */ + + Timer_interrupts = 0; /* clear timer ISR count */ + + m302.reg.trr2 = TRR2_VAL; /* set timer reference register */ + m302.reg.tmr2 = TMR2_VAL; /* set timer mode register */ + m302.reg.imr |= RBIT_IMR_TIMER2; /* set 68302 int-mask to allow ints */ +} + +/* + * The following controls the behavior of Read_timer(). + * + * FIND_AVG_OVERHEAD * instructs the routine to return the "raw" count. + * + * AVG_OVEREHAD is the overhead for starting and stopping the timer. It + * is usually deducted from the number returned. + * + * LEAST_VALID is the lowest number this routine should trust. Numbers + * below this are "noise" and zero is returned. + */ + +#define AVG_OVERHEAD 0 /* It typically takes X.X microseconds */ + /* (Y countdowns) to start/stop the timer. */ + /* This value is in microseconds. */ +#define LEAST_VALID 1 /* Don't trust a clicks value lower than this */ + +/* + * Return timer value in 1/2-microsecond units + */ +int Read_timer( void ) +{ + rtems_unsigned16 clicks; + rtems_unsigned32 total; + + /* + * Read the timer and see how many clicks it has been since counter + * rolled over. + */ + + clicks = m302.reg.tcn2; + + /* + * Total is calculated by taking into account the number of timer overflow + * interrupts since the timer was initialized and clicks since the last + * interrupts. + */ + + total = (Timer_interrupts * TRR2_VAL) + clicks; + + if ( Timer_driver_Find_average_overhead == 1 ) + return total; /* in XXX microsecond units */ + + if ( total < LEAST_VALID ) + return 0; /* below timer resolution */ + + /* + * Convert 1/2-microsecond count into microseconds + */ + + return (total - AVG_OVERHEAD) >> 1; +} + + +/* + * Empty function call used in loops to measure basic cost of looping + * in Timing Test Suite. + */ + +rtems_status_code Empty_function(void) +{ + return RTEMS_SUCCESSFUL; +} + +void Set_find_average_overhead( + rtems_boolean find_flag +) +{ + Timer_driver_Find_average_overhead = find_flag; +} diff --git a/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s b/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s new file mode 100644 index 0000000000..c804b9dfa6 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s @@ -0,0 +1,28 @@ +/* + * Handle 68302 TIMER2 interrupts. + * + * All code in this routine is pure overhead which can perturb the + * accuracy of RTEMS' timing test suite. + * + * See also: Read_timer() + * + * To reduce overhead this is best to be the "rawest" hardware interupt + * handler you can write. This should be the only interrupt which can + * occur during the measured time period. + * + * An external counter, Timer_interrupts, is incremented. + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + PUBLIC(timerisr) +SYM(timerisr): + move.w #0x0040,SYM(m302)+2072 | clear interrupt in-service bit + move.b #3,SYM(m302)+2137 | clear timer interrupt event register + addq.l #1,SYM(Timer_interrupts) | increment timer value + rte +END_CODE +END diff --git a/c/src/lib/libmisc/stackchk/check.c b/c/src/lib/libmisc/stackchk/check.c index 2d25f51f3e..ac15973815 100644 --- a/c/src/lib/libmisc/stackchk/check.c +++ b/c/src/lib/libmisc/stackchk/check.c @@ -329,7 +329,7 @@ void *Stack_check_find_high_water_mark( * match pattern */ - base += 4; + base += PATTERN_SIZE_WORDS; for (ebase = base + length; base < ebase; base++) if (*base != U32_PATTERN) return (void *) base; |