diff options
Diffstat (limited to '')
31 files changed, 689 insertions, 256 deletions
diff --git a/c/src/lib/include/ringbuf.h b/c/src/lib/include/ringbuf.h index b2494c1527..8c80aaf9c8 100644 --- a/c/src/lib/include/ringbuf.h +++ b/c/src/lib/include/ringbuf.h @@ -10,13 +10,13 @@ #define __RINGBUF_H__ #ifndef RINGBUF_QUEUE_LENGTH -#define RINGBUF_QUEUE_LENGTH 200 +#define RINGBUF_QUEUE_LENGTH 128 #endif typedef struct { char buffer[RINGBUF_QUEUE_LENGTH]; - int head; - int tail; + volatile int head; + volatile int tail; } Ring_buffer_t; #define Ring_buffer_Initialize( _buffer ) \ @@ -27,16 +27,27 @@ typedef struct { #define Ring_buffer_Is_empty( _buffer ) \ ( (_buffer)->head == (_buffer)->tail ) +#define Ring_buffer_Is_full( _buffer ) \ + ( (_buffer)->head == ((_buffer)->tail + 1) % RINGBUF_QUEUE_LENGTH ) + #define Ring_buffer_Add_character( _buffer, _ch ) \ do { \ - (_buffer)->buffer[ (_buffer)->tail ] = (_ch); \ - (_buffer)->tail = ((_buffer)->tail+1) % RINGBUF_QUEUE_LENGTH; \ + rtems_unsigned32 isrlevel; \ + \ + rtems_interrupt_disable( isrlevel ); \ + (_buffer)->tail = ((_buffer)->tail+1) % RINGBUF_QUEUE_LENGTH; \ + (_buffer)->buffer[ (_buffer)->tail ] = (_ch); \ + rtems_interrupt_enable( isrlevel ); \ } while ( 0 ) #define Ring_buffer_Remove_character( _buffer, _ch ) \ do { \ - (_ch) = (_buffer)->buffer[ (_buffer)->head ]; \ - (_buffer)->head = ((_buffer)->head+1) % RINGBUF_QUEUE_LENGTH; \ + rtems_unsigned32 isrlevel; \ + \ + rtems_interrupt_disable( isrlevel ); \ + (_buffer)->head = ((_buffer)->head+1) % RINGBUF_QUEUE_LENGTH; \ + (_ch) = (_buffer)->buffer[ (_buffer)->head ]; \ + rtems_interrupt_enable( isrlevel ); \ } while ( 0 ) #endif diff --git a/c/src/lib/libbsp/hppa1.1/simhppa/startup/bspstart.c b/c/src/lib/libbsp/hppa1.1/simhppa/startup/bspstart.c index 0c19667b1f..bfdb429ef8 100644 --- a/c/src/lib/libbsp/hppa1.1/simhppa/startup/bspstart.c +++ b/c/src/lib/libbsp/hppa1.1/simhppa/startup/bspstart.c @@ -29,7 +29,7 @@ #include <rtems.h> #include <bsp.h> #include <rtems/libio.h> -#include <rtems/score/intthrd.h> +#include <rtems/intthrd.h> #include <libcsupport.h> @@ -243,19 +243,22 @@ bsp_pretasking_hook(void) void bsp_postdriver_hook(void) { - int stdin_fd, stdout_fd, stderr_fd; - - if ((stdin_fd = __open("/dev/tty00", O_RDONLY, 0)) == -1) - rtems_fatal_error_occurred('STD0'); - - if ((stdout_fd = __open("/dev/tty00", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD1'); - - if ((stderr_fd = __open("/dev/tty00", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD2'); - - if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) - rtems_fatal_error_occurred('STIO'); + int stdin_fd, stdout_fd, stderr_fd; + int error_code; + + error_code = 'S' << 24 | 'T' << 16; + + if ((stdin_fd = __open("/dev/console", O_RDONLY, 0)) == -1) + rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); + + if ((stdout_fd = __open("/dev/console", O_WRONLY, 0)) == -1) + rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); + + if ((stderr_fd = __open("/dev/console", O_WRONLY, 0)) == -1) + rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); + + if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) + rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); } /* diff --git a/c/src/lib/libbsp/i386/force386/clock/ckinit.c b/c/src/lib/libbsp/i386/force386/clock/ckinit.c index 45a64f6f14..9bfad8991a 100644 --- a/c/src/lib/libbsp/i386/force386/clock/ckinit.c +++ b/c/src/lib/libbsp/i386/force386/clock/ckinit.c @@ -75,17 +75,6 @@ void Install_clock( atexit( Clock_exit ); } -void ReInstall_clock( - rtems_isr_entry clock_isr -) -{ - rtems_unsigned32 isrlevel = 0; - - rtems_interrupt_disable( isrlevel ); - (void) set_vector( clock_isr, CLOCK_VECTOR, 1 ); - rtems_interrupt_enable( isrlevel ); -} - void Clock_exit( void ) { if ( BSP_Configuration.ticks_per_timeslice ) { @@ -119,6 +108,7 @@ rtems_device_driver Clock_control( void *pargp ) { + rtems_unsigned32 isrlevel; rtems_libio_ioctl_args_t *args = pargp; if (args == 0) @@ -135,7 +125,9 @@ rtems_device_driver Clock_control( } else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { - ReInstall_clock(args->buffer); + rtems_interrupt_disable( isrlevel ); + (void) set_vector( args->buffer, CLOCK_VECTOR, 1 ); + rtems_interrupt_enable( isrlevel ); } done: diff --git a/c/src/lib/libbsp/i386/force386/startup/bspstart.c b/c/src/lib/libbsp/i386/force386/startup/bspstart.c index 1433e5e02a..3f001fb109 100644 --- a/c/src/lib/libbsp/i386/force386/startup/bspstart.c +++ b/c/src/lib/libbsp/i386/force386/startup/bspstart.c @@ -122,18 +122,21 @@ void bsp_postdriver_hook(void) { int stdin_fd, stdout_fd, stderr_fd; + int error_code; + + error_code = 'S' << 24 | 'T' << 16; if ((stdin_fd = __open("/dev/console", O_RDONLY, 0)) == -1) - rtems_fatal_error_occurred('STD0'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); if ((stdout_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD1'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); if ((stderr_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD2'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) - rtems_fatal_error_occurred('STIO'); + rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); } int main( diff --git a/c/src/lib/libbsp/i386/go32/clock/ckinit.c b/c/src/lib/libbsp/i386/go32/clock/ckinit.c index fa6a8bf057..70c564fabc 100644 --- a/c/src/lib/libbsp/i386/go32/clock/ckinit.c +++ b/c/src/lib/libbsp/i386/go32/clock/ckinit.c @@ -108,17 +108,6 @@ void Install_clock( atexit( Clock_exit ); } -void ReInstall_clock( - rtems_isr_entry clock_isr -) -{ - rtems_unsigned32 isrlevel = 0; - - rtems_interrupt_disable( isrlevel ); - (void) set_vector( clock_isr, CLOCK_VECTOR, 1 ); - rtems_interrupt_enable( isrlevel ); -} - void Clock_exit( void ) { if ( BSP_Configuration.ticks_per_timeslice ) { @@ -161,6 +150,7 @@ rtems_device_driver Clock_control( void *pargp ) { + rtems_unsigned32 isrlevel; rtems_libio_ioctl_args_t *args = pargp; if (args == 0) @@ -177,7 +167,9 @@ rtems_device_driver Clock_control( } else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { - ReInstall_clock(args->buffer); + rtems_interrupt_disable( isrlevel ); + (void) set_vector( args->buffer, CLOCK_VECTOR, 1 ); + rtems_interrupt_enable( isrlevel ); } done: diff --git a/c/src/lib/libbsp/i386/go32/startup/bspstart.c b/c/src/lib/libbsp/i386/go32/startup/bspstart.c index 17a10b4193..602b7bdfd6 100644 --- a/c/src/lib/libbsp/i386/go32/startup/bspstart.c +++ b/c/src/lib/libbsp/i386/go32/startup/bspstart.c @@ -129,18 +129,21 @@ void bsp_postdriver_hook(void) { int stdin_fd, stdout_fd, stderr_fd; + int error_code; + + error_code = 'S' << 24 | 'T' << 16; if ((stdin_fd = __open("/dev/console", O_RDONLY, 0)) == -1) - rtems_fatal_error_occurred('STD0'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); if ((stdout_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD1'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); if ((stderr_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD2'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) - rtems_fatal_error_occurred('STIO'); + rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); } /* This is the original command line passed from DOS */ diff --git a/c/src/lib/libbsp/i960/cvme961/clock/ckinit.c b/c/src/lib/libbsp/i960/cvme961/clock/ckinit.c index b479ad137c..3f2ba718bc 100644 --- a/c/src/lib/libbsp/i960/cvme961/clock/ckinit.c +++ b/c/src/lib/libbsp/i960/cvme961/clock/ckinit.c @@ -60,13 +60,6 @@ void Install_clock( } } -void ReInstall_clock( - rtems_isr_entry clock_isr -) -{ - (void) set_vector( clock_isr, CLOCK_VECTOR, 1 ); -} - void Clock_exit() { unsigned char *victimer; @@ -105,6 +98,7 @@ rtems_device_driver Clock_control( void *pargp ) { + rtems_unsigned32 isrlevel; rtems_libio_ioctl_args_t *args = pargp; if (args == 0) @@ -121,7 +115,9 @@ rtems_device_driver Clock_control( } else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { - ReInstall_clock(args->buffer); + rtems_interrupt_disable( isrlevel ); + (void) set_vector( args->buffer, CLOCK_VECTOR, 1 ); + rtems_interrupt_enable( isrlevel ); } done: diff --git a/c/src/lib/libbsp/i960/cvme961/startup/bspstart.c b/c/src/lib/libbsp/i960/cvme961/startup/bspstart.c index ec4f8b601d..1c9c29f29e 100644 --- a/c/src/lib/libbsp/i960/cvme961/startup/bspstart.c +++ b/c/src/lib/libbsp/i960/cvme961/startup/bspstart.c @@ -124,18 +124,21 @@ void bsp_postdriver_hook(void) { int stdin_fd, stdout_fd, stderr_fd; + int error_code; + + error_code = 'S' << 24 | 'T' << 16; if ((stdin_fd = __open("/dev/console", O_RDONLY, 0)) == -1) - rtems_fatal_error_occurred('STD0'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); if ((stdout_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD1'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); if ((stderr_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD2'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) - rtems_fatal_error_occurred('STIO'); + rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); } int main( diff --git a/c/src/lib/libbsp/m68k/dmv152/clock/ckinit.c b/c/src/lib/libbsp/m68k/dmv152/clock/ckinit.c index 8715cdcc26..128bed84d7 100644 --- a/c/src/lib/libbsp/m68k/dmv152/clock/ckinit.c +++ b/c/src/lib/libbsp/m68k/dmv152/clock/ckinit.c @@ -97,17 +97,6 @@ void Install_clock( } } -void ReInstall_clock( - rtems_isr_entry clock_isr -) -{ - rtems_unsigned32 isrlevel = 0 ; - - rtems_interrupt_disable( isrlevel ); - (void) set_vector( clock_isr, CLOCK_VECTOR, 1 ); - rtems_interrupt_enable( isrlevel ); -} - void Clock_exit( void ) { rtems_unsigned8 data; @@ -145,6 +134,7 @@ rtems_device_driver Clock_control( void *pargp ) { + rtems_unsigned32 isrlevel; rtems_libio_ioctl_args_t *args = pargp; if (args == 0) @@ -161,7 +151,9 @@ rtems_device_driver Clock_control( } else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { - ReInstall_clock(args->buffer); + rtems_interrupt_disable( isrlevel ); + (void) set_vector( args->buffer, CLOCK_VECTOR, 1 ); + rtems_interrupt_enable( isrlevel ); } done: diff --git a/c/src/lib/libbsp/m68k/dmv152/startup/bspstart.c b/c/src/lib/libbsp/m68k/dmv152/startup/bspstart.c index 44ad6b6f7e..0f0ecbf00d 100644 --- a/c/src/lib/libbsp/m68k/dmv152/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/dmv152/startup/bspstart.c @@ -123,18 +123,21 @@ void bsp_postdriver_hook(void) { int stdin_fd, stdout_fd, stderr_fd; + int error_code; + + error_code = 'S' << 24 | 'T' << 16; if ((stdin_fd = __open("/dev/console", O_RDONLY, 0)) == -1) - rtems_fatal_error_occurred('STD0'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); if ((stdout_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD1'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); if ((stderr_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD2'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) - rtems_fatal_error_occurred('STIO'); + rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); } int main( diff --git a/c/src/lib/libbsp/m68k/efi332/clock/ckinit.c b/c/src/lib/libbsp/m68k/efi332/clock/ckinit.c index 2bfa34d32d..8b46fc283d 100644 --- a/c/src/lib/libbsp/m68k/efi332/clock/ckinit.c +++ b/c/src/lib/libbsp/m68k/efi332/clock/ckinit.c @@ -70,17 +70,6 @@ void Install_clock( } } -void ReInstall_clock( - rtems_isr_entry clock_isr -) -{ - rtems_unsigned32 isrlevel = 0 ; - - rtems_interrupt_disable( isrlevel ); - (void) set_vector( clock_isr, CLOCK_VECTOR, 1 ); - rtems_interrupt_enable( isrlevel ); -} - void Clock_exit( void ) { @@ -120,6 +109,7 @@ rtems_device_driver Clock_control( void *pargp ) { + rtems_unsigned32 isrlevel; rtems_libio_ioctl_args_t *args = pargp; if (args == 0) @@ -136,7 +126,9 @@ rtems_device_driver Clock_control( } else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { - ReInstall_clock(args->buffer); + rtems_interrupt_disable( isrlevel ); + (void) set_vector( args->buffer, CLOCK_VECTOR, 1 ); + rtems_interrupt_enable( isrlevel ); } done: diff --git a/c/src/lib/libbsp/m68k/efi332/startup/bspstart.c b/c/src/lib/libbsp/m68k/efi332/startup/bspstart.c index 6a7830bcfe..7a291ef02e 100644 --- a/c/src/lib/libbsp/m68k/efi332/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/efi332/startup/bspstart.c @@ -123,18 +123,21 @@ void bsp_postdriver_hook(void) { int stdin_fd, stdout_fd, stderr_fd; + int error_code; + + error_code = 'S' << 24 | 'T' << 16; if ((stdin_fd = __open("/dev/console", O_RDONLY, 0)) == -1) - rtems_fatal_error_occurred('STD0'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); if ((stdout_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD1'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); if ((stderr_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD2'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) - rtems_fatal_error_occurred('STIO'); + rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); } int main( diff --git a/c/src/lib/libbsp/m68k/efi68k/clock/ckinit.c b/c/src/lib/libbsp/m68k/efi68k/clock/ckinit.c index c90eba1e22..9c698cd0ba 100644 --- a/c/src/lib/libbsp/m68k/efi68k/clock/ckinit.c +++ b/c/src/lib/libbsp/m68k/efi68k/clock/ckinit.c @@ -93,17 +93,6 @@ void Install_clock( } } -void ReInstall_clock( - rtems_isr_entry clock_isr -) -{ - rtems_unsigned32 isrlevel = 0 ; - - rtems_interrupt_disable( isrlevel ); - (void) set_vector( clock_isr, CLOCK_VECTOR, 1 ); - rtems_interrupt_enable( isrlevel ); -} - void Clock_exit( void ) { @@ -141,6 +130,7 @@ rtems_device_driver Clock_control( void *pargp ) { + rtems_unsigned32 isrlevel; rtems_libio_ioctl_args_t *args = pargp; if (args == 0) @@ -157,7 +147,9 @@ rtems_device_driver Clock_control( } else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { - ReInstall_clock(args->buffer); + rtems_interrupt_disable( isrlevel ); + (void) set_vector( args->buffer, CLOCK_VECTOR, 1 ); + rtems_interrupt_enable( isrlevel ); } done: diff --git a/c/src/lib/libbsp/m68k/efi68k/startup/bspstart.c b/c/src/lib/libbsp/m68k/efi68k/startup/bspstart.c index e08f78baff..366a6502e7 100644 --- a/c/src/lib/libbsp/m68k/efi68k/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/efi68k/startup/bspstart.c @@ -130,18 +130,21 @@ void bsp_postdriver_hook(void) { int stdin_fd, stdout_fd, stderr_fd; + int error_code; + + error_code = 'S' << 24 | 'T' << 16; if ((stdin_fd = __open("/dev/console", O_RDONLY, 0)) == -1) - rtems_fatal_error_occurred('STD0'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); if ((stdout_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD1'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); if ((stderr_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD2'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) - rtems_fatal_error_occurred('STIO'); + rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); } int main( diff --git a/c/src/lib/libbsp/m68k/gen68302/clock/ckinit.c b/c/src/lib/libbsp/m68k/gen68302/clock/ckinit.c index f842bbc83c..386fc026a7 100644 --- a/c/src/lib/libbsp/m68k/gen68302/clock/ckinit.c +++ b/c/src/lib/libbsp/m68k/gen68302/clock/ckinit.c @@ -89,7 +89,7 @@ void Install_clock( Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000; if ( BSP_Configuration.ticks_per_timeslice ) { -/* set_vector( clock_isr, CLOCK_VECTOR, 1 );*/ + set_vector( clock_isr, CLOCK_VECTOR, 1 ); m302.reg.trr1 = TRR1_VAL; /* set timer reference register */ m302.reg.tmr1 = TMR1_VAL; /* set timer mode register & enable */ @@ -102,17 +102,6 @@ void Install_clock( } } -void ReInstall_clock( - rtems_isr_entry clock_isr -) -{ - rtems_unsigned32 isrlevel; - - rtems_interrupt_disable( isrlevel ); - /* (void) set_vector( clock_isr, CLOCK_VECTOR, 1 ); */ - rtems_interrupt_enable( isrlevel ); -} - void Clock_exit( void ) { if ( BSP_Configuration.ticks_per_timeslice ) { @@ -145,6 +134,7 @@ rtems_device_driver Clock_control( void *pargp ) { + rtems_unsigned32 isrlevel; rtems_libio_ioctl_args_t *args = pargp; if (args == 0) @@ -161,7 +151,9 @@ rtems_device_driver Clock_control( } else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { - ReInstall_clock(args->buffer); + rtems_interrupt_disable( isrlevel ); + (void) set_vector( args->buffer, CLOCK_VECTOR, 1 ); + rtems_interrupt_enable( isrlevel ); } done: diff --git a/c/src/lib/libbsp/m68k/gen68302/start/start302.s b/c/src/lib/libbsp/m68k/gen68302/start/start302.s index d92ed1ce6b..311cd3fa39 100644 --- a/c/src/lib/libbsp/m68k/gen68302/start/start302.s +++ b/c/src/lib/libbsp/m68k/gen68302/start/start302.s @@ -193,7 +193,6 @@ cpy_Bad1: move.l d1,(a0)+ | move.l #_cnsl_isr,vbase+0x028 | SCC2 move.l #timerisr,vbase+0x018 | Timer ISR - move.l #RTC_ISR,vbase+0x024 | Real Time Clock ISR | | zero out uninitialized data area @@ -236,14 +235,6 @@ loop: movel d0,a1@+ | to zero out uninitialized Bad: bra Bad nop -RTC_ISR: - movem.l d0-d1/a0-a1,a7@- | save d0-d1,a0-a1 - addql #1,_ISR_Nest_level | one nest level deeper - addql #1,_Thread_Dispatch_disable_level - | disable multitasking - - jbsr Clock_isr | invoke the user ISR - jmp _ISR_Exit END_CODE diff --git a/c/src/lib/libbsp/m68k/gen68302/start302/start302.s b/c/src/lib/libbsp/m68k/gen68302/start302/start302.s index d92ed1ce6b..311cd3fa39 100644 --- a/c/src/lib/libbsp/m68k/gen68302/start302/start302.s +++ b/c/src/lib/libbsp/m68k/gen68302/start302/start302.s @@ -193,7 +193,6 @@ cpy_Bad1: move.l d1,(a0)+ | move.l #_cnsl_isr,vbase+0x028 | SCC2 move.l #timerisr,vbase+0x018 | Timer ISR - move.l #RTC_ISR,vbase+0x024 | Real Time Clock ISR | | zero out uninitialized data area @@ -236,14 +235,6 @@ loop: movel d0,a1@+ | to zero out uninitialized Bad: bra Bad nop -RTC_ISR: - movem.l d0-d1/a0-a1,a7@- | save d0-d1,a0-a1 - addql #1,_ISR_Nest_level | one nest level deeper - addql #1,_Thread_Dispatch_disable_level - | disable multitasking - - jbsr Clock_isr | invoke the user ISR - jmp _ISR_Exit END_CODE diff --git a/c/src/lib/libbsp/m68k/gen68302/startup/bspstart.c b/c/src/lib/libbsp/m68k/gen68302/startup/bspstart.c index 94973ea4cc..af512c0d8e 100644 --- a/c/src/lib/libbsp/m68k/gen68302/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/gen68302/startup/bspstart.c @@ -130,18 +130,21 @@ void bsp_postdriver_hook(void) { int stdin_fd, stdout_fd, stderr_fd; + int error_code; + + error_code = 'S' << 24 | 'T' << 16; if ((stdin_fd = __open("/dev/console", O_RDONLY, 0)) == -1) - rtems_fatal_error_occurred('STD0'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); if ((stdout_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD1'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); if ((stderr_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD2'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) - rtems_fatal_error_occurred('STIO'); + rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); } int main( diff --git a/c/src/lib/libbsp/m68k/idp/clock/ckinit.c b/c/src/lib/libbsp/m68k/idp/clock/ckinit.c index 7966fc61d1..6d93523563 100644 --- a/c/src/lib/libbsp/m68k/idp/clock/ckinit.c +++ b/c/src/lib/libbsp/m68k/idp/clock/ckinit.c @@ -130,16 +130,6 @@ rtems_isr_entry clock_isr; } } -void ReInstall_clock( clock_isr ) -rtems_isr_entry clock_isr; -{ - rtems_unsigned32 isrlevel = 0 ; - - rtems_interrupt_disable( isrlevel ); - (void) set_vector( clock_isr, CLOCK_VECTOR, 1 ); - rtems_interrupt_enable( isrlevel ); -} - /* The following was added for debugging purposes */ void Clock_exit( void ) { @@ -181,6 +171,7 @@ rtems_device_driver Clock_control( void *pargp ) { + rtems_unsigned32 isrlevel; rtems_libio_ioctl_args_t *args = pargp; if (args == 0) @@ -197,7 +188,9 @@ rtems_device_driver Clock_control( } else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { - ReInstall_clock(args->buffer); + rtems_interrupt_disable( isrlevel ); + (void) set_vector( args->buffer, CLOCK_VECTOR, 1 ); + rtems_interrupt_enable( isrlevel ); } done: diff --git a/c/src/lib/libbsp/m68k/idp/console/duart.c b/c/src/lib/libbsp/m68k/idp/console/duart.c index fe4b657b37..2d82590a49 100644 --- a/c/src/lib/libbsp/m68k/idp/console/duart.c +++ b/c/src/lib/libbsp/m68k/idp/console/duart.c @@ -1,6 +1,6 @@ -# -# $Id$ -# +/* + * $Id$ + */ /*######################################################### # diff --git a/c/src/lib/libbsp/m68k/idp/startup/bspstart.c b/c/src/lib/libbsp/m68k/idp/startup/bspstart.c index b4f4928f7d..9c79960580 100644 --- a/c/src/lib/libbsp/m68k/idp/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/idp/startup/bspstart.c @@ -131,18 +131,21 @@ void bsp_postdriver_hook(void) { int stdin_fd, stdout_fd, stderr_fd; + int error_code; + + error_code = 'S' << 24 | 'T' << 16; if ((stdin_fd = __open("/dev/console", O_RDONLY, 0)) == -1) - rtems_fatal_error_occurred('STD0'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); if ((stdout_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD1'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); if ((stderr_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD2'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) - rtems_fatal_error_occurred('STIO'); + rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); } int main( diff --git a/c/src/lib/libbsp/m68k/mvme136/clock/ckinit.c b/c/src/lib/libbsp/m68k/mvme136/clock/ckinit.c index 61069a8627..0ba674aee9 100644 --- a/c/src/lib/libbsp/m68k/mvme136/clock/ckinit.c +++ b/c/src/lib/libbsp/m68k/mvme136/clock/ckinit.c @@ -108,17 +108,6 @@ void Install_clock( } -void ReInstall_clock( - rtems_isr_entry clock_isr -) -{ - rtems_unsigned32 isrlevel; - - rtems_interrupt_disable( isrlevel ); - (void) set_vector( clock_isr, CLOCK_VECTOR, 1 ); - rtems_interrupt_enable( isrlevel ); -} - void Clock_exit( void ) { volatile struct z8036_map *timer; @@ -157,6 +146,7 @@ rtems_device_driver Clock_control( void *pargp ) { + rtems_unsigned32 isrlevel; rtems_libio_ioctl_args_t *args = pargp; if (args == 0) @@ -173,7 +163,9 @@ rtems_device_driver Clock_control( } else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { - ReInstall_clock(args->buffer); + rtems_interrupt_disable( isrlevel ); + (void) set_vector( args->buffer, CLOCK_VECTOR, 1 ); + rtems_interrupt_enable( isrlevel ); } done: diff --git a/c/src/lib/libbsp/m68k/mvme136/startup/bspstart.c b/c/src/lib/libbsp/m68k/mvme136/startup/bspstart.c index 3465f72416..ea8eb56db6 100644 --- a/c/src/lib/libbsp/m68k/mvme136/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/mvme136/startup/bspstart.c @@ -124,18 +124,21 @@ void bsp_postdriver_hook(void) { int stdin_fd, stdout_fd, stderr_fd; - + int error_code; + + error_code = 'S' << 24 | 'T' << 16; + if ((stdin_fd = __open("/dev/console", O_RDONLY, 0)) == -1) - rtems_fatal_error_occurred('STD0'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); if ((stdout_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD1'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); if ((stderr_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD2'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) - rtems_fatal_error_occurred('STIO'); + rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); } diff --git a/c/src/lib/libbsp/m68k/mvme162/clock/ckinit.c b/c/src/lib/libbsp/m68k/mvme162/clock/ckinit.c index df0a13d52f..57afd71292 100644 --- a/c/src/lib/libbsp/m68k/mvme162/clock/ckinit.c +++ b/c/src/lib/libbsp/m68k/mvme162/clock/ckinit.c @@ -89,15 +89,6 @@ void Install_clock(rtems_isr_entry clock_isr ) } } -void ReInstall_clock(rtems_isr_entry clock_isr) -{ - rtems_unsigned32 isrlevel; - - rtems_interrupt_disable( isrlevel ); - (void) set_vector( clock_isr, CLOCK_VECTOR, 1 ); - rtems_interrupt_enable( isrlevel ); -} - void Clock_exit( void ) { /* Dummy for now. See other m68k BSP's for code examples */ @@ -127,6 +118,7 @@ rtems_device_driver Clock_control( void *pargp ) { + rtems_unsigned32 isrlevel; rtems_libio_ioctl_args_t *args = pargp; if (args == 0) @@ -143,7 +135,9 @@ rtems_device_driver Clock_control( } else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { - ReInstall_clock(args->buffer); + rtems_interrupt_disable( isrlevel ); + (void) set_vector( args->buffer, CLOCK_VECTOR, 1 ); + rtems_interrupt_enable( isrlevel ); } done: diff --git a/c/src/lib/libbsp/m68k/mvme162/startup/bspstart.c b/c/src/lib/libbsp/m68k/mvme162/startup/bspstart.c index 123cd413d2..211ce19032 100644 --- a/c/src/lib/libbsp/m68k/mvme162/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/mvme162/startup/bspstart.c @@ -130,18 +130,21 @@ void bsp_postdriver_hook(void) { int stdin_fd, stdout_fd, stderr_fd; + int error_code; + + error_code = 'S' << 24 | 'T' << 16; if ((stdin_fd = __open("/dev/console", O_RDONLY, 0)) == -1) - rtems_fatal_error_occurred('STD0'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); if ((stdout_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD1'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); if ((stderr_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD2'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) - rtems_fatal_error_occurred('STIO'); + rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); } int main( diff --git a/c/src/lib/libbsp/no_cpu/no_bsp/clock/ckinit.c b/c/src/lib/libbsp/no_cpu/no_bsp/clock/ckinit.c index efe0225520..7c8f9617e7 100644 --- a/c/src/lib/libbsp/no_cpu/no_bsp/clock/ckinit.c +++ b/c/src/lib/libbsp/no_cpu/no_bsp/clock/ckinit.c @@ -105,7 +105,7 @@ void Install_clock( */ if ( BSP_Configuration.ticks_per_timeslice ) { - Old_ticker = ( rtems_isr_entry ) set_vector( clock_isr, CLOCK_VECTOR, 1 ); + Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 ); /* * Hardware specific initialize goes here */ @@ -121,30 +121,6 @@ void Install_clock( } /* - * Reinstall_clock - * - * Install a clock tick handler without reprogramming the chip. This - * is used by the polling shared memory device driver. - */ - -void ReInstall_clock( - rtems_isr_entry clock_isr -) -{ - rtems_unsigned32 isrlevel = 0; - - /* - * Disable interrupts and install the clock ISR vector using the - * BSP dependent set_vector routine. In the below example, the clock - * ISR is on vector 4 and is an RTEMS interrupt. - */ - - rtems_interrupt_disable( isrlevel ); - (void) set_vector( clock_isr, CLOCK_VECTOR, 1 ); - rtems_interrupt_enable( isrlevel ); -} - -/* * Clean up before the application exits */ @@ -188,6 +164,7 @@ rtems_device_driver Clock_control( void *pargp ) { + rtems_unsigned32 isrlevel; rtems_libio_ioctl_args_t *args = pargp; if (args == 0) @@ -204,7 +181,9 @@ rtems_device_driver Clock_control( } else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { - ReInstall_clock(args->buffer); + rtems_interrupt_disable( isrlevel ); + (void) set_vector( args->buffer, CLOCK_VECTOR, 1 ); + rtems_interrupt_enable( isrlevel ); } done: diff --git a/c/src/lib/libbsp/no_cpu/no_bsp/startup/bspstart.c b/c/src/lib/libbsp/no_cpu/no_bsp/startup/bspstart.c index e28e791503..7f08b779dd 100644 --- a/c/src/lib/libbsp/no_cpu/no_bsp/startup/bspstart.c +++ b/c/src/lib/libbsp/no_cpu/no_bsp/startup/bspstart.c @@ -131,18 +131,21 @@ void bsp_postdriver_hook(void) { int stdin_fd, stdout_fd, stderr_fd; + int error_code; + + error_code = 'S' << 24 | 'T' << 16; if ((stdin_fd = __open("/dev/console", O_RDONLY, 0)) == -1) - rtems_fatal_error_occurred('STD0'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); if ((stdout_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD1'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); if ((stderr_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD2'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) - rtems_fatal_error_occurred('STIO'); + rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); } int bsp_start( diff --git a/c/src/lib/libbsp/powerpc/papyrus/startup/bspstart.c b/c/src/lib/libbsp/powerpc/papyrus/startup/bspstart.c index 6c5133f7ed..b044367f43 100644 --- a/c/src/lib/libbsp/powerpc/papyrus/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/papyrus/startup/bspstart.c @@ -149,18 +149,21 @@ void bsp_postdriver_hook(void) { int stdin_fd, stdout_fd, stderr_fd; + int error_code; + + error_code = 'S' << 24 | 'T' << 16; if ((stdin_fd = __open("/dev/console", O_RDONLY, 0)) == -1) - rtems_fatal_error_occurred('STD0'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); if ((stdout_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD1'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); if ((stderr_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD2'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) - rtems_fatal_error_occurred('STIO'); + rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); } int main( diff --git a/c/src/lib/libbsp/unix/posix/clock/clock.c b/c/src/lib/libbsp/unix/posix/clock/clock.c index da0dd46807..3e05b694a7 100644 --- a/c/src/lib/libbsp/unix/posix/clock/clock.c +++ b/c/src/lib/libbsp/unix/posix/clock/clock.c @@ -31,30 +31,18 @@ rtems_unsigned32 Clock_driver_vector; rtems_device_major_number rtems_clock_major = ~0; rtems_device_minor_number rtems_clock_minor; -void -Install_clock(rtems_isr_entry clock_isr) +void Install_clock(rtems_isr_entry clock_isr) { Clock_driver_ticks = 0; - (void)set_vector(clock_isr, Clock_driver_vector, 1); + (void) set_vector( clock_isr, Clock_driver_vector, 1 ); _CPU_Start_clock( BSP_Configuration.microseconds_per_tick ); atexit(Clock_exit); } -void -ReInstall_clock(rtems_isr_entry new_clock_isr) -{ - rtems_unsigned32 isrlevel = 0; - - rtems_interrupt_disable(isrlevel); - (void)set_vector(new_clock_isr, Clock_driver_vector, 1); - rtems_interrupt_enable(isrlevel); -} - -void -Clock_isr(int vector) +void Clock_isr(int vector) { Clock_driver_ticks++; rtems_clock_tick(); @@ -65,16 +53,14 @@ Clock_isr(int vector) * Remove the clock signal */ -void -Clock_exit(void) +void Clock_exit(void) { _CPU_Stop_clock(); - (void)set_vector(0, Clock_driver_vector, 1); + (void) set_vector( 0, Clock_driver_vector, 1 ); } -rtems_device_driver -Clock_initialize( +rtems_device_driver Clock_initialize( rtems_device_major_number major, rtems_device_minor_number minor, void *pargp @@ -99,6 +85,7 @@ rtems_device_driver Clock_control( void *pargp ) { + rtems_unsigned32 isrlevel; rtems_libio_ioctl_args_t *args = pargp; if (args == 0) @@ -115,7 +102,9 @@ rtems_device_driver Clock_control( } else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { - ReInstall_clock(args->buffer); + rtems_interrupt_disable( isrlevel ); + (void) set_vector( args->buffer, Clock_driver_vector, 1 ); + rtems_interrupt_enable( isrlevel ); } done: diff --git a/c/src/lib/libbsp/unix/posix/startup/bspstart.c b/c/src/lib/libbsp/unix/posix/startup/bspstart.c index 8ce3e92ecb..cefa60032f 100644 --- a/c/src/lib/libbsp/unix/posix/startup/bspstart.c +++ b/c/src/lib/libbsp/unix/posix/startup/bspstart.c @@ -182,18 +182,21 @@ bsp_postdriver_hook(void) { #if 0 int stdin_fd, stdout_fd, stderr_fd; + int error_code; + + error_code = 'S' << 24 | 'T' << 16; if ((stdin_fd = __open("/dev/console", O_RDONLY, 0)) == -1) - rtems_fatal_error_occurred('STD0'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); if ((stdout_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD1'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); if ((stderr_fd = __open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred('STD2'); + rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) - rtems_fatal_error_occurred('STIO'); + rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); #endif #if defined(MALLOC_STATS) diff --git a/c/src/lib/libcpu/sparc/include/erc32.h b/c/src/lib/libcpu/sparc/include/erc32.h new file mode 100644 index 0000000000..9a8b875c49 --- /dev/null +++ b/c/src/lib/libcpu/sparc/include/erc32.h @@ -0,0 +1,503 @@ +/* erc32.h + * + * This include file contains information pertaining to the ERC32. + * The ERC32 is a custom SPARC V7 implementation based on the Cypress + * 601/602 chipset. This CPU has a number of on-board peripherals and + * was developed by the European Space Agency to target space applications. + * + * NOTE: Other than where absolutely required, this version currently + * supports only the peripherals and bits used by the basic board + * support package. This includes at least significant pieces of + * the following items: + * + * + UART Channels A and B + * + General Purpose Timer + * + Real Time Clock + * + Watchdog Timer (so it can be disabled) + * + Control Register (so powerdown mode can be enabled) + * + Memory Control Register + * + Interrupt Control + * + * $Id$ + */ + +#ifndef _INCLUDE_ERC32_h +#define _INCLUDE_ERC32_h + +#include <rtems/score/sparc.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Interrupt Sources + * + * The interrupt source numbers directly map to the trap type and to + * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask, + * and the Interrupt Pending Registers. + */ + +#define ERC32_INTERRUPT_MASKED_ERRORS 1 +#define ERC32_INTERRUPT_EXTERNAL_1 2 +#define ERC32_INTERRUPT_EXTERNAL_2 3 +#define ERC32_INTERRUPT_UART_A_RX_TX 4 +#define ERC32_INTERRUPT_UART_B_RX_TX 5 +#define ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR 6 +#define ERC32_INTERRUPT_UART_ERROR 7 +#define ERC32_INTERRUPT_DMA_ACCESS_ERROR 8 +#define ERC32_INTERRUPT_DMA_TIMEOUT 9 +#define ERC32_INTERRUPT_EXTERNAL_3 10 +#define ERC32_INTERRUPT_EXTERNAL_4 11 +#define ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER 12 +#define ERC32_INTERRUPT_REAL_TIME_CLOCK 13 +#define ERC32_INTERRUPT_EXTERNAL_5 14 +#define ERC32_INTERRUPT_WATCHDOG_TIMEOUT 15 + +#ifndef ASM + +/* + * Trap Types for on-chip peripherals + * + * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments + * + * NOTE: The priority level for each source corresponds to the least + * significant nibble of the trap type. + */ + +#define ERC32_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) + +#define ERC32_TRAP_SOURCE( _trap ) ((_trap) - 0x10) + +#define ERC32_Is_MEC_Trap( _trap ) \ + ( (_trap) >= ERC32_TRAP_TYPE( ERC32_INTERRUPT_MASKED_ERRORS ) && \ + (_trap) <= ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ) ) + +/* + * Structure for ERC32 memory mapped registers. + * + * Source: Section 3.25.2 - Register Address Map + * + * NOTE: There is only one of these structures per CPU, its base address + * is 0x01f80000, and the variable MEC is placed there by the + * linkcmds file. + */ + +typedef struct { + volatile unsigned32 Control; /* offset 0x00 */ + volatile unsigned32 Software_Reset; /* offset 0x04 */ + volatile unsigned32 Power_Down; /* offset 0x08 */ + volatile unsigned32 Unimplemented_0; /* offset 0x0c */ + volatile unsigned32 Memory_Configuration; /* offset 0x10 */ + volatile unsigned32 IO_Configuration; /* offset 0x14 */ + volatile unsigned32 Wait_State_Configuration; /* offset 0x18 */ + volatile unsigned32 Unimplemented_1; /* offset 0x1c */ + volatile unsigned32 Memory_Access_0; /* offset 0x20 */ + volatile unsigned32 Memory_Access_1; /* offset 0x24 */ + volatile unsigned32 Unimplemented_2[ 7 ]; /* offset 0x28 */ + volatile unsigned32 Interrupt_Shape; /* offset 0x44 */ + volatile unsigned32 Interrupt_Pending; /* offset 0x48 */ + volatile unsigned32 Interrupt_Mask; /* offset 0x4c */ + volatile unsigned32 Interrupt_Clear; /* offset 0x50 */ + volatile unsigned32 Interrupt_Force; /* offset 0x54 */ + volatile unsigned32 Unimplemented_3[ 2 ]; /* offset 0x58 */ + /* offset 0x60 */ + volatile unsigned32 Watchdog_Program_and_Timeout_Acknowledge; + volatile unsigned32 Watchdog_Trap_Door_Set; /* offset 0x64 */ + volatile unsigned32 Unimplemented_4[ 6 ]; /* offset 0x68 */ + volatile unsigned32 Real_Time_Clock_Counter; /* offset 0x80 */ + volatile unsigned32 Real_Time_Clock_Scalar; /* offset 0x84 */ + volatile unsigned32 General_Purpose_Timer_Counter; /* offset 0x88 */ + volatile unsigned32 General_Purpose_Timer_Scalar; /* offset 0x8c */ + volatile unsigned32 Unimplemented_5[ 2 ]; /* offset 0x90 */ + volatile unsigned32 Timer_Control; /* offset 0x98 */ + volatile unsigned32 Unimplemented_6; /* offset 0x9c */ + volatile unsigned32 System_Fault_Status; /* offset 0xa0 */ + volatile unsigned32 First_Failing_Address; /* offset 0xa4 */ + volatile unsigned32 First_Failing_Data; /* offset 0xa8 */ + volatile unsigned32 First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */ + volatile unsigned32 Error_and_Reset_Status; /* offset 0xb0 */ + volatile unsigned32 Error_Mask; /* offset 0xb4 */ + volatile unsigned32 Unimplemented_7[ 2 ]; /* offset 0xb8 */ + volatile unsigned32 Debug_Control; /* offset 0xc0 */ + volatile unsigned32 Breakpoint; /* offset 0xc4 */ + volatile unsigned32 Watchpoint; /* offset 0xc8 */ + volatile unsigned32 Unimplemented_8; /* offset 0xcc */ + volatile unsigned32 Test_Control; /* offset 0xd0 */ + volatile unsigned32 Test_Data; /* offset 0xd4 */ + volatile unsigned32 Unimplemented_9[ 2 ]; /* offset 0xd8 */ + volatile unsigned32 UART_Channel_A; /* offset 0xe0 */ + volatile unsigned32 UART_Channel_B; /* offset 0xe4 */ + volatile unsigned32 UART_Status; /* offset 0xe8 */ +} ERC32_Register_Map; + +#endif + +/* + * The following constants are intended to be used ONLY in assembly + * language files. + * + * NOTE: The intended style of usage is to load the address of MEC + * into a register and then use these as displacements from + * that register. + */ + +#ifdef ASM + +#define ERC32_MEC_CONTROL_OFFSET 0x00 +#define ERC32_MEC_SOFTWARE_RESET_OFFSET 0x04 +#define ERC32_MEC_POWER_DOWN_OFFSET 0x08 +#define ERC32_MEC_UNIMPLEMENTED_0_OFFSET 0x0C +#define ERC32_MEC_MEMORY_CONFIGURATION_OFFSET 0x10 +#define ERC32_MEC_IO_CONFIGURATION_OFFSET 0x14 +#define ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET 0x18 +#define ERC32_MEC_UNIMPLEMENTED_1_OFFSET 0x1C +#define ERC32_MEC_MEMORY_ACCESS_0_OFFSET 0x20 +#define ERC32_MEC_MEMORY_ACCESS_1_OFFSET 0x24 +#define ERC32_MEC_UNIMPLEMENTED_2_OFFSET 0x28 +#define ERC32_MEC_INTERRUPT_SHAPE_OFFSET 0x44 +#define ERC32_MEC_INTERRUPT_PENDING_OFFSET 0x48 +#define ERC32_MEC_INTERRUPT_MASK_OFFSET 0x4C +#define ERC32_MEC_INTERRUPT_CLEAR_OFFSET 0x50 +#define ERC32_MEC_INTERRUPT_FORCE_OFFSET 0x54 +#define ERC32_MEC_UNIMPLEMENTED_3_OFFSET 0x58 +#define ERC32_MEC_WATCHDOG_PROGRAM_AND_TIMEOUT_ACKNOWLEDGE_OFFSET 0x60 +#define ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET 0x64 +#define ERC32_MEC_UNIMPLEMENTED_4_OFFSET 0x6C +#define ERC32_MEC_REAL_TIME_CLOCK_COUNTER_OFFSET 0x80 +#define ERC32_MEC_REAL_TIME_CLOCK_SCALAR_OFFSET 0x84 +#define ERC32_MEC_GENERAL_PURPOSE_TIMER_COUNTER_OFFSET 0x88 +#define ERC32_MEC_GENERAL_PURPOSE_TIMER_SCALAR_OFFSET 0x8C +#define ERC32_MEC_UNIMPLEMENTED_5_OFFSET 0x90 +#define ERC32_MEC_TIMER_CONTROL_OFFSET 0x98 +#define ERC32_MEC_UNIMPLEMENTED_6_OFFSET 0x9C +#define ERC32_MEC_SYSTEM_FAULT_STATUS_OFFSET 0xA0 +#define ERC32_MEC_FIRST_FAILING_ADDRESS_OFFSET 0xA4 +#define ERC32_MEC_FIRST_FAILING_DATA_OFFSET 0xA8 +#define ERC32_MEC_FIRST_FAILING_SYNDROME_AND_CHECK_BITS_OFFSET 0xAC +#define ERC32_MEC_ERROR_AND_RESET_STATUS_OFFSET 0xB0 +#define ERC32_MEC_ERROR_MASK_OFFSET 0xB4 +#define ERC32_MEC_UNIMPLEMENTED_7_OFFSET 0xB8 +#define ERC32_MEC_DEBUG_CONTROL_OFFSET 0xC0 +#define ERC32_MEC_BREAKPOINT_OFFSET 0xC4 +#define ERC32_MEC_WATCHPOINT_OFFSET 0xC8 +#define ERC32_MEC_UNIMPLEMENTED_8_OFFSET 0xCC +#define ERC32_MEC_TEST_CONTROL_OFFSET 0xD0 +#define ERC32_MEC_TEST_DATA_OFFSET 0xD4 +#define ERC32_MEC_UNIMPLEMENTED_9_OFFSET 0xD8 +#define ERC32_MEC_UART_CHANNEL_A_OFFSET 0xE0 +#define ERC32_MEC_UART_CHANNEL_B_OFFSET 0xE4 +#define ERC32_MEC_UART_STATUS_OFFSET 0xE8 + +#endif + +/* + * The following defines the bits in the Configuration Register. + */ + +#define ERC32_CONFIGURATION_POWER_DOWN_MASK 0x00000001 +#define ERC32_CONFIGURATION_POWER_DOWN_ALLOWED 0x00000001 +#define ERC32_CONFIGURATION_POWER_DOWN_DISABLED 0x00000000 + +#define ERC32_CONFIGURATION_SOFTWARE_RESET_MASK 0x00000002 +#define ERC32_CONFIGURATION_SOFTWARE_RESET_ALLOWED 0x00000002 +#define ERC32_CONFIGURATION_SOFTWARE_RESET_DISABLED 0x00000000 + +#define ERC32_CONFIGURATION_BUS_TIMEOUT_MASK 0x00000004 +#define ERC32_CONFIGURATION_BUS_TIMEOUT_ENABLED 0x00000004 +#define ERC32_CONFIGURATION_BUS_TIMEOUT_DISABLED 0x00000000 + +#define ERC32_CONFIGURATION_ACCESS_PROTECTION_MASK 0x00000008 +#define ERC32_CONFIGURATION_ACCESS_PROTECTION_ENABLED 0x00000008 +#define ERC32_CONFIGURATION_ACCESS_PROTECTION_DISABLED 0x00000000 + + +/* + * The following defines the bits in the Memory Configuration Register. + */ + +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001C00 +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_256K ( 0 << 10 ) +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_512K ( 1 << 10 ) +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_1MB ( 2 << 10 ) +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_2MB ( 3 << 10 ) +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_4MB ( 4 << 10 ) +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_8MB ( 5 << 10 ) +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_16MB ( 6 << 10 ) +#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB ( 7 << 10 ) + +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x001C0000 +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4K ( 0 << 18 ) +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8K ( 1 << 18 ) +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16K ( 2 << 18 ) +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_32K ( 3 << 18 ) +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_64K ( 4 << 18 ) +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K ( 5 << 18 ) +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K ( 6 << 18 ) +#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K ( 7 << 18 ) + +/* + * The following defines the bits in the Timer Control Register. + */ + +#define ERC32_MEC_TIMER_CONTROL_GCR 0x00000001 /* 1 = reload at 0 */ + /* 0 = stop at 0 */ +#define ERC32_MEC_TIMER_CONTROL_GCL 0x00000002 /* 1 = load and start */ + /* 0 = no function */ +#define ERC32_MEC_TIMER_CONTROL_GSE 0x00000004 /* 1 = enable counting */ + /* 0 = hold scalar and counter */ +#define ERC32_MEC_TIMER_CONTROL_GSL 0x00000008 /* 1 = load scalar and start */ + /* 0 = no function */ + +#define ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100 /* 1 = reload at 0 */ + /* 0 = stop at 0 */ +#define ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200 /* 1 = load and start */ + /* 0 = no function */ +#define ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400 /* 1 = enable counting */ + /* 0 = hold scalar and counter */ +#define ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800 /* 1 = load scalar and start */ + /* 0 = no function */ + +/* + * The following defines the bits in the UART Control Registers. + * + * NOTE: Same bits in UART channels A and B. + */ + +#define ERC32_MEC_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ +#define ERC32_MEC_UART_CONTROL_DR 0x00000100 /* RX Data Ready */ +#define ERC32_MEC_UART_CONTROL_TSE 0x00000200 /* TX Send Empty */ + /* (i.e. no data to send) */ +#define ERC32_MEC_UART_CONTROL_THE 0x00000400 /* TX Hold Empty */ + /* (i.e. ready to load) */ + +/* + * The following defines the bits in the MEC UART Control Registers. + */ + +#define ERC32_MEC_UART_STATUS_DR 0x00000001 /* Data Ready */ +#define ERC32_MEC_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ +#define ERC32_MEC_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ +#define ERC32_MEC_UART_STATUS_FE 0x00000010 /* RX Framing Error */ +#define ERC32_MEC_UART_STATUS_PE 0x00000020 /* RX Parity Error */ +#define ERC32_MEC_UART_STATUS_OE 0x00000040 /* RX Overrun Error */ +#define ERC32_MEC_UART_STATUS_CU 0x00000080 /* Clear Errors */ +#define ERC32_MEC_UART_STATUS_TXE 0x00000006 /* TX Empty */ + +#define ERC32_MEC_UART_STATUS_DRA (ERC32_MEC_UART_STATUS_DR << 0) +#define ERC32_MEC_UART_STATUS_TSEA (ERC32_MEC_UART_STATUS_TSE << 0) +#define ERC32_MEC_UART_STATUS_THEA (ERC32_MEC_UART_STATUS_THE << 0) +#define ERC32_MEC_UART_STATUS_FEA (ERC32_MEC_UART_STATUS_FE << 0) +#define ERC32_MEC_UART_STATUS_PEA (ERC32_MEC_UART_STATUS_PE << 0) +#define ERC32_MEC_UART_STATUS_OEA (ERC32_MEC_UART_STATUS_OE << 0) +#define ERC32_MEC_UART_STATUS_CUA (ERC32_MEC_UART_STATUS_CU << 0) +#define ERC32_MEC_UART_STATUS_TXEA (ERC32_MEC_UART_STATUS_TXE << 0) + +#define ERC32_MEC_UART_STATUS_DRB (ERC32_MEC_UART_STATUS_DR << 16) +#define ERC32_MEC_UART_STATUS_TSEB (ERC32_MEC_UART_STATUS_TSE << 16) +#define ERC32_MEC_UART_STATUS_THEB (ERC32_MEC_UART_STATUS_THE << 16) +#define ERC32_MEC_UART_STATUS_FEB (ERC32_MEC_UART_STATUS_FE << 16) +#define ERC32_MEC_UART_STATUS_PEB (ERC32_MEC_UART_STATUS_PE << 16) +#define ERC32_MEC_UART_STATUS_OEB (ERC32_MEC_UART_STATUS_OE << 16) +#define ERC32_MEC_UART_STATUS_CUB (ERC32_MEC_UART_STATUS_CU << 16) +#define ERC32_MEC_UART_STATUS_TXEB (ERC32_MEC_UART_STATUS_TXE << 16) + +#ifndef ASM + +/* + * This is used to manipulate the on-chip registers. + * + * The following symbol must be defined in the linkcmds file and point + * to the correct location. + */ + +extern ERC32_Register_Map ERC32_MEC; + +/* + * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, + * and the Interrupt Pending Registers. + * + * NOTE: For operations which are not atomic, this code disables interrupts + * to guarantee there are no intervening accesses to the same register. + * The operations which read the register, modify the value and then + * store the result back are vulnerable. + */ + +#define ERC32_Clear_interrupt( _source ) \ + do { \ + ERC32_MEC.Interrupt_Clear = (1 << (_source)); \ + } while (0) + +#define ERC32_Force_interrupt( _source ) \ + do { \ + ERC32_MEC.Interrupt_Force = (1 << (_source)); \ + } while (0) + +#define ERC32_Is_interrupt_pending( _source ) \ + (ERC32_MEC.Interrupt_Pending & (1 << (_source))) + +#define ERC32_Is_interrupt_masked( _source ) \ + (ERC32_MEC.Interrupt_Masked & (1 << (_source))) + +#define ERC32_Mask_interrupt( _source ) \ + do { \ + unsigned32 _level; \ + \ + sparc_disable_interrupts( _level ); \ + ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \ + sparc_enable_interrupts( _level ); \ + } while (0) + +#define ERC32_Unmask_interrupt( _source ) \ + do { \ + unsigned32 _level; \ + \ + sparc_disable_interrupts( _level ); \ + ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \ + sparc_enable_interrupts( _level ); \ + } while (0) + +#define ERC32_Disable_interrupt( _source, _previous ) \ + do { \ + unsigned32 _level; \ + unsigned32 _mask = 1 << (_source); \ + \ + sparc_disable_interrupts( _level ); \ + (_previous) = ERC32_MEC.Interrupt_Mask; \ + ERC32_MEC.Interrupt_Mask = _previous | _mask; \ + sparc_enable_interrupts( _level ); \ + (_previous) &= ~_mask; \ + } while (0) + +#define ERC32_Restore_interrupt( _source, _previous ) \ + do { \ + unsigned32 _level; \ + unsigned32 _mask = 1 << (_source); \ + \ + sparc_disable_interrupts( _level ); \ + ERC32_MEC.Interrupt_Mask = \ + (ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \ + sparc_enable_interrupts( _level ); \ + } while (0) + +/* + * The following macros attempt to hide the fact that the General Purpose + * Timer and Real Time Clock Timer share the Timer Control Register. Because + * the Timer Control Register is write only, we must mirror it in software + * and insure that writes to one timer do not alter the current settings + * and status of the other timer. + * + * This code promotes the view that the two timers are completely independent. + * By exclusively using the routines below to access the Timer Control + * Register, the application can view the system as having a General Purpose + * Timer Control Register and a Real Time Clock Timer Control Register + * rather than the single shared value. + * + * Each logical timer control register is organized as follows: + * + * D0 - Counter Reload + * 1 = reload counter at zero and restart + * 0 = stop counter at zero + * + * D1 - Counter Load + * 1 = load counter with preset value and restart + * 0 = no function + * + * D2 - Enable + * 1 = enable counting + * 0 = hold scaler and counter + * + * D2 - Scaler Load + * 1 = load scalar with preset value and restart + * 0 = no function + * + * To insure the management of the mirror is atomic, we disable interrupts + * around updates. + */ + +#define ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000001 +#define ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 + +#define ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER 0x00000002 + +#define ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING 0x00000004 +#define ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 + +#define ERC32_MEC_TIMER_COUNTER_LOAD_SCALER 0x00000008 + +#define ERC32_MEC_TIMER_COUNTER_RELOAD_MASK 0x00000001 +#define ERC32_MEC_TIMER_COUNTER_ENABLE_MASK 0x00000004 + +#define ERC32_MEC_TIMER_COUNTER_DEFINED_MASK 0x0000000F +#define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000005 + +extern unsigned32 _ERC32_MEC_Timer_Control_Mirror; + +/* + * This macros manipulate the General Purpose Timer portion of the + * Timer Control register and promote the view that there are actually + * two independent Timer Control Registers. + */ + +#define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \ + do { \ + unsigned32 _level; \ + unsigned32 _control; \ + unsigned32 __value; \ + \ + __value = ((_value) & 0x0f); \ + sparc_disable_interrupts( _level ); \ + _control = _ERC32_MEC_Timer_Control_Mirror; \ + _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \ + _ERC32_MEC_Timer_Control_Mirror = _control | _value; \ + _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \ + _control |= __value; \ + /* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \ + ERC32_MEC.Timer_Control = _control; \ + sparc_enable_interrupts( _level ); \ + } while ( 0 ) + +#define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \ + do { \ + (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \ + } while ( 0 ) + +/* + * This macros manipulate the Real Timer Clock Timer portion of the + * Timer Control register and promote the view that there are actually + * two independent Timer Control Registers. + */ + +#define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \ + do { \ + unsigned32 _level; \ + unsigned32 _control; \ + unsigned32 __value; \ + \ + __value = ((_value) & 0x0f) << 8; \ + sparc_disable_interrupts( _level ); \ + _control = _ERC32_MEC_Timer_Control_Mirror; \ + _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \ + _ERC32_MEC_Timer_Control_Mirror = _control | _value; \ + _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \ + _control |= __value; \ + /* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \ + ERC32_MEC.Timer_Control = _control; \ + sparc_enable_interrupts( _level ); \ + } while ( 0 ) + +#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \ + do { \ + (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \ + } while ( 0 ) + + +#endif /* !ASM */ + +#ifdef __cplusplus +} +#endif + +#endif /* !_INCLUDE_ERC32_h */ +/* end of include file */ + |