diff options
Diffstat (limited to 'c/src/lib')
| -rw-r--r-- | c/src/lib/libbsp/mips/shared/irq/exception.S | 9 | ||||
| -rw-r--r-- | c/src/lib/libcpu/sparc64/shared/score/interrupt.S | 4 |
2 files changed, 6 insertions, 7 deletions
diff --git a/c/src/lib/libbsp/mips/shared/irq/exception.S b/c/src/lib/libbsp/mips/shared/irq/exception.S index f95dec253b..e8f8d693bf 100644 --- a/c/src/lib/libbsp/mips/shared/irq/exception.S +++ b/c/src/lib/libbsp/mips/shared/irq/exception.S @@ -87,7 +87,6 @@ #endif -EXTERN(_Thread_Dispatch_disable_level,4) .extern _Thread_Dispatch .extern _ISR_Vector_table @@ -239,10 +238,10 @@ _chk_int: /* * _Thread_Dispatch_disable_level++; */ - lw t1,_Thread_Dispatch_disable_level + lw t1,THREAD_DISPATCH_DISABLE_LEVEL NOP add t1,t1,1 - sw t1,_Thread_Dispatch_disable_level + sw t1,THREAD_DISPATCH_DISABLE_LEVEL /* DEBUG - Add the following code to disable interrupts and clear * EXL in status register, this will allow memory @@ -302,10 +301,10 @@ _ISR_Handler_cleanup: /* * --_Thread_Dispatch_disable_level; */ - lw t1,_Thread_Dispatch_disable_level + lw t1,THREAD_DISPATCH_DISABLE_LEVEL NOP add t1,t1,-1 - sw t1,_Thread_Dispatch_disable_level + sw t1,THREAD_DISPATCH_DISABLE_LEVEL /* * if ( _Thread_Dispatch_disable_level || _ISR_Nest_level ) * goto the label "exit interrupt (simple case)" diff --git a/c/src/lib/libcpu/sparc64/shared/score/interrupt.S b/c/src/lib/libcpu/sparc64/shared/score/interrupt.S index b477a6e416..8a930c9c1b 100644 --- a/c/src/lib/libcpu/sparc64/shared/score/interrupt.S +++ b/c/src/lib/libcpu/sparc64/shared/score/interrupt.S @@ -176,7 +176,7 @@ PUBLIC(_ISR_Handler) * nest and thread dispatch disable levels are unnested. */ - setx SYM(_Thread_Dispatch_disable_level), %o5, %g3 + setx THREAD_DISPATCH_DISABLE_LEVEL, %o5, %g3 lduw [%g3], %g5 setx ISR_NEST_LEVEL, %o5, %g6 lduw [%g6], %g4 @@ -299,7 +299,7 @@ PUBLIC(_ISR_Handler) * window for _ISR_Handler. */ - setx SYM(_Thread_Dispatch_disable_level), %o5, %g3 + setx THREAD_DISPATCH_DISABLE_LEVEL, %o5, %g3 lduw [%g3],%g5 lduw [%g6],%g4 sub %g5, 1, %g5 |