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-rw-r--r--c/src/lib/libcpu/mips/ChangeLog18
-rw-r--r--c/src/lib/libcpu/mips/Makefile.am6
-rw-r--r--c/src/lib/libcpu/mips/clock/ckinit.c4
-rw-r--r--c/src/lib/libcpu/mips/configure.in7
-rw-r--r--c/src/lib/libcpu/mips/shared/.cvsignore2
-rw-r--r--c/src/lib/libcpu/mips/shared/Makefile.am10
-rw-r--r--c/src/lib/libcpu/mips/shared/cache/.cvsignore2
-rw-r--r--c/src/lib/libcpu/mips/shared/cache/Makefile.am39
-rw-r--r--c/src/lib/libcpu/mips/shared/cache/cache.c10
-rw-r--r--c/src/lib/libcpu/mips/shared/cache/cache_.h13
-rw-r--r--c/src/lib/libcpu/mips/shared/interrupts/.cvsignore2
-rw-r--r--c/src/lib/libcpu/mips/shared/interrupts/Makefile.am32
-rw-r--r--c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c29
-rw-r--r--c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S74
-rw-r--r--c/src/lib/libcpu/mips/shared/interrupts/maxvectors.c29
-rw-r--r--c/src/lib/libcpu/mips/tx39/.cvsignore13
-rw-r--r--c/src/lib/libcpu/mips/tx39/Makefile.am11
-rw-r--r--c/src/lib/libcpu/mips/tx39/include/.cvsignore13
-rw-r--r--c/src/lib/libcpu/mips/tx39/include/Makefile.am22
-rw-r--r--c/src/lib/libcpu/mips/tx39/include/tx3904.h63
20 files changed, 396 insertions, 3 deletions
diff --git a/c/src/lib/libcpu/mips/ChangeLog b/c/src/lib/libcpu/mips/ChangeLog
index 8beec7d771..ba0a4aa02a 100644
--- a/c/src/lib/libcpu/mips/ChangeLog
+++ b/c/src/lib/libcpu/mips/ChangeLog
@@ -1,3 +1,21 @@
+2000-12-13 Joel Sherrill <joel@OARcorp.com>
+
+ * shared/.cvsignore, shared/Makefile.am,
+ shared/cache/.cvsignore, shared/cache/Makefile.am,
+ shared/cache/cache.c, shared/cache/cache_.h,
+ shared/interrupts/.cvsignore, shared/interrupts/Makefile.am,
+ shared/interrupts/installisrentries.c,
+ shared/interrupts/isr_entries.S,
+ shared/interrupts/maxvectors.c, tx39/.cvsignore,
+ tx39/Makefile.am, tx39/include/.cvsignore,
+ tx39/include/Makefile.am, tx39/include/tx3904.h: New file.
+ Moved some pieces of interrupt processing from score/cpu to
+ libcpu/mips since many interrupt servicing characteristics are
+ CPU model dependent. This patch addresses the number of interrupt
+ sources and where the ISR prologues are located. The only way to
+ currently install the ISR prologues requires that the prologues
+ be installed into RAM.
+
2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
diff --git a/c/src/lib/libcpu/mips/Makefile.am b/c/src/lib/libcpu/mips/Makefile.am
index c9c91b7900..c98068980d 100644
--- a/c/src/lib/libcpu/mips/Makefile.am
+++ b/c/src/lib/libcpu/mips/Makefile.am
@@ -5,7 +5,11 @@
AUTOMAKE_OPTIONS = foreign 1.4
ACLOCAL_AMFLAGS = -I ../../../../../aclocal
-SHARED_LIB =
+SHARED_LIB = shared
+
+if tx39
+CPU_SUBDIR = tx39
+endif
if r46xx
CPU_SUBDIR = clock timer
diff --git a/c/src/lib/libcpu/mips/clock/ckinit.c b/c/src/lib/libcpu/mips/clock/ckinit.c
index c6ae88f9e0..f6990a44d5 100644
--- a/c/src/lib/libcpu/mips/clock/ckinit.c
+++ b/c/src/lib/libcpu/mips/clock/ckinit.c
@@ -168,7 +168,7 @@ void Install_clock(
mips_timer_rate =
rtems_configuration_get_microseconds_per_tick() * CLOCKS_PER_MICROSECOND;
mips_set_timer( mips_timer_rate );
- enable_int(CLOCK_VECTOR_MASK);
+ mips_enable_in_interrupt_mask(CLOCK_VECTOR_MASK);
/*
* Schedule the clock cleanup routine to execute if the application exits.
@@ -184,7 +184,7 @@ void Install_clock(
void Clock_exit( void )
{
/* mips: turn off the timer interrupts */
- disable_int(~CLOCK_VECTOR_MASK);
+ mips_disable_in_interrupt_mask(CLOCK_VECTOR_MASK);
}
/*
diff --git a/c/src/lib/libcpu/mips/configure.in b/c/src/lib/libcpu/mips/configure.in
index 822592cdc0..70e45bc664 100644
--- a/c/src/lib/libcpu/mips/configure.in
+++ b/c/src/lib/libcpu/mips/configure.in
@@ -29,8 +29,15 @@ RTEMS_CHECK_BSP_CACHE(RTEMS_BSP)
AM_CONDITIONAL(r46xx, test "$RTEMS_CPU_MODEL" = "R4600" \
|| test "$RTEMS_CPU_MODEL" = "R4650" )
+AM_CONDITIONAL(tx39, test "$RTEMS_CPU_MODEL" = "tx3904")
+
# Explicitly list all Makefiles here
AC_OUTPUT(
Makefile
clock/Makefile
+shared/Makefile
+shared/cache/Makefile
+shared/interrupts/Makefile
+tx39/Makefile
+tx39/include/Makefile
timer/Makefile)
diff --git a/c/src/lib/libcpu/mips/shared/.cvsignore b/c/src/lib/libcpu/mips/shared/.cvsignore
new file mode 100644
index 0000000000..282522db03
--- /dev/null
+++ b/c/src/lib/libcpu/mips/shared/.cvsignore
@@ -0,0 +1,2 @@
+Makefile
+Makefile.in
diff --git a/c/src/lib/libcpu/mips/shared/Makefile.am b/c/src/lib/libcpu/mips/shared/Makefile.am
new file mode 100644
index 0000000000..b534a0c8ea
--- /dev/null
+++ b/c/src/lib/libcpu/mips/shared/Makefile.am
@@ -0,0 +1,10 @@
+##
+## $Id$
+##
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+SUBDIRS = cache interrupts
+
+include $(top_srcdir)/../../../../../automake/subdirs.am
+include $(top_srcdir)/../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/mips/shared/cache/.cvsignore b/c/src/lib/libcpu/mips/shared/cache/.cvsignore
new file mode 100644
index 0000000000..282522db03
--- /dev/null
+++ b/c/src/lib/libcpu/mips/shared/cache/.cvsignore
@@ -0,0 +1,2 @@
+Makefile
+Makefile.in
diff --git a/c/src/lib/libcpu/mips/shared/cache/Makefile.am b/c/src/lib/libcpu/mips/shared/cache/Makefile.am
new file mode 100644
index 0000000000..ca04231141
--- /dev/null
+++ b/c/src/lib/libcpu/mips/shared/cache/Makefile.am
@@ -0,0 +1,39 @@
+##
+## $Id$
+##
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+VPATH = @srcdir@:@srcdir@/../../../shared/src
+
+C_FILES = cache.c cache_aligned_malloc.c cache_manager.c
+C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
+
+H_FILES = cache_.h
+INSTALLED_H_FILES =
+
+OBJS = $(C_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
+include $(top_srcdir)/../../../../../automake/compile.am
+include $(top_srcdir)/../../../../../automake/lib.am
+
+AM_CPPFLAGS += -I$(srcdir)
+
+$(PROJECT_INCLUDE)/libcpu:
+ $(mkinstalldirs) $@
+
+$(PROJECT_INCLUDE)/libcpu/%.h: %.h
+ $(INSTALL_DATA) $< $@
+
+$(PROJECT_INCLUDE)/libcpu/cache.h: $(top_srcdir)/../shared/include/cache.h
+ $(INSTALL_DATA) $< $@
+
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu \
+ $(PROJECT_INCLUDE)/libcpu/cache.h
+
+all-local: $(ARCH) $(PREINSTALL_FILES) $(OBJS)
+
+EXTRA_DIST = cache.c cache_.h
+
+include $(top_srcdir)/../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/mips/shared/cache/cache.c b/c/src/lib/libcpu/mips/shared/cache/cache.c
new file mode 100644
index 0000000000..9af01feffd
--- /dev/null
+++ b/c/src/lib/libcpu/mips/shared/cache/cache.c
@@ -0,0 +1,10 @@
+/*
+ * Cache Management Support Routines for the MIPS
+ *
+ * $Id$
+ */
+
+#include <rtems.h>
+#include "cache_.h"
+
+/* TBD */
diff --git a/c/src/lib/libcpu/mips/shared/cache/cache_.h b/c/src/lib/libcpu/mips/shared/cache/cache_.h
new file mode 100644
index 0000000000..d51c4ee075
--- /dev/null
+++ b/c/src/lib/libcpu/mips/shared/cache/cache_.h
@@ -0,0 +1,13 @@
+/*
+ * MIPS Cache Manager Support
+ */
+
+#ifndef __MIPS_CACHE_h
+#define __MIPS_CACHE_h
+
+#include <libcpu/cache.h>
+
+/* TBD */
+
+#endif
+/* end of include file */
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/.cvsignore b/c/src/lib/libcpu/mips/shared/interrupts/.cvsignore
new file mode 100644
index 0000000000..282522db03
--- /dev/null
+++ b/c/src/lib/libcpu/mips/shared/interrupts/.cvsignore
@@ -0,0 +1,2 @@
+Makefile
+Makefile.in
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/Makefile.am b/c/src/lib/libcpu/mips/shared/interrupts/Makefile.am
new file mode 100644
index 0000000000..434f2a38ec
--- /dev/null
+++ b/c/src/lib/libcpu/mips/shared/interrupts/Makefile.am
@@ -0,0 +1,32 @@
+##
+## $Id$
+##
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+PGM = $(ARCH)/interrupts.rel
+
+C_FILES = installisrentries.c maxvectors.c
+
+S_FILES = isr_entries.S
+
+interrupts_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) $(S_FILES:%.S=$(ARCH)/%.o)
+
+include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
+include $(top_srcdir)/../../../../../automake/compile.am
+include $(top_srcdir)/../../../../../automake/lib.am
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+$(PGM): $(interrupts_rel_OBJECTS)
+ $(make-rel)
+
+all-local: $(ARCH) $(interrupts_rel_OBJECTS) $(PGM)
+
+.PRECIOUS: $(PGM)
+
+EXTRA_DIST = maxvectors.c
+
+include $(top_srcdir)/../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c b/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c
new file mode 100644
index 0000000000..5dd37f82bb
--- /dev/null
+++ b/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c
@@ -0,0 +1,29 @@
+/*
+ * $Id$
+ */
+
+#include <rtems.h>
+#include <idtcpu.h>
+#include <stdlib.h>
+
+void mips_install_isr_entries( void )
+{
+#if __mips == 1
+ void exc_utlb_code(void);
+ void exc_norm_code(void);
+
+ memcpy( (void *)UT_VEC, exc_utlb_code, 40 ); /* utlbmiss vector */
+ memcpy( (void *)E_VEC, exc_norm_code, 40 ); /* exception vevtor */
+#elif __mips == 3
+ void exc_tlb_code(void);
+ void exc_utlb_code(void);
+ void exc_cache_code(void);
+ void exc_norm_code(void);
+
+ memcpy( (void *)T_VEC, exc_tlb_code, 40 ); /* tlbmiss vector */
+ memcpy( (void *)X_VEC, exc_xtlb_code, 40 ); /* xtlbmiss vector */
+ memcpy( (void *)C_VEC, exc_cache_code, 40 ); /* cache error vector */
+ memcpy( (void *)E_VEC, exc_norm_code, 40 ); /* exception vector */
+#endif
+ rtems_cache_flush_entire_data();
+}
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S
new file mode 100644
index 0000000000..8fe31cd6e2
--- /dev/null
+++ b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S
@@ -0,0 +1,74 @@
+/*
+ * This file contains the raw entry points for the exceptions.
+ *
+ * COPYRIGHT (c) 1989-2000.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * $Id$
+ */
+/* @(#)cpu_asm.S 08/20/96 1.15 */
+
+#include <asm.h>
+#include "iregdef.h"
+#include "idtcpu.h"
+
+/*
+ * MIPS ISA Level 1 entries
+ */
+
+#if __mips == 1
+
+FRAME(exc_norm_code,sp,0,ra)
+ la k0, _ISR_Handler /* generic external int hndlr */
+ j k0
+ nop
+ENDFRAME(exc_norm_code)
+
+/* XXX this is dependent on IDT/SIM and needs to be addressed */
+FRAME(exc_utlb_code,sp,0,ra)
+ la k0, (R_VEC+((48)*8))
+ j k0
+ nop
+ENDFRAME(exc_tlb_code)
+
+/*
+ * MIPS ISA Level 3
+ * XXX Again, reliance on SIM. Not good.
+ */
+#elif __mips == 3
+
+FRAME(exc_tlb_code,sp,0,ra)
+ la k0, (R_VEC+((112)*8)) /* R4000 Sim location */
+ j k0
+ nop
+ENDFRAME(exc_tlb_code)
+
+FRAME(exc_xtlb_code,sp,0,ra)
+ la k0, (R_VEC+((112)*8)) /* R4000 Sim location */
+ j k0
+ nop
+
+ENDFRAME(exc_xtlb_code)
+
+FRAME(exc_cache_code,sp,0,ra)
+ la k0, (R_VEC+((112)*8)) /* R4000 Sim location */
+ j k0
+ nop
+ENDFRAME(exc_cache_code)
+
+FRAME(exc_norm_code,sp,0,ra)
+ la k0, _ISR_Handler /* generic external int hndlr */
+ j k0
+ nop
+ENDFRAME(exc_norm_code)
+
+#else
+
+#error "isr_entries.S: ISA support problem"
+
+#endif
+
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/maxvectors.c b/c/src/lib/libcpu/mips/shared/interrupts/maxvectors.c
new file mode 100644
index 0000000000..c1e5df20a4
--- /dev/null
+++ b/c/src/lib/libcpu/mips/shared/interrupts/maxvectors.c
@@ -0,0 +1,29 @@
+/*
+ * This file contains the maximum number of vectors. This can not
+ * be determined without knowing the RTEMS CPU model.
+ *
+ * COPYRIGHT (c) 1989-2000.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * $Id$
+ */
+
+
+/*
+ * The tx3904 attaches 4 of the eight interrupt bits to an on-CPU interrupt
+ * controller so that these four bits map to 16 unique interrupts.
+ * So you have: 2 software interrupts, an NMI, and 16 others.
+ */
+#if defined(tx3904)
+#define MAX_VECTORS 19
+#endif
+
+#ifndef MAX
+#define MAX_VECTORS 8
+#endif
+
+unsigned int mips_interrupt_number_of_vectors = MAX_VECTORS;
diff --git a/c/src/lib/libcpu/mips/tx39/.cvsignore b/c/src/lib/libcpu/mips/tx39/.cvsignore
new file mode 100644
index 0000000000..525275c115
--- /dev/null
+++ b/c/src/lib/libcpu/mips/tx39/.cvsignore
@@ -0,0 +1,13 @@
+Makefile
+Makefile.in
+aclocal.m4
+config.cache
+config.guess
+config.log
+config.status
+config.sub
+configure
+depcomp
+install-sh
+missing
+mkinstalldirs
diff --git a/c/src/lib/libcpu/mips/tx39/Makefile.am b/c/src/lib/libcpu/mips/tx39/Makefile.am
new file mode 100644
index 0000000000..4a691c2fc2
--- /dev/null
+++ b/c/src/lib/libcpu/mips/tx39/Makefile.am
@@ -0,0 +1,11 @@
+##
+## $Id$
+##
+
+AUTOMAKE_OPTIONS = foreign 1.4
+ACLOCAL_AMFLAGS = -I ../../../../../../aclocal
+
+SUBDIRS = include
+
+include $(top_srcdir)/../../../../../automake/subdirs.am
+include $(top_srcdir)/../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/mips/tx39/include/.cvsignore b/c/src/lib/libcpu/mips/tx39/include/.cvsignore
new file mode 100644
index 0000000000..525275c115
--- /dev/null
+++ b/c/src/lib/libcpu/mips/tx39/include/.cvsignore
@@ -0,0 +1,13 @@
+Makefile
+Makefile.in
+aclocal.m4
+config.cache
+config.guess
+config.log
+config.status
+config.sub
+configure
+depcomp
+install-sh
+missing
+mkinstalldirs
diff --git a/c/src/lib/libcpu/mips/tx39/include/Makefile.am b/c/src/lib/libcpu/mips/tx39/include/Makefile.am
new file mode 100644
index 0000000000..2c680fb005
--- /dev/null
+++ b/c/src/lib/libcpu/mips/tx39/include/Makefile.am
@@ -0,0 +1,22 @@
+##
+## $Id$
+##
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+H_FILES = tx3904.h
+
+$(PROJECT_INCLUDE)/libcpu:
+ $(mkinstalldirs) $@
+
+$(PROJECT_INCLUDE)/libcpu/%.h: %.h
+ $(INSTALL_DATA) $< $@
+
+TMPINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu \
+ $(H_FILES:%.h=$(PROJECT_INCLUDE)/libcpu/%.h)
+
+all-local: $(TMPINSTALL_FILES)
+
+EXTRA_DIST = tx3904.h
+
+include $(top_srcdir)/../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/mips/tx39/include/tx3904.h b/c/src/lib/libcpu/mips/tx39/include/tx3904.h
new file mode 100644
index 0000000000..ac0efae1f6
--- /dev/null
+++ b/c/src/lib/libcpu/mips/tx39/include/tx3904.h
@@ -0,0 +1,63 @@
+/*
+ * MIPS Tx3904 specific information
+ *
+ * NOTE: This is far from complete. --joel (13 Dec 2000)
+ *
+ * $Id$
+ */
+
+#ifndef __TX3904_h
+#define __TX3904_h
+
+/*
+ * Timer Base Addresses and Offsets
+ */
+
+#define TX3904_TIMER0_BASE 0xFFFFF000
+#define TX3904_TIMER1_BASE 0xFFFFF100
+#define TX3904_TIMER2_BASE 0xFFFFF200
+
+#define TX3904_TIMER_TCR 0x00
+#define TX3904_TIMER_TISR 0x04
+#define TX3904_TIMER_CPRA 0x08
+#define TX3904_TIMER_CPRB 0x0C
+#define TX3904_TIMER_ITMR 0x10
+#define TX3904_TIMER_CCDR 0x20
+#define TX3904_TIMER_PGMR 0x30
+#define TX3904_TIMER_WTMR 0x40
+#define TX3904_TIMER_TRR 0xF0
+
+#define TX3904_TIMER_READ( _base, _register ) \
+ *((volatile unsigned32 *)((_base) + (_register)))
+
+#define TX3904_TIMER_WRITE( _base, _register, _value ) \
+ *((volatile unsigned32 *)((_base) + (_register))) = (_value)
+
+/*
+ * Interrupt Vector Numbers
+ *
+ * NOTE: Numbers 0-15 directly map to levels on the IRC.
+ * Number 16 is "1xxxx" per p. 164 of the TX3904 manual.
+ */
+
+#define TX3904_IRQ_INT1 0
+#define TX3904_IRQ_INT2 1
+#define TX3904_IRQ_INT3 2
+#define TX3904_IRQ_INT4 3
+#define TX3904_IRQ_INT5 4
+#define TX3904_IRQ_INT6 5
+#define TX3904_IRQ_INT7 6
+#define TX3904_IRQ_DMAC3 7
+#define TX3904_IRQ_DMAC2 8
+#define TX3904_IRQ_DMAC1 9
+#define TX3904_IRQ_DMAC0 10
+#define TX3904_IRQ_SIO0 11
+#define TX3904_IRQ_SIO1 12
+#define TX3904_IRQ_TMR0 13
+#define TX3904_IRQ_TMR1 14
+#define TX3904_IRQ_TMR2 15
+#define TX3904_IRQ_INT0 16
+#define TX3904_IRQ_SOFTWARE_1 17
+#define TX3904_IRQ_SOFTWARE_2 18
+
+#endif