diff options
Diffstat (limited to 'c/src/lib/libcpu/sh/sh7750')
| -rw-r--r-- | c/src/lib/libcpu/sh/sh7750/clock/ckinit.c | 56 | ||||
| -rw-r--r-- | c/src/lib/libcpu/sh/sh7750/include/rtems/score/iosh7750.h | 8 | ||||
| -rw-r--r-- | c/src/lib/libcpu/sh/sh7750/include/rtems/score/ipl.h | 4 | ||||
| -rw-r--r-- | c/src/lib/libcpu/sh/sh7750/include/rtems/score/ispsh7750.h | 4 | ||||
| -rw-r--r-- | c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh4_regs.h | 10 | ||||
| -rw-r--r-- | c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh7750_regs.h | 58 | ||||
| -rw-r--r-- | c/src/lib/libcpu/sh/sh7750/sci/console.c | 14 | ||||
| -rw-r--r-- | c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c | 78 | ||||
| -rw-r--r-- | c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c | 22 | ||||
| -rw-r--r-- | c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c | 22 | ||||
| -rw-r--r-- | c/src/lib/libcpu/sh/sh7750/timer/timer.c | 48 |
11 files changed, 162 insertions, 162 deletions
diff --git a/c/src/lib/libcpu/sh/sh7750/clock/ckinit.c b/c/src/lib/libcpu/sh/sh7750/clock/ckinit.c index 05bd7214aa..9fb729bec6 100644 --- a/c/src/lib/libcpu/sh/sh7750/clock/ckinit.c +++ b/c/src/lib/libcpu/sh/sh7750/clock/ckinit.c @@ -70,11 +70,11 @@ rtems_isr_entry Old_ticker; * * PARAMETERS: * vector - interrupt vector number - * + * * RETURNS: * none */ -rtems_isr +rtems_isr Clock_isr(rtems_vector_number vector) { uint16_t tcr; @@ -103,7 +103,7 @@ Clock_isr(rtems_vector_number vector) * SIDE EFFECTS: * Establish clock interrupt handler, configure Timer 0 hardware */ -void +void Install_clock(rtems_isr_entry clock_isr) { int cpudiv = 1; /* CPU frequency divider */ @@ -111,7 +111,7 @@ Install_clock(rtems_isr_entry clock_isr) uint32_t timer_divider; /* Calculated Timer Divider value */ uint8_t temp8; uint16_t temp16; - + /* * Initialize the clock tick device driver variables */ @@ -124,27 +124,27 @@ Install_clock(rtems_isr_entry clock_isr) case SH7750_FRQCR_IFCDIV1: cpudiv = 1; break; - + case SH7750_FRQCR_IFCDIV2: cpudiv = 2; break; - + case SH7750_FRQCR_IFCDIV3: cpudiv = 3; break; - + case SH7750_FRQCR_IFCDIV4: cpudiv = 4; break; - + case SH7750_FRQCR_IFCDIV6: cpudiv = 6; break; - + case SH7750_FRQCR_IFCDIV8: cpudiv = 8; break; - + default: rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); } @@ -155,35 +155,35 @@ Install_clock(rtems_isr_entry clock_isr) case SH7750_FRQCR_PFCDIV2: tidiv = 2 * CLOCK_PRESCALER; break; - + case SH7750_FRQCR_PFCDIV3: tidiv = 3 * CLOCK_PRESCALER; break; - + case SH7750_FRQCR_PFCDIV4: tidiv = 4 * CLOCK_PRESCALER; break; - + case SH7750_FRQCR_PFCDIV6: tidiv = 6 * CLOCK_PRESCALER; break; - + case SH7750_FRQCR_PFCDIV8: tidiv = 8 * CLOCK_PRESCALER; break; - + default: rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); } - timer_divider = - (rtems_cpu_configuration_get_clicks_per_second() * + timer_divider = + (rtems_cpu_configuration_get_clicks_per_second() * cpudiv / (tidiv*1000000)) * rtems_configuration_get_microseconds_per_tick(); /* * Hardware specific initialization */ - + /* Stop the Timer 0 */ temp8 = read8(SH7750_TSTR); temp8 &= ~SH7750_TSTR_STR0; @@ -197,7 +197,7 @@ Install_clock(rtems_isr_entry clock_isr) /* Load divider */ write32(timer_divider, SH7750_TCOR0); - + write16( SH7750_TCR_UNIE | /* Enable Underflow Interrupt */ SH7750_TCR_CKEG_RAISE | /* Count on rising edge */ @@ -233,7 +233,7 @@ Install_clock(rtems_isr_entry clock_isr) * SIDE EFFECTS: * Stop Timer 0 counting, set timer 0 interrupt priority level to 0. */ -void +void Clock_exit(void) { uint8_t temp8 = 0; @@ -264,19 +264,19 @@ Clock_exit(void) * RETURNS: * RTEMS_SUCCESSFUL */ -rtems_device_driver -Clock_initialize(rtems_device_major_number major, +rtems_device_driver +Clock_initialize(rtems_device_major_number major, rtems_device_minor_number minor, void *pargp) { Install_clock( Clock_isr ); - + /* * make major/minor avail to others such as shared memory driver */ rtems_clock_major = major; rtems_clock_minor = minor; - + return RTEMS_SUCCESSFUL; } @@ -291,21 +291,21 @@ Clock_initialize(rtems_device_major_number major, * RETURNS: * RTEMS_SUCCESSFUL */ -rtems_device_driver +rtems_device_driver Clock_control(rtems_device_major_number major, rtems_device_minor_number minor, void *pargp) { uint32_t isrlevel; rtems_libio_ioctl_args_t *args = pargp; - + if (args != 0) { /* * This is hokey, but until we get a defined interface * to do this, it will just be this simple... */ - + if (args->command == rtems_build_name('I', 'S', 'R', ' ')) { Clock_isr(CLOCK_VECTOR); @@ -315,7 +315,7 @@ Clock_control(rtems_device_major_number major, rtems_isr_entry ignored ; rtems_interrupt_disable( isrlevel ); rtems_interrupt_catch( args->buffer, CLOCK_VECTOR, &ignored ); - + rtems_interrupt_enable( isrlevel ); } } diff --git a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/iosh7750.h b/c/src/lib/libcpu/sh/sh7750/include/rtems/score/iosh7750.h index 0a3d7a16a5..c586348ebf 100644 --- a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/iosh7750.h +++ b/c/src/lib/libcpu/sh/sh7750/include/rtems/score/iosh7750.h @@ -7,7 +7,7 @@ * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and * Bernd Becker (becker@faw.uni-ulm.de) * - * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which + * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which * contained no copyright notice. * * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany @@ -15,7 +15,7 @@ * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * + * * * COPYRIGHT (c) 1998. * On-Line Applications Research Corporation (OAR). @@ -24,8 +24,8 @@ * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * - * Modified to reflect on-chip registers for sh7045 processor, based on - * "Register.h" distributed with Hitachi's EVB7045F tutorials, and which + * Modified to reflect on-chip registers for sh7045 processor, based on + * "Register.h" distributed with Hitachi's EVB7045F tutorials, and which * contained no copyright notice: * John M. Mills (jmills@tga.com) * TGA Technologies, Inc. diff --git a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/ipl.h b/c/src/lib/libcpu/sh/sh7750/include/rtems/score/ipl.h index 0dbc3cff11..f59d575cbe 100644 --- a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/ipl.h +++ b/c/src/lib/libcpu/sh/sh7750/include/rtems/score/ipl.h @@ -27,8 +27,8 @@ extern "C" { #define IPL_DRIVER_TABLE_ENTRY \ { ipl_console_initialize, ipl_console_open, ipl_console_close, \ ipl_console_read, ipl_console_write, ipl_console_control } - - + + #define NULL_SUCCESSFUL RTEMS_SUCCESSFUL rtems_device_driver ipl_console_initialize( diff --git a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/ispsh7750.h b/c/src/lib/libcpu/sh/sh7750/include/rtems/score/ispsh7750.h index 2361b32137..93e14f6ce7 100644 --- a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/ispsh7750.h +++ b/c/src/lib/libcpu/sh/sh7750/include/rtems/score/ispsh7750.h @@ -14,7 +14,7 @@ * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * + * * * COPYRIGHT (c) 1998. * On-Line Applications Research Corporation (OAR). @@ -28,7 +28,7 @@ * TGA Technologies, Inc. * 100 Pinnacle Way, Suite 140 * Norcross, GA 30071 U.S.A. - * + * * * This modified file may be copied and distributed in accordance * the above-referenced license. It is provided for critique and diff --git a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh4_regs.h b/c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh4_regs.h index b165b23ace..184d1f2d91 100644 --- a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh4_regs.h +++ b/c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh4_regs.h @@ -8,7 +8,7 @@ * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. - * + * * @(#) $Id$ */ @@ -20,14 +20,14 @@ #define SH4_SR_RB 0x20000000 /* General register bank specifier */ #define SH4_SR_BL 0x10000000 /* Exeption/interrupt masking bit */ #define SH4_SR_FD 0x00008000 /* FPU disable bit */ -#define SH4_SR_M 0x00000200 /* For signed division: +#define SH4_SR_M 0x00000200 /* For signed division: divisor (module) is negative */ -#define SH4_SR_Q 0x00000100 /* For signed division: +#define SH4_SR_Q 0x00000100 /* For signed division: dividend (and quotient) is negative */ #define SH4_SR_IMASK 0x000000f0 /* Interrupt mask level */ #define SH4_SR_IMASK_S 4 #define SH4_SR_S 0x00000002 /* Saturation for MAC instruction: - if set, data in MACH/L register + if set, data in MACH/L register is restricted to 48/32 bits for MAC.W/L instructions */ #define SH4_SR_T 0x00000001 /* 1 if last condiyion was true */ @@ -36,7 +36,7 @@ /* FPSCR -- FPU Starus/Control Register */ #define SH4_FPSCR_FR 0x00200000 /* FPU register bank specifier */ #define SH4_FPSCR_SZ 0x00100000 /* FMOV 64-bit transfer mode */ -#define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point +#define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point operations flag */ /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */ #define SH4_FPSCR_DN 0x00040000 /* Treat denormalized number as zero */ diff --git a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh7750_regs.h b/c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh7750_regs.h index d047609863..b87cccbc2c 100644 --- a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh7750_regs.h +++ b/c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh7750_regs.h @@ -12,26 +12,26 @@ * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. - * + * * @(#) $Id$ */ #ifndef __SH7750_REGS_H__ #define __SH7750_REGS_H__ -/* - * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and +/* + * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and * in 0x1f000000 - 0x1fffffff (area 7 address) */ -#define SH7750_P4_BASE 0xff000000 /* Accessable only in +#define SH7750_P4_BASE 0xff000000 /* Accessable only in priveleged mode */ #define SH7750_A7_BASE 0x1f000000 /* Accessable only using TLB */ #define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs)) #define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs)) -/* - * MMU Registers +/* + * MMU Registers */ /* Page Table Entry High register - PTEH */ @@ -61,9 +61,9 @@ #define SH7750_PTEL_PR_RWPO 0x00000020 /* read-write in priv mode */ #define SH7750_PTEL_PR_ROPU 0x00000040 /* read-only in priv or user mode*/ #define SH7750_PTEL_PR_RWPU 0x00000060 /* read-write in priv or user mode*/ -#define SH7750_PTEL_C 0x00000008 /* Cacheability +#define SH7750_PTEL_C 0x00000008 /* Cacheability (0 - page not cacheable) */ -#define SH7750_PTEL_D 0x00000004 /* Dirty bit (1 - write has been +#define SH7750_PTEL_D 0x00000004 /* Dirty bit (1 - write has been performed to a page) */ #define SH7750_PTEL_SH 0x00000002 /* Share Status bit (1 - page are shared by processes) */ @@ -130,12 +130,12 @@ #define SH7750_CCR_A7 SH7750_A7_REG32(SH7750_CCR_REGOFS) #define SH7750_CCR_IIX 0x00008000 /* IC index enable bit */ -#define SH7750_CCR_ICI 0x00000800 /* IC invalidation bit: +#define SH7750_CCR_ICI 0x00000800 /* IC invalidation bit: set it to clear IC */ #define SH7750_CCR_ICE 0x00000100 /* IC enable bit */ #define SH7750_CCR_OIX 0x00000080 /* OC index enable bit */ -#define SH7750_CCR_ORA 0x00000020 /* OC RAM enable bit - if you set OCE = 0, +#define SH7750_CCR_ORA 0x00000020 /* OC RAM enable bit + if you set OCE = 0, you should set ORA = 0 */ #define SH7750_CCR_OCI 0x00000008 /* OC invalidation bit */ #define SH7750_CCR_CB 0x00000004 /* Copy-back bit for P1 area */ @@ -166,7 +166,7 @@ #define SH7750_TRA_IMM_S 2 /* Exeption event register - EXPEVT */ -#define SH7750_EXPEVT_REGOFS 0x000024 +#define SH7750_EXPEVT_REGOFS 0x000024 #define SH7750_EXPEVT SH7750_P4_REG32(SH7750_EXPEVT_REGOFS) #define SH7750_EXPEVT_A7 SH7750_A7_REG32(SH7750_EXPEVT_REGOFS) @@ -174,7 +174,7 @@ #define SH7750_EXPEVT_EX_S 0 /* Interrupt event register */ -#define SH7750_INTEVT_REGOFS 0x000028 +#define SH7750_INTEVT_REGOFS 0x000028 #define SH7750_INTEVT SH7750_P4_REG32(SH7750_INTEVT_REGOFS) #define SH7750_INTEVT_A7 SH7750_A7_REG32(SH7750_INTEVT_REGOFS) #define SH7750_INTEVT_EX 0x00000fff /* Exeption code */ @@ -254,7 +254,7 @@ /* Peripheral Module Interrupts - Memory Refresh Unit (REF) */ #define SH7750_EVT_REF_RCMI 0x580 /* Compare-match Interrupt */ -#define SH7750_EVT_REF_ROVI 0x5A0 /* Refresh Counter Overflow +#define SH7750_EVT_REF_ROVI 0x5A0 /* Refresh Counter Overflow interrupt */ /* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */ @@ -292,7 +292,7 @@ standby mode: 0 - normal state 1 - high-impendance state */ - + #define SH7750_STBCR_PPU 0x20 /* Peripheral module pins pull-up controls*/ #define SH7750_STBCR_MSTP4 0x10 /* Stopping the clock supply to DMAC */ #define SH7750_STBCR_DMAC_STP SH7750_STBCR_MSTP4 @@ -331,7 +331,7 @@ #define SH7750_FRQCR SH7750_P4_REG32(SH7750_FRQCR_REGOFS) #define SH7750_FRQCR_A7 SH7750_A7_REG32(SH7750_FRQCR_REGOFS) -#define SH7750_FRQCR_CKOEN 0x0800 /* Clock Output Enable +#define SH7750_FRQCR_CKOEN 0x0800 /* Clock Output Enable 0 - CKIO pin goes to HiZ/pullup 1 - Clock is output from CKIO */ #define SH7750_FRQCR_PLL1EN 0x0400 /* PLL circuit 1 enable */ @@ -364,7 +364,7 @@ /* * Watchdog Timer (WDT) */ - + /* Watchdog Timer Counter register - WTCNT */ #define SH7750_WTCNT_REGOFS 0xC00008 /* offset */ #define SH7750_WTCNT SH7750_P4_REG32(SH7750_WTCNT_REGOFS) @@ -621,7 +621,7 @@ #define SH7750_BCR1_A7 SH7750_A7_REG32(SH7750_BCR1_REGOFS) #define SH7750_BCR1_ENDIAN 0x80000000 /* Endianness (1 - little endian) */ #define SH7750_BCR1_MASTER 0x40000000 /* Master/Slave mode (1-master) */ -#define SH7750_BCR1_A0MPX 0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX)*/ +#define SH7750_BCR1_A0MPX 0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX)*/ #define SH7750_BCR1_IPUP 0x02000000 /* Input Pin Pull-up Control: 0 - pull-up resistor is on for control input pins @@ -643,7 +643,7 @@ #define SH7750_BCR1_BREQEN 0x00080000 /* BREQ Enable: 0 - External requests are not accepted - 1 - External requests are + 1 - External requests are accepted */ #define SH7750_BCR1_PSHR 0x00040000 /* Partial Sharing Bit: 0 - Master Mode @@ -877,14 +877,14 @@ #define SH7750_MCR_TCAS_1 0x00000000 /* 1 */ #define SH7750_MCR_TCAS_2 0x00800000 /* 2 */ -#define SH7750_MCR_TPC 0x00380000 /* DRAM: RAS Precharge Period +#define SH7750_MCR_TPC 0x00380000 /* DRAM: RAS Precharge Period SDRAM: minimum number of cycles until the next bank active cmd is output after precharging */ #define SH7750_MCR_TPC_S 19 #define SH7750_MCR_TPC_SDRAM_1 0x00000000 /* 1 cycle */ #define SH7750_MCR_TPC_SDRAM_2 0x00080000 /* 2 cycles */ -#define SH7750_MCR_TPC_SDRAM_3 0x00100000 /* 3 cycles */ +#define SH7750_MCR_TPC_SDRAM_3 0x00100000 /* 3 cycles */ #define SH7750_MCR_TPC_SDRAM_4 0x00180000 /* 4 cycles */ #define SH7750_MCR_TPC_SDRAM_5 0x00200000 /* 5 cycles */ #define SH7750_MCR_TPC_SDRAM_6 0x00280000 /* 6 cycles */ @@ -1148,7 +1148,7 @@ #define SH7750_CHCR_DSA_AMEM16 0x0E000000 /* 16-bit attribute memory space */ #define SH7750_CHCR_DTC 0x01000000 /* Destination Address Wait Control - Select, specifies CS5 or CS6 + Select, specifies CS5 or CS6 space wait control for PCMCIA access */ @@ -1186,8 +1186,8 @@ Address Mode (External Addr Space -> External Device) */ #define SH7750_CHCR_RS_ER_SA_ED_TO_EA 0x300 /* External Request, Single - Address Mode, (External - Device -> External Addr + Address Mode, (External + Device -> External Addr Space)*/ #define SH7750_CHCR_RS_AR_EA_TO_EA 0x400 /* Auto-Request (External Addr Space -> External Addr Space)*/ @@ -1195,7 +1195,7 @@ #define SH7750_CHCR_RS_AR_EA_TO_OCP 0x500 /* Auto-Request (External Addr Space -> On-chip Peripheral Module) */ -#define SH7750_CHCR_RS_AR_OCP_TO_EA 0x600 /* Auto-Request (On-chip +#define SH7750_CHCR_RS_AR_OCP_TO_EA 0x600 /* Auto-Request (On-chip Peripheral Module -> External Addr Space */ #define SH7750_CHCR_RS_SCITX_EA_TO_SC 0x800 /* SCI Transmit-Data-Empty intr @@ -1206,7 +1206,7 @@ External Addr Space) */ #define SH7750_CHCR_RS_SCIFTX_EA_TO_SC 0xA00 /* SCIF Transmit-Data-Empty intr transfer request (external - address space -> SCFTDR1) */ + address space -> SCFTDR1) */ #define SH7750_CHCR_RS_SCIFRX_SC_TO_EA 0xB00 /* SCIF Receive-Data-Full intr transfer request (SCFRDR2 -> External Addr Space) */ @@ -1341,7 +1341,7 @@ #define SH7750_SCSSR1_TDRE 0x80 /* Transmit Data Register Empty */ #define SH7750_SCSSR1_RDRF 0x40 /* Receive Data Register Full */ -#define SH7750_SCSSR1_ORER 0x20 /* Overrun Error */ +#define SH7750_SCSSR1_ORER 0x20 /* Overrun Error */ #define SH7750_SCSSR1_FER 0x10 /* Framing Error */ #define SH7750_SCSSR1_PER 0x08 /* Parity Error */ #define SH7750_SCSSR1_TEND 0x04 /* Transmit End */ @@ -1569,7 +1569,7 @@ #define SH7750_IPRA_RTC_S 0 /* Interrupt Priority Register B - IPRB (half) */ -#define SH7750_IPRB_REGOFS 0xD00008 /* offset */ +#define SH7750_IPRB_REGOFS 0xD00008 /* offset */ #define SH7750_IPRB SH7750_P4_REG32(SH7750_IPRB_REGOFS) #define SH7750_IPRB_A7 SH7750_A7_REG32(SH7750_IPRB_REGOFS) @@ -1596,7 +1596,7 @@ #define SH7750_IPRC_HUDI_S 0 -/* +/* * User Break Controller registers */ #define SH7750_BARA 0x200000 /* Break address regiser A */ diff --git a/c/src/lib/libcpu/sh/sh7750/sci/console.c b/c/src/lib/libcpu/sh/sh7750/sci/console.c index 95e03285b7..e5a7cab52b 100644 --- a/c/src/lib/libcpu/sh/sh7750/sci/console.c +++ b/c/src/lib/libcpu/sh/sh7750/sci/console.c @@ -157,10 +157,10 @@ console_first_open(int major, int minor, void *arg) args->iop->data1, /* tty */ minor+1, /* channel */ (console_mode == CONSOLE_MODE_INT)); - + if (sc == RTEMS_SUCCESSFUL) sc = sh4uart_reset(&sh4_uarts[minor]); - + return sc; } @@ -193,7 +193,7 @@ console_last_close(int major, int minor, void *arg) void console_reserve_resources(rtems_configuration_table *configuration) { - if ((console_mode != CONSOLE_MODE_RAW) && + if ((console_mode != CONSOLE_MODE_RAW) && (console_mode != CONSOLE_MODE_IPL)) rtems_termios_reserve_resources (configuration, 2); } @@ -233,7 +233,7 @@ console_initialize(rtems_device_major_number major, if ((console_mode != CONSOLE_MODE_RAW) && (console_mode != CONSOLE_MODE_IPL)) rtems_termios_initialize (); - + /* * Register the devices */ @@ -265,7 +265,7 @@ console_initialize(rtems_device_major_number major, sc = sh4uart_reset(&sh4_uarts[1]); return sc; - } + } return RTEMS_SUCCESSFUL; } @@ -348,7 +348,7 @@ console_close(rtems_device_major_number major, return rtems_termios_close (arg); else return RTEMS_SUCCESSFUL; -} +} /* console_read -- * Read from the console device @@ -425,7 +425,7 @@ console_write(rtems_device_major_number major, char *buf = argp->buffer; int count = argp->count; int i; - + for (i = 0; i < count; i++) { if (*buf == '\n') diff --git a/c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c b/c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c index 34e2f70b4b..94e0ec9e34 100644 --- a/c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c +++ b/c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c @@ -72,15 +72,15 @@ sh4uart_init(sh4uart *uart, void *tty, int chn, int int_driven) /* * sh4uart_get_Pph -- * Get current peripheral module clock. - * + * * PARAMETERS: none; - * Cpu clock is get from CPU_CLOCK_RATE_HZ marco + * Cpu clock is get from CPU_CLOCK_RATE_HZ marco * (defined in bspopts.h, included from bsp.h) * * RETURNS: * peripheral module clock in Hz. */ -uint32_t +uint32_t sh4uart_get_Pph(void) { uint16_t frqcr = *(volatile uint16_t*)SH7750_FRQCR; @@ -114,7 +114,7 @@ sh4uart_get_Pph(void) default: /* unreachable */ break; } - + switch (frqcr & SH7750_FRQCR_PFC) { case SH7750_FRQCR_PFCDIV2: @@ -202,7 +202,7 @@ sh4uart_set_baudrate(sh4uart *uart, speed_t baud) /* Set default baudrate if specified baudrate is impossible */ if (n >= 4) sh4uart_set_baudrate(uart, B9600); - + SCSMR(uart->chn) &= ~SH7750_SCSMR_CKS; SCSMR(uart->chn) |= n << SH7750_SCSMR_CKS_S; SCBRR(uart->chn) = div; @@ -240,7 +240,7 @@ sh4uart_reset(sh4uart *uart) SCSMR(chn) = 0x0; /* 8-bit, non-parity, 1 stop bit, pf/1 clock */ if (chn == SH4_SCIF) - SCFCR2 = SH7750_SCFCR2_TFRST | SH7750_SCFCR2_RFRST | + SCFCR2 = SH7750_SCFCR2_TFRST | SH7750_SCFCR2_RFRST | SH7750_SCFCR2_RTRG_1 | SH7750_SCFCR2_TTRG_4; if (chn == SH4_SCI) @@ -259,13 +259,13 @@ sh4uart_reset(sh4uart *uart) ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRB_SCI1_S; IPRB = ipr; - rc = rtems_interrupt_catch(sh4uart1_interrupt_transmit, - SH7750_EVT_TO_NUM(SH7750_EVT_SCI_TXI), + rc = rtems_interrupt_catch(sh4uart1_interrupt_transmit, + SH7750_EVT_TO_NUM(SH7750_EVT_SCI_TXI), &uart->old_handler_transmit); if (rc != RTEMS_SUCCESSFUL) return rc; - rc = rtems_interrupt_catch(sh4uart1_interrupt_receive, - SH7750_EVT_TO_NUM(SH7750_EVT_SCI_RXI), + rc = rtems_interrupt_catch(sh4uart1_interrupt_receive, + SH7750_EVT_TO_NUM(SH7750_EVT_SCI_RXI), &uart->old_handler_receive); if (rc != RTEMS_SUCCESSFUL) return rc; @@ -277,13 +277,13 @@ sh4uart_reset(sh4uart *uart) ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRC_SCIF_S; IPRC = ipr; - rc = rtems_interrupt_catch(sh4uart2_interrupt_transmit, - SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_TXI), + rc = rtems_interrupt_catch(sh4uart2_interrupt_transmit, + SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_TXI), &uart->old_handler_transmit); if (rc != RTEMS_SUCCESSFUL) return rc; - rc = rtems_interrupt_catch(sh4uart2_interrupt_receive, - SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_RXI), + rc = rtems_interrupt_catch(sh4uart2_interrupt_receive, + SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_RXI), &uart->old_handler_receive); if (rc != RTEMS_SUCCESSFUL) return rc; @@ -295,10 +295,10 @@ sh4uart_reset(sh4uart *uart) sh4uart_set_baudrate(uart, B38400); /* debug defaults (unfortunately, it is differ to termios default */ - SCSCR(chn) = SH7750_SCSCR_TE | SH7750_SCSCR_RE | - (chn == SH4_SCI ? 0x0 : SH7750_SCSCR2_REIE) | + SCSCR(chn) = SH7750_SCSCR_TE | SH7750_SCSCR_RE | + (chn == SH4_SCI ? 0x0 : SH7750_SCSCR2_REIE) | (int_driven ? (SH7750_SCSCR_RIE | SH7750_SCSCR_TIE) : 0x0); - + return RTEMS_SUCCESSFUL; } @@ -324,15 +324,15 @@ sh4uart_disable(sh4uart *uart, int disable_port) if (uart->int_driven) { - rc = rtems_interrupt_catch(uart->old_handler_transmit, - uart->chn == SH4_SCI ? - SH7750_EVT_SCI_TXI : SH7750_EVT_SCIF_TXI, + rc = rtems_interrupt_catch(uart->old_handler_transmit, + uart->chn == SH4_SCI ? + SH7750_EVT_SCI_TXI : SH7750_EVT_SCIF_TXI, NULL); if (rc != RTEMS_SUCCESSFUL) return rc; - rc = rtems_interrupt_catch(uart->old_handler_receive, - uart->chn == SH4_SCI ? - SH7750_EVT_SCI_RXI : SH7750_EVT_SCIF_RXI, + rc = rtems_interrupt_catch(uart->old_handler_receive, + uart->chn == SH4_SCI ? + SH7750_EVT_SCI_RXI : SH7750_EVT_SCIF_RXI, NULL); if (rc != RTEMS_SUCCESSFUL) return rc; @@ -359,7 +359,7 @@ sh4uart_set_attributes(sh4uart *uart, const struct termios *t) int level; speed_t baud; uint16_t smr; - + smr = (uint16_t)(*(uint8_t*)SH7750_SCSMR(uart->chn)); baud = cfgetospeed(t); @@ -473,7 +473,7 @@ sh4uart_poll_read(sh4uart *uart) if (chn == SH4_SCI) { - if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER | + if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER | SH7750_SCSSR1_ORER)) != 0) { error_occured = 1; @@ -487,7 +487,7 @@ sh4uart_poll_read(sh4uart *uart) else { if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR | - SH7750_SCSSR2_BRK)) != 0 || + SH7750_SCSSR2_BRK)) != 0 || (SCLSR2 & SH7750_SCLSR2_ORER) != 0) { error_occured = 1; @@ -560,15 +560,15 @@ sh4uart_poll_write(sh4uart *uart, const char *buf, int len) while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0) { int i; - for (i = 0; - i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 & - SH7750_SCFCR2_TTRG); + for (i = 0; + i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 & + SH7750_SCFCR2_TTRG); i++) { SCTDR2 = *buf++; len--; } - while ((SCSSR2 & SH7750_SCSSR2_TDFE) == 0 || + while ((SCSSR2 & SH7750_SCSSR2_TDFE) == 0 || (SCSSR2 & SH7750_SCSSR2_TEND) == 0); SCSSR2 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND); } @@ -604,7 +604,7 @@ sh4uart1_interrupt_receive(rtems_vector_number vec) if ((bp < sizeof(buf) - 1) && ((SCSSR1 & SH7750_SCSSR1_RDRF) != 0)) { /* Receive character and handle frame/parity errors */ - if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER | + if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER | SH7750_SCSSR1_ORER)) != 0) { if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER)) @@ -661,7 +661,7 @@ sh4uart2_interrupt_receive(rtems_vector_number vec) if ((bp < sizeof(buf) - 1) && ((SCSSR2 & SH7750_SCSSR2_RDF) != 0)) { if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR | - SH7750_SCSSR2_BRK)) != 0 || + SH7750_SCSSR2_BRK)) != 0 || (SH7750_SCLSR2 & SH7750_SCLSR2_ORER) != 0) { if (SCSSR2 & SH7750_SCSSR2_ER) @@ -687,7 +687,7 @@ sh4uart2_interrupt_receive(rtems_vector_number vec) else buf[bp++] = 0x00; /* XXX -- SIGINT */ } - + sh4uart_handle_error(uart); } else @@ -722,7 +722,7 @@ sh4uart1_interrupt_transmit(rtems_vector_number vec) if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len) { - while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0 && + while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0 && uart->tx_ptr < uart->tx_buf_len) { SCTDR1 = uart->tx_buf[uart->tx_ptr++]; @@ -764,9 +764,9 @@ sh4uart2_interrupt_transmit(rtems_vector_number vec) while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0) { int i; - for (i = 0; - i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 & - SH7750_SCFCR2_TTRG); + for (i = 0; + i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 & + SH7750_SCFCR2_TTRG); i++) SCTDR2 = uart->tx_buf[uart->tx_ptr++]; while ((SCSSR1 & SH7750_SCSSR1_TDRE) == 0 || @@ -807,7 +807,7 @@ sh4uart_interrupt_write(sh4uart *uart, const char *buf, int len) while ((SCSSR1 & SH7750_SCSSR1_TEND) == 0); rtems_interrupt_disable(level); - + uart->tx_buf = buf; uart->tx_buf_len = len; uart->tx_ptr = 0; @@ -932,7 +932,7 @@ int ipl_console_poll_write(int minor, const char *buf, int len) { int c; - while (len > 0) + while (len > 0) { c = (len < 64 ? len : 64); ipl_serial_output(buf, c); diff --git a/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c index a541ab471c..574efd6f40 100644 --- a/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c +++ b/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c @@ -13,7 +13,7 @@ * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * + * * * COPYRIGHT (c) 1998. * On-Line Applications Research Corporation (OAR). @@ -48,7 +48,7 @@ extern proc_ptr _Hardware_isr_Table[]; unsigned long *_old_stack_ptr; #endif -register unsigned long *stack_ptr asm("r15"); +register unsigned long *stack_ptr asm("r15"); /* * _CPU_Context_save_fp_context @@ -68,7 +68,7 @@ void _CPU_Context_save_fp( ) { #if SH_HAS_FPU - + asm volatile("\n\ mov.l @%0,r4 \n\ add %1,r4\n\ @@ -95,12 +95,12 @@ asm volatile("\n\ fmov xd4,@-r4\n\ fmov xd2,@-r4\n\ fmov xd0,@-r4\n\ - " + " #endif "lds %4,fpscr\n\ " - : - : "r"(fp_context_ptr), "r"(sizeof(Context_Control_fp)), + : + : "r"(fp_context_ptr), "r"(sizeof(Context_Control_fp)), "r"(SH4_FPSCR_SZ), "r"(SH4_FPSCR_PR | SH4_FPSCR_SZ), "r"(SH4_FPSCR_PR) : "r4", "r0"); @@ -154,7 +154,7 @@ asm volatile("\n\ fmov @r4+,dr14\n\ lds.l @r4+,fpul\n\ lds.l @r4+,fpscr\n\ - " : + " : : "r"(fp_context_ptr), "r"(SH4_FPSCR_PR | SH4_FPSCR_SZ), "r"(SH4_FPSCR_SZ) : "r4", "r0"); @@ -182,7 +182,7 @@ asm volatile("\n\ */ /* - * FIXME: This is an ugly hack, but we wanted to avoid recalculating + * FIXME: This is an ugly hack, but we wanted to avoid recalculating * the offset each time Context_Control is changed */ void __CPU_Context_switch( @@ -250,10 +250,10 @@ __CPU_Context_restore:\n\ nop" ); } -/* +/* * This routine provides the RTEMS interrupt management. */ - + void __ISR_Handler( uint32_t vector) { register uint32_t level; @@ -290,7 +290,7 @@ void __ISR_Handler( uint32_t vector) if( _ISR_Nest_level == 0 ) /* restore old stack pointer */ - stack_ptr = _old_stack_ptr; + stack_ptr = _old_stack_ptr; #endif _CPU_ISR_Enable( level ); diff --git a/c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c b/c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c index 322c1ba75a..e793483a5e 100644 --- a/c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c +++ b/c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c @@ -13,7 +13,7 @@ * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE - * + * * * COPYRIGHT (c) 1998. * On-Line Applications Research Corporation (OAR). @@ -117,7 +117,7 @@ asm (" .text\n" " .long __VBR_Saved\n" "offset100_k:\n" " .long 0x100\n" - + " .org __vbr_base + 0x400\n" "vbr_400:\n" " mov.l r0,@-r15\n" @@ -155,7 +155,7 @@ asm (" .text\n" " mov.l r5,@-r15 \n" " mov.l r6,@-r15 \n" " mov.l r7,@-r15 \n" -#if 0 +#if 0 " mov.l r8,@-r15 \n" " mov.l r9,@-r15 \n" " mov.l r10,@-r15 \n" @@ -184,7 +184,7 @@ asm (" .text\n" " fmov fr13,@-r15 \n" " fmov fr14,@-r15 \n" " fmov fr15,@-r15 \n" - + " sts.l pr,@-r15 \n" " sts.l mach,@-r15 \n" " sts.l macl,@-r15 \n" @@ -200,7 +200,7 @@ asm (" .text\n" " mov.l @r4,r4 \n" " shlr2 r4 \n" " shlr r4 \n" - + " mov.l _ISR_Table_k,r0\n" " mov.l @r0,r0 \n" " add r4,r0 \n" @@ -247,7 +247,7 @@ asm (" .text\n" " mov.l @r15+,r9 \n" " mov.l @r15+,r8 \n" #endif - + " mov.l @r15+,r7 \n" " mov.l @r15+,r6 \n" " mov.l @r15+,r5 \n" @@ -298,15 +298,15 @@ asm (" .text\n" " lds.l @r15+,fpul \n" " lds.l @r15+,fpscr\n" " mov.l @r15+,r14 \n" - + " mov.l @r15+,r13 \n" " mov.l @r15+,r12 \n" " mov.l @r15+,r11 \n" " mov.l @r15+,r10 \n" " mov.l @r15+,r9 \n" " mov.l @r15+,r8 \n" - - + + " mov.l @r15+,r7 \n" " mov.l @r15+,r6 \n" " mov.l @r15+,r5 \n" @@ -329,10 +329,10 @@ asm (" .text\n" " .long 0x600\n" ); - + /************************************************ - * Dummy interrupt service procedure for + * Dummy interrupt service procedure for * interrupts being not allowed --> Trap 2 ************************************************/ asm(" .section .text\n\ diff --git a/c/src/lib/libcpu/sh/sh7750/timer/timer.c b/c/src/lib/libcpu/sh/sh7750/timer/timer.c index 88c0c839fc..9f43eb0373 100644 --- a/c/src/lib/libcpu/sh/sh7750/timer/timer.c +++ b/c/src/lib/libcpu/sh/sh7750/timer/timer.c @@ -62,7 +62,7 @@ rtems_boolean Timer_driver_Find_average_overhead; * RETURNS: * none */ -void +void Timer_initialize(void) { uint8_t temp8; @@ -81,27 +81,27 @@ Timer_initialize(void) case SH7750_FRQCR_IFCDIV1: cpudiv = 1; break; - + case SH7750_FRQCR_IFCDIV2: cpudiv = 2; break; - + case SH7750_FRQCR_IFCDIV3: cpudiv = 3; break; - + case SH7750_FRQCR_IFCDIV4: cpudiv = 4; break; - + case SH7750_FRQCR_IFCDIV6: cpudiv = 6; break; - + case SH7750_FRQCR_IFCDIV8: cpudiv = 8; break; - + default: rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); } @@ -112,29 +112,29 @@ Timer_initialize(void) case SH7750_FRQCR_PFCDIV2: tidiv = 2 * TIMER_PRESCALER; break; - + case SH7750_FRQCR_PFCDIV3: tidiv = 3 * TIMER_PRESCALER; break; - + case SH7750_FRQCR_PFCDIV4: tidiv = 4 * TIMER_PRESCALER; break; - + case SH7750_FRQCR_PFCDIV6: tidiv = 6 * TIMER_PRESCALER; break; - + case SH7750_FRQCR_PFCDIV8: tidiv = 8 * TIMER_PRESCALER; break; - + default: rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); } - microseconds_divider = - rtems_cpu_configuration_get_clicks_per_second() * cpudiv / + microseconds_divider = + rtems_cpu_configuration_get_clicks_per_second() * cpudiv / (tidiv * 1000000); microseconds_per_int = 0xFFFFFFFF / microseconds_divider; @@ -153,7 +153,7 @@ Timer_initialize(void) /* Reset timer constant and counter */ write32(0xFFFFFFFF, SH7750_TCOR1); write32(0xFFFFFFFF, SH7750_TCNT1); - + /* Select timer mode */ write16( SH7750_TCR_UNIE | /* Enable Underflow Interrupt */ @@ -200,7 +200,7 @@ Timer_initialize(void) * RETURNS: * number of microseconds since timer has been started */ -int +int Read_timer(void) { uint32_t clicks; @@ -208,16 +208,16 @@ Read_timer(void) uint32_t total ; rtems_interrupt_level level; uint32_t tcr; - + _CPU_ISR_Disable(level); clicks = 0xFFFFFFFF - read32(SH7750_TCNT1); tcr = read32(SH7750_TCR1); ints = Timer_interrupts; - + _CPU_ISR_Enable(level); - + /* Handle the case when timer overflowed but interrupt was not processed */ if ((clicks > 0xFF000000) && ((tcr & SH7750_TCR_UNF) != 0)) { @@ -228,7 +228,7 @@ Read_timer(void) if ( Timer_driver_Find_average_overhead ) return total; /* in microsecond units */ - else + else { if ( total < LEAST_VALID ) return 0; /* below timer resolution */ @@ -249,7 +249,7 @@ Read_timer(void) * RETURNS: * RTEMS_SUCCESSFUL */ -rtems_status_code +rtems_status_code Empty_function( void ) { return RTEMS_SUCCESSFUL; @@ -267,18 +267,18 @@ Empty_function( void ) * RETURNS: * none */ -void +void Set_find_average_overhead(rtems_boolean find_flag) { Timer_driver_Find_average_overhead = find_flag; } /* timerisr -- - * Timer interrupt handler routine. This function invoked on timer + * Timer interrupt handler routine. This function invoked on timer * underflow event; once per 2^32 clocks. It should reset the timer * event and increment timer interrupts counter. */ -void +void timerisr(void) { uint8_t temp8; |