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Diffstat (limited to 'c/src/lib/libcpu/bfin/ChangeLog')
| -rw-r--r-- | c/src/lib/libcpu/bfin/ChangeLog | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/c/src/lib/libcpu/bfin/ChangeLog b/c/src/lib/libcpu/bfin/ChangeLog index 1859b4a8b9..2c515d1364 100644 --- a/c/src/lib/libcpu/bfin/ChangeLog +++ b/c/src/lib/libcpu/bfin/ChangeLog @@ -12,20 +12,6 @@ type of interrupt is identified by the central ISR dispatcher bf52x/interrupt or interrupt/. This simplifies the UART ISR. -2011-04-40 Rohan Kangralkar <rkangral@ece.neu.edu> - - * bf52x/include: Added additional MMR. - * bf52x/interrupt: The BF52X processors have a different System interrupt - controller than present in the 53X range of processors. The 52X have 8 - interrupt assignment registers. The implementation uses tables to increase - predictability. - * serial/uart.?: Added DMA based and interrupt based transfer support. The - old uart code used a single ISR for TX and RX and tried to identify and - multiplex inside the ISR. In the new code the type of interrupt is - identified by the central ISR dispatcher bf52x/interrupt or interrupt/. - This simplifies the UART ISR. - - 2011-02-02 Ralf Corsépius <ralf.corsepius@rtems.org> * configure.ac: Require autoconf-2.68, automake-1.11.1. |