diff options
Diffstat (limited to 'c/src/lib/libbsp/sh/gensh2/startup/hw_init.c')
| -rw-r--r-- | c/src/lib/libbsp/sh/gensh2/startup/hw_init.c | 118 |
1 files changed, 61 insertions, 57 deletions
diff --git a/c/src/lib/libbsp/sh/gensh2/startup/hw_init.c b/c/src/lib/libbsp/sh/gensh2/startup/hw_init.c index f0b6e3b90e..72d714086c 100644 --- a/c/src/lib/libbsp/sh/gensh2/startup/hw_init.c +++ b/c/src/lib/libbsp/sh/gensh2/startup/hw_init.c @@ -3,8 +3,14 @@ * Pin and memory assignments assume * target is Hitachi SH7045F EVB ("lcevb") * + * Provides two initialization routines: + * A. 'void early_hw_init(void)' for 'start.S' + * sets up hw needed for early RTEMS boot, and + * B. 'void bsp_hw_init(void)' for 'bspstart.c' + * sets up hardware used by this BSP. + * * Author: John M. Mills (jmills@tga.com) - * COPYRIGHT(c) 1999, TGA Technologies, Inc + * COPYRIGHT(c) 2000, TGA Technologies, Inc * Norcross, GA 30071 U.S.A * * This program is distributed in the hope that it will be useful, @@ -40,74 +46,72 @@ #include <rtems/score/sh_io.h> #include <rtems/score/iosh7045.h> -/* exported entry */ -extern void hw_initialize (void); +/* exported entries */ +extern void bsp_hw_init (void); +extern void early_hw_init (void); -/* STANDALONE_EVB sets up bus, DRAM, PFC, and SCI0 */ -/* no STANDALONE_EVB accepts defaults, adds RESET, SCI1, WDT */ +/* called from 'start.S' on "#ifdef START_HW_INIT" */ +void early_hw_init (void) +{ +#ifdef STANDALONE_EVB + /* STANDALONE_EVB minimally sets up bus and DRAM here */ + /* no STANDALONE_EVB accepts defaults from debug monitor */ + + /* FIXME: replace 'magic numbers' with logical names */ + + write16(0x2020, BSC_BCR1); /* Bus width access - 32-bit on CS1 */ + write16(0xF3DD, BSC_BCR2); /* Idle cycles CS3-CS0 - 0 idle cycles*/ + write16(0xFF3F, BSC_WCR1); /* Waits for CS3-CS0 - 3 waits on CS1 */ + write16(0x000F, BSC_WCR2); /* Waits for DRAM/DMA access - default */ + write16(0x0000, BSC_DCR); /* DRAM control - default */ + write16(0x0000, BSC_RTCSR); /* DRAM refresh - default */ + write16(0x0000, BSC_RTCNT); /* DRAM refresh counter - default*/ + write16(0x0000, BSC_RTCOR); /* DRAM refresh compare match - default */ +#endif -/***************************************************/ -/* Inline function to access CPU features */ -/* from C. This makes use of GNU extensions. */ -/***************************************************/ + /* add early-init functions here */ -__inline__ void set_interrupt_mask(unsigned char mask) -{ - asm("mov.l r0,@-r15"); - asm("mov %0,r0"::"r"(mask)); - asm("and #0xF,r0"); - asm("rotl r0"); - asm("rotl r0"); - asm("rotl r0"); - asm("rotl r0"); - asm("ldc r0,sr"); - asm("mov.l @r15+,r0"); -} +}; -void hw_initialize (void) +/* to be called from 'bspstart.c' */ +void bsp_hw_init (void) { - int a; - unsigned8 temp8; - unsigned16 temp16; + int a; + unsigned8 temp8; + unsigned16 temp16; #ifdef STANDALONE_EVB - /* FIXME: replace 'magic numbers' */ - - write16(0x2020, BSC_BCR1); /* Bus width access - 32-bit on CS1 */ - write16(0xF3DD, BSC_BCR2); /* Idle cycles CS3-CS0 - 0 idle cycles*/ - write16(0xFF3F, BSC_WCR1); /* Waits for CS3-CS0 - 3 waits on CS1 */ - write16(0x000F, BSC_WCR2); /* Waits for DRAM/DMA access - default */ - write16(0x0000, BSC_DCR); /* DRAM control - default */ - write16(0x0000, BSC_RTCSR); /* DRAM refresh - default */ - write16(0x0000, BSC_RTCNT); /* DRAM refresh counter - default*/ - write16(0x0000, BSC_RTCOR); /* DRAM refresh compare match - default */ + /* STANDALONE_EVB: sets up PFC */ + /* no STANDALONE_EVB: accepts defaults, adds RESET */ + + /* FIXME: replace 'magic numbers' */ - write16(0x5000, PFC_PACRH); /* Pin function controller - WRHH, WRHL */ - write16(0x1550, PFC_PACRL1); /* Pin fun. controller - WRH,WRL,RD,CS1 */ - write16(0x0000, PFC_PBCR1); /* Pin function controller - default */ - write16(0x2005, PFC_PBCR2); /* Pin function controller - A18,A17,A16 */ - write16(0xFFFF, PFC_PCCR); /* Pin function controller - A15-A0 */ - write16(0x5555, PFC_PDCRH1; /* Pin function controller - D31-D24 */ - write16(0x5555, PFC_PDCRH2); /* Pin function controller - D23-D16 */ - write16(0xFFFF, PFC_PDCRL); /* Pin function controller - D15-D0 */ - write16(0x0000, PFC_IFCR); /* Pin function controller - default */ - write16(0x0005, PFC_PACRL2); /* Pin function controller - Tx0, Rx0 */ - - write16(0x00, PFC_PACRL2); /* default disconnects all I/O */ - /* pins; connected by DEVICE_open() */ + write16(0x5000, PFC_PACRH); /* Pin function controller - WRHH, WRHL */ + write16(0x1550, PFC_PACRL1); /* Pin fun. controller - WRH,WRL,RD,CS1 */ + write16(0x0000, PFC_PBCR1); /* Pin function controller - default */ + write16(0x2005, PFC_PBCR2); /* Pin fcn. controller - A18,A17,A16 */ + write16(0xFFFF, PFC_PCCR); /* Pin function controller - A15-A0 */ + write16(0x5555, PFC_PDCRH1); /* Pin function controller - D31-D24 */ + write16(0x5555, PFC_PDCRH2); /* Pin function controller - D23-D16 */ + write16(0xFFFF, PFC_PDCRL); /* Pin function controller - D15-D0 */ + write16(0x0000, PFC_IFCR); /* Pin function controller - default */ + write16(0x0000, PFC_PACRL2); /* default disconnects all I/O pins;*/ + /* [re-connected by DEVICE_open()] */ #endif - /* default hardware setup for SH7045F EVB */ + /* default hardware setup for SH7045F EVB */ - /* PFC: General I/O except pin 13 (reset): */ - temp16 = read16(PFC_PECR1) | 0x0800; - write16(temp16, PFC_PECR1); + /* PFC: General I/O except pin 13 (reset): */ + temp16 = read16(PFC_PECR1); + temp16 |= 0x0800; + write16(temp16, PFC_PECR1); - /* All I/O lines bits 7-0: */ - write16(0x00, PFC_PECR2); + /* All I/O lines bits 7-0: */ + write16(0x00, PFC_PECR2); - /* P5 (LED) out, all other pins in: */ - temp16 = read16(PFC_PEIOR) | 0x0020; - write16(temp16, PFC_PEIOR); + /* P5 (LED) out, all other pins in: */ + temp16 = read16(PFC_PEIOR); + temp16 |= 0x0020; + write16(temp16, PFC_PEIOR); } |