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Diffstat (limited to 'c/src/lib/libbsp/powerpc/tqm8xx/startup/cpuinit.c')
-rw-r--r--c/src/lib/libbsp/powerpc/tqm8xx/startup/cpuinit.c26
1 files changed, 19 insertions, 7 deletions
diff --git a/c/src/lib/libbsp/powerpc/tqm8xx/startup/cpuinit.c b/c/src/lib/libbsp/powerpc/tqm8xx/startup/cpuinit.c
index 23311ee2aa..5b3ed03cda 100644
--- a/c/src/lib/libbsp/powerpc/tqm8xx/startup/cpuinit.c
+++ b/c/src/lib/libbsp/powerpc/tqm8xx/startup/cpuinit.c
@@ -22,6 +22,7 @@
void _InitTQM8xx (void)
{
register uint32_t r1;
+ uint32_t msr;
/*
* Initialize the Instruction Support Control Register (ICTRL) to a
@@ -122,12 +123,23 @@ void _InitTQM8xx (void)
r1 = 0x00000000;
_mtspr( M8xx_TBU_WR, r1 );
_mtspr( M8xx_TBL_WR, r1 );
-}
-/*
- * further initialization (called from bsp_start)
- */
-void cpu_init(void)
-{
- /* mmu initialization */
+ /* init the MMU */
mmu_init();
+
+ /*
+ * override setting from mmu_init:
+ * make sure the cache is ON(!!!) when the MMU is disabled
+ * otherwise the exception code will break
+ */
+ r1 = 0x04000e00;
+ _mtspr( M8xx_MD_CTR, r1 );
+
+ /* Read MSR */
+ msr = ppc_machine_state_register();
+
+ /* Enable data and instruction MMU in MSR */
+ msr |= MSR_DR | MSR_IR;
+
+ /* Update MSR */
+ ppc_set_machine_state_register( msr);
}