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-rw-r--r--c/src/lib/libbsp/powerpc/haleakala/ChangeLog7
-rw-r--r--c/src/lib/libbsp/powerpc/haleakala/Makefile.am30
-rw-r--r--c/src/lib/libbsp/powerpc/haleakala/irq/irq.c85
-rw-r--r--c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c21
-rw-r--r--c/src/lib/libbsp/powerpc/haleakala/startup/linkcmds2
5 files changed, 87 insertions, 58 deletions
diff --git a/c/src/lib/libbsp/powerpc/haleakala/ChangeLog b/c/src/lib/libbsp/powerpc/haleakala/ChangeLog
index 91a7b1bad8..a2191707ce 100644
--- a/c/src/lib/libbsp/powerpc/haleakala/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/haleakala/ChangeLog
@@ -1,5 +1,12 @@
2008-07-14 Thomas Doerfler <thomas.doerfler@embedded-brains.de>
+ * irq/irq.c: adapted DCR access syntax
+
+ * startup/linkcmds, startup/bspstartup.c, Makefile.am:
+ adapted to exception support code
+
+2008-07-14 Thomas Doerfler <thomas.doerfler@embedded-brains.de>
+
* README, bsp_specs, INSTALL, bsp_specs.dl, configure.ac,
* Makefile.am, preinstall.am, dlentry/dlentry.S,
* include/bsp.h, include/coverhd.h, include/tm27.h
diff --git a/c/src/lib/libbsp/powerpc/haleakala/Makefile.am b/c/src/lib/libbsp/powerpc/haleakala/Makefile.am
index be74e8d2a5..3af080be86 100644
--- a/c/src/lib/libbsp/powerpc/haleakala/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/haleakala/Makefile.am
@@ -56,20 +56,20 @@ include_bsp_HEADERS += irq/irq.h \
../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h \
../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h
-
+
noinst_PROGRAMS += irq.rel
irq_rel_SOURCES = irq/irq_init.c irq/irq.c
irq_rel_CPPFLAGS = $(AM_CPPFLAGS)
irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
-if HAS_NETWORKING
-network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
-noinst_PROGRAMS += network.rel
-network_rel_SOURCES = network/network.c
-network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS)
-network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
-endif
+## if HAS_NETWORKING
+## network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
+## noinst_PROGRAMS += network.rel
+## network_rel_SOURCES = network/network.c
+## network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS)
+## network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+## endif
noinst_LIBRARIES = libbsp.a
@@ -77,17 +77,17 @@ libbsp_a_SOURCES =
libbsp_a_LIBADD = startup.rel dlentry.rel console.rel irq.rel
-if HAS_NETWORKING
-libbsp_a_LIBADD += network.rel
-endif
+## if HAS_NETWORKING
+## libbsp_a_LIBADD += network.rel
+## endif
libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
- ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
- ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
+ ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
+ ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
- ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
+ ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/ppc403/clock.rel \
- ../../../libcpu/@RTEMS_CPU@/ppc403/timer.rel
+ ../../../libcpu/@RTEMS_CPU@/ppc403/timer.rel
EXTRA_DIST += times
diff --git a/c/src/lib/libbsp/powerpc/haleakala/irq/irq.c b/c/src/lib/libbsp/powerpc/haleakala/irq/irq.c
index dd20e93b90..e09adb55f0 100644
--- a/c/src/lib/libbsp/powerpc/haleakala/irq/irq.c
+++ b/c/src/lib/libbsp/powerpc/haleakala/irq/irq.c
@@ -69,9 +69,12 @@ static inline int IsUICIRQ(const rtems_irq_number irqLine)
static void WriteIState()
/* Write the gEnabledInts state masked by gIntInhibited to the hardware */
{
- mtdcr(UIC0_ER, gEnabledInts[0] & ~gIntInhibited[0]);
- mtdcr(UIC1_ER, gEnabledInts[1] & ~gIntInhibited[1]);
- mtdcr(UIC2_ER, gEnabledInts[2] & ~gIntInhibited[2]);
+ PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_ER,
+ gEnabledInts[0] & ~gIntInhibited[0]);
+ PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_ER,
+ gEnabledInts[1] & ~gIntInhibited[1]);
+ PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_ER,
+ gEnabledInts[2] & ~gIntInhibited[2]);
}
void
@@ -112,26 +115,44 @@ BSP_setup_the_pic(rtems_irq_global_settings* config)
for (i=0; i<kUICWords; i++)
gIntInhibited[i] = 0;
- mtdcr (UIC2_ER, 0x00000000); /* disable all interrupts */
- mtdcr (UIC2_CR, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (UIC2_PR, 0xf7ffffff); /* Set Interrupt Polarities */
- mtdcr (UIC2_TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
- mtdcr (UIC2_VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (UIC2_SR, 0xffffffff); /* clear all interrupts */
-
- mtdcr (UIC1_ER, 0x00000000); /* disable all interrupts */
- mtdcr (UIC1_CR, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (UIC1_PR, 0xfffac785); /* Set Interrupt Polarities */
- mtdcr (UIC1_TR, 0x001d0040); /* Set Interrupt Trigger Levels */
- mtdcr (UIC1_VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (UIC1_SR, 0xffffffff); /* clear all interrupts */
-
- mtdcr (UIC0_ER, 0x0000000a); /* Disable all interrupts except cascade UIC0 and UIC1 */
- mtdcr (UIC0_CR, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (UIC0_PR, 0xffbfefef); /* Set Interrupt Polarities */
- mtdcr (UIC0_TR, 0x00007000); /* Set Interrupt Trigger Levels */
- mtdcr (UIC0_VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (UIC0_SR, 0xffffffff); /* clear all interrupts */
+ /* disable all interrupts */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_ER, 0x00000000);
+ /* Set Critical / Non Critical interrupts */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_CR, 0x00000000);
+ /* Set Interrupt Polarities */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_PR, 0xf7ffffff);
+ /* Set Interrupt Trigger Levels */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_TR, 0x01e1fff8);
+ /* Set Vect base=0,INT31 Highest priority */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_VR, 0x00000001);
+ /* clear all interrupts */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC2_SR, 0xffffffff);
+
+ /* disable all interrupts */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_ER, 0x00000000);
+ /* Set Critical / Non Critical interrupts */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_CR, 0x00000000);
+ /* Set Interrupt Polarities */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_PR, 0xfffac785);
+ /* Set Interrupt Trigger Levels */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_TR, 0x001d0040);
+ /* Set Vect base=0,INT31 Highest priority */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_VR, 0x00000001);
+ /* clear all interrupts */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC1_SR, 0xffffffff);
+
+ /* Disable all interrupts except cascade UIC0 and UIC1 */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_ER, 0x0000000a);
+ /* Set Critical / Non Critical interrupts */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_CR, 0x00000000);
+ /* Set Interrupt Polarities */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_PR, 0xffbfefef);
+ /* Set Interrupt Trigger Levels */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_TR, 0x00007000);
+ /* Set Vect base=0,INT31 Highest priority */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_VR, 0x00000001);
+ /* clear all interrupts */
+ PPC_SET_DEVICE_CONTROL_REGISTER (UIC0_SR, 0xffffffff);
return 1;
}
@@ -153,9 +174,9 @@ C_dispatch_irq_handler( struct _BSP_Exception_frame* frame, unsigned int excNum
/* Fetch the masked flags that tell us what external ints are active.
Likely to be only one, but we need to handle more than one,
OR the flags into gIntInhibited */
- active[0] = mfdcr(UIC0_MSR);
- active[1] = mfdcr(UIC1_MSR);
- active[2] = mfdcr(UIC2_MSR);
+ active[0] = PPC_DEVICE_CONTROL_REGISTER(UIC0_MSR);
+ active[1] = PPC_DEVICE_CONTROL_REGISTER(UIC1_MSR);
+ active[2] = PPC_DEVICE_CONTROL_REGISTER(UIC2_MSR);
gIntInhibited[0] |= active[0];
gIntInhibited[1] |= active[1];
gIntInhibited[2] |= active[2];
@@ -180,9 +201,15 @@ C_dispatch_irq_handler( struct _BSP_Exception_frame* frame, unsigned int excNum
/* Write a 1-bit to the appropriate status register to clear it */
bmask = 0x80000000 >> bit;
switch (index) {
- case 0: mtdcr(UIC0_SR, bmask); break;
- case 1: mtdcr(UIC1_SR, bmask); break;
- case 2: mtdcr(UIC2_SR, bmask); break;
+ case 0:
+ PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_SR, bmask);
+ break;
+ case 1:
+ PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_SR, bmask);
+ break;
+ case 2:
+ PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_SR, bmask);
+ break;
}
/* Clear in the active record and gIntInhibited */
diff --git a/c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c b/c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c
index 2bf2f18c1b..8fc2cea2c5 100644
--- a/c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c
@@ -68,14 +68,11 @@
#include <bsp/irq.h>
#include <rtems/bspIo.h>
#include <libcpu/cpuIdent.h>
-#include <libcpu/spr.h>
#include <rtems/powerpc/powerpc.h>
+#include <bsp/ppc_exc_bspsupp.h>
#include <ppc4xx/ppc405gp.h>
#include <ppc4xx/ppc405ex.h>
-SPR_RW(SPRG0)
-SPR_RW(SPRG1)
-
#include <stdio.h>
/*
@@ -232,8 +229,8 @@ BSP_output_char_function_type BSP_output_char = DirectUARTWrite;
void bsp_start( void )
{
- extern unsigned long *intrStackPtr;
- register unsigned char* intrStack;
+ LINKER_SYMBOL(intrStack_start);
+ LINKER_SYMBOL(intrStack_size);
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
@@ -262,16 +259,12 @@ void bsp_start( void )
bsp_timer_least_valid = 3;
/*
- * Initialize some SPRG registers related to irq handling
- */
-
- intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
- _write_SPRG1((unsigned int)intrStack);
- /* signal them that we have fixed PR288 - eventually, this should go away */
- /*
* Initialize default raw exception handlers.
*/
- initialize_exceptions();
+ ppc_exc_initialize(
+ PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
+ (uint32_t) intrStack_start,
+ (uint32_t) intrStack_size);
/*
* Install our own set of exception vectors
diff --git a/c/src/lib/libbsp/powerpc/haleakala/startup/linkcmds b/c/src/lib/libbsp/powerpc/haleakala/startup/linkcmds
index abd15dab60..65b84cbfb4 100644
--- a/c/src/lib/libbsp/powerpc/haleakala/startup/linkcmds
+++ b/c/src/lib/libbsp/powerpc/haleakala/startup/linkcmds
@@ -229,6 +229,8 @@ SECTIONS
. += kIntrStackSize;
intrStack = .;
PROVIDE(intrStackPtr = intrStack);
+ PROVIDE(intrStack_start = IntrStack_start);
+ PROVIDE(intrStack_size = kIntrStackSize);
/* Main stack: align to a cache-line boundary */
stack.start = ALIGN(0x20);
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-29 11:50:20 +0000