diff options
Diffstat (limited to 'c/src/lib/libbsp/powerpc/eth_comm/startup')
4 files changed, 101 insertions, 11 deletions
diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c index be35333ea5..c5c1c37d76 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c @@ -18,7 +18,6 @@ */ #include <bsp.h> -#include <mpc860.h> #include <rtems/libio.h> #include <libcsupport.h> @@ -115,6 +114,10 @@ void bsp_start(void) extern int _end; rtems_unsigned32 heap_start; rtems_unsigned32 ws_start; + + cpu_init(); + mmu_init(); + /* * Allocate the memory for the RTEMS Work Space. This can come from * a variety of places: hard coded address, malloc'ed from outside @@ -166,16 +169,14 @@ void bsp_start(void) * transciever that is used for 10/100 Mbps ethernet now, so that * we can attempt to read it later in rtems_enet_driver_attach() */ - m860.fec.mii_speed = 0x0a; - m860.fec.mii_data = 0x680a0000; - + m8xx.fec.mii_speed = 0x0a; + m8xx.fec.mii_data = 0x680a0000; - m860.scc2.sccm=0; - m860.scc2p.rbase=0; - m860.scc2p.tbase=0; - M860ExecuteRISC(M860_CR_OP_STOP_TX | M860_CR_CHAN_SCC2); - mmu_init(); + m8xx.scc2.sccm=0; + m8xx.scc2p.rbase=0; + m8xx.scc2p.tbase=0; + m8xx_cp_execute_cmd( M8xx_CR_OP_STOP_TX | M8xx_CR_CHAN_SCC2 ); } diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/cpuinit.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/cpuinit.c new file mode 100644 index 0000000000..6049f37878 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/cpuinit.c @@ -0,0 +1,44 @@ +/* + * cpuinit.c - this file contains functions for initializing the CPU + * + * Written by Jay Monkman (jmonkman@frasca.com) + * + * $Id$ + */ + +#include <bsp.h> + +/* Macros for handling all the MMU SPRs */ +#define PUT_IC_CST(r) __asm__ volatile ("mtspr 0x230,%0\n" ::"r"(r)) +#define GET_IC_CST(r) __asm__ volatile ("mfspr %0,0x230\n" :"=r"(r)) +#define PUT_DC_CST(r) __asm__ volatile ("mtspr 0x238,%0\n" ::"r"(r)) +#define GET_DC_CST(r) __asm__ volatile ("mfspr %0,0x238\n" :"=r"(r)) + +void cpu_init(void) +{ + register unsigned long t1, t2; + + /* Let's clear MSR[IR] and MSR[DR] */ + t2 = PPC_MSR_IR | PPC_MSR_DR; + __asm__ volatile ( + "mfmsr %0\n" + "andc %0, %0, %1\n" + "mtmsr %0\n" :"=r"(t1), "=r"(t2): + "1"(t2)); + + t1 = M8xx_CACHE_CMD_UNLOCK; + /* PUT_DC_CST(t1); */ + PUT_IC_CST(t1); + + t1 = M8xx_CACHE_CMD_INVALIDATE; + /* PUT_DC_CST(t1); */ + PUT_IC_CST(t1); + + t1 = M8xx_CACHE_CMD_ENABLE; + PUT_IC_CST(t1); + + t1 = M8xx_CACHE_CMD_SFWT; + /* PUT_DC_CST(t1); */ + t1 = M8xx_CACHE_CMD_ENABLE; + /* PUT_DC_CST(t1);*/ +} diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/linkcmds b/c/src/lib/libbsp/powerpc/eth_comm/startup/linkcmds index d2a072876f..a565798488 100644 --- a/c/src/lib/libbsp/powerpc/eth_comm/startup/linkcmds +++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/linkcmds @@ -128,8 +128,8 @@ SECTIONS dpram : { - m860 = .; - _m860 = .; + m8xx = .; + _m8xx = .; . += (8 * 1024); } >dpram diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c new file mode 100644 index 0000000000..2153ccccab --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/mmutlbtab.c @@ -0,0 +1,45 @@ +/* + * mmutlbtab.c + * + * This file defines the MMU_TLB_table for the eth_comm board. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + */ + +#include <bsp.h> +#include <mpc8xx/mmu.h> + +/* + * This MMU_TLB_table is used to statically initialize the Table Lookaside + * Buffers in the MMU of the MPC860 processor. + * + * We initialize the entries in both the instruction and data TLBs + * with the same values - a few bits relevant to the data TLB are unused + * in the instruction TLB. + * + * An Effective Page Number (EPN), Tablewalk Control Register (TWC) and + * Real Page Number (RPN) value are supplied in the table for each TLB entry. + * + * The instruction and data TLBs each can hold 32 entries, so _TLB_Table must + * not have more than 32 lines in it! + * + * We set up the virtual memory map so that virtual address of a + * location is equal to its real address. + */ +MMU_TLB_table_t MMU_TLB_table[] = { + /* + * DRAM: CS1, Start address 0x00000000, 8M, + * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, + * R/W,X for supervisor, no ASID comparison, not cache-inhibited. + * EPN TWC RPN + */ + { 0x00000200, 0x0D, 0x000001FD } /* DRAM - PS=PS=8M */ +}; + +/* + * MMU_N_TLB_Table_Entries is defined here because the size of the + * MMU_TLB_table is only known in this file. + */ +int MMU_N_TLB_Table_Entries = ( sizeof(MMU_TLB_table) / sizeof(MMU_TLB_table[0]) ); |