diff options
Diffstat (limited to 'c/src/lib/libbsp/mips/genmongoosev/start/mg5.h')
| -rw-r--r-- | c/src/lib/libbsp/mips/genmongoosev/start/mg5.h | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/c/src/lib/libbsp/mips/genmongoosev/start/mg5.h b/c/src/lib/libbsp/mips/genmongoosev/start/mg5.h index 12776c8fc3..8d54133d64 100644 --- a/c/src/lib/libbsp/mips/genmongoosev/start/mg5.h +++ b/c/src/lib/libbsp/mips/genmongoosev/start/mg5.h @@ -9,8 +9,6 @@ */ #define PMON_ADDRESS 0xbfc00000 - - /* ** Mongoose V Peripheral Function Registers */ @@ -65,7 +63,6 @@ #define MG5_MAVN_RANGE_4_REG 0xfffe01d0 /* Range 4 */ #define MG5_MAVN_RANGE_5_REG 0xfffe01d4 /* Range 5 */ - /* ** Uart Specific Peripheral Function Registers */ @@ -76,7 +73,6 @@ #define MG5_UART_1_TX_REG 0xfffe01f8 #define MG5_UART_1_BAUD_REG 0xfffe01fc - /* ** Section 2: Bit definitions ** @@ -106,7 +102,6 @@ #define UART_CTSN_TEST_BIT 0x00000004 #define UART_RESET_BIT 0x00000002 - /* ** Interrupt Status/Cause/Mask register bits - from 31 to 0 */ @@ -138,7 +133,6 @@ #define EXTERN_INT_1_BIT 0x00000002 #define EXTERN_INT_0_BIT 0x00000001 - /* ** MAVN Range Bits */ @@ -152,7 +146,6 @@ #define MAVN_GLOBAL_WRITE_BIT 0x00000200 - #define MAVN_RANGE_0_READ_BIT 0x00000400 #define MAVN_RANGE_1_READ_BIT 0x00000800 #define MAVN_RANGE_2_READ_BIT 0x00001000 @@ -239,11 +232,6 @@ #define MAVN_START_ADDR_MASK 0xFFFFFE00 #define MAVN_PS_CODE_MASK 0x0000001F - - - - - /* lr33000.h - defines for LSI Logic LR33000 */ /* Define counter/timer register addresses */ @@ -268,11 +256,6 @@ /* lr33000.h */ - - - - - #define _LR33300_ #define M_SRAM 0xfffe0100 /* SRAM config reg */ @@ -340,12 +323,6 @@ /* _LR33300_ */ - - - - - - #define _ERNIE_CORE_ #define M_BIU 0xfffe0130 @@ -396,7 +373,6 @@ /* _ERNIE_CORE_ */ - /* Definitions for cache sizes */ #define LR33300_IC_SIZE 0x1000 /* 33300 Inst cache = 4Kbytes */ |