diff options
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libbsp/m68k/mvme167/startup/page_table.c | 50 |
1 files changed, 34 insertions, 16 deletions
diff --git a/c/src/lib/libbsp/m68k/mvme167/startup/page_table.c b/c/src/lib/libbsp/m68k/mvme167/startup/page_table.c index ebbcc9739d..e6e5f1571a 100644 --- a/c/src/lib/libbsp/m68k/mvme167/startup/page_table.c +++ b/c/src/lib/libbsp/m68k/mvme167/startup/page_table.c @@ -32,11 +32,13 @@ * physical range 0x0 to 0x7FFFFFFF. We rely on the hardware to signal bus * errors if we address non-existent memory within this range. Our two * MVME167s are configured to exist at physical addresses 0x00800000 to - * 0x00BFFFFF and 0x00C00000 to 0x00FFFFFF respectively. We map the space - * from 0x0 to 0x7FFFFFFF as copyback, unless jumper J1-5 is removed, in - * which case we map as writethrough. If jumper J1-7 is removed, the data - * cache is NOT enabled. If jumper J1-6 is removed, the instruction cache - * is not enabled. + * 0x00BFFFFF and 0x00C00000 to 0x00FFFFFF respectively. If jumper J1-4 is + * installed, memeory and cache control can be done by providing parameters + * in NVRAM. See the README for details. If J1-4 is removed, behaviour + * defaults to the following. We map the space from 0x0 to 0x7FFFFFFF as + * copyback, unless jumper J1-5 is removed, in which case we map as writethrough. + * If jumper J1-7 is removed, the data cache is NOT enabled. If jumper J1-6 + * is removed, the instruction cache is not enabled. * * Copyright (c) 1998, National Research Council of Canada * @@ -84,23 +86,39 @@ void page_table_init( */ dtt0 = 0x007FC020; - cacr = 0x80008000; /* Data and instruction cache on */ + cacr = 0x00000000; /* Data and instruction cache off */ /* Read the J1 header */ j1 = (unsigned char)(lcsr->vector_base & 0xFF); + + if ( !(j1 & 0x10) ) { + /* Jumper J1-4 is on, configure from NVRAM */ + + if ( nvram->dcache_enable ) + cacr |= 0x80000000; + + if ( nvram->icache_enable ) + cacr |= 0x00008000; + + if ( nvram->cache_mode ) + dtt0 = ((nvram->cache_mode & 0x0003) << 5) | (dtt0 & 0xFFFFFF9F); + } + else { + /* Configure according to other jumper settings */ - if ( j1 & 0x80 ) - /* Jumper J1-7 if off, disable data caching */ - cacr &= 0x7FFFFFFF; + if ( j1 & 0x80 ) + /* Jumper J1-7 if off, disable data caching */ + cacr &= 0x7FFFFFFF; - if ( j1 & 0x40 ) - /* Jumper J1-6 if off, disable instruction caching */ - cacr &= 0xFFFF7FFF; + if ( j1 & 0x40 ) + /* Jumper J1-6 if off, disable instruction caching */ + cacr &= 0xFFFF7FFF; - if ( j1 & 0x20 ) - /* Jumper J1-5 is off, enable writethrough caching */ - dtt0 &= 0xFFFFFF9F; - + if ( j1 & 0x20 ) + /* Jumper J1-5 is off, enable writethrough caching */ + dtt0 &= 0xFFFFFF9F; + } + /* do it ! */ asm volatile("movec %0, %%tc /* turn off paged address translation */ movec %0, %%cacr /* disable both caches */ |