diff options
Diffstat (limited to 'c/src/lib/libbsp/m68k/mvme162/startup')
| -rw-r--r-- | c/src/lib/libbsp/m68k/mvme162/startup/bspclean.c | 55 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/mvme162/startup/bspstart.c | 256 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/mvme162/startup/linkcmds | 50 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/mvme162/startup/page_table.c | 201 |
4 files changed, 562 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/m68k/mvme162/startup/bspclean.c b/c/src/lib/libbsp/m68k/mvme162/startup/bspclean.c new file mode 100644 index 0000000000..8c8497aaf5 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mvme162/startup/bspclean.c @@ -0,0 +1,55 @@ +/* + * This routine returns control to 162Bug. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * + * Modifications of respective RTEMS file: COPYRIGHT (c) 1994. + * EISCAT Scientific Association. M.Savitski + * + * This material is a part of the MVME162 Board Support Package + * for the RTEMS executive. Its licensing policies are those of the + * RTEMS above. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> +#include <z8036.h> + +void bsp_return_to_monitor_trap() +{ + extern void start( void ); + + page_table_teardown(); + + lcsr->intr_ena = 0; /* disable interrupts */ + m68k_set_vbr(0xFFE00000); /* restore 162Bug vectors */ + asm volatile( "trap #15" ); /* trap to 162Bug */ + asm volatile( ".short 0x63" ); /* return to 162Bug (.RETURN) */ + /* restart program */ + /* + * This does not work on the 162.... + */ +#if 0 + { register volatile void *start_addr; + + start_addr = start; + + asm volatile ( "jmp %0@" : "=a" (start_addr) : "0" (start_addr) ); + } +#endif +} + +void bsp_cleanup( void ) +{ + M68Kvec[ 45 ] = bsp_return_to_monitor_trap; /* install handler */ + asm volatile( "trap #13" ); /* insures SUPV mode */ +} diff --git a/c/src/lib/libbsp/m68k/mvme162/startup/bspstart.c b/c/src/lib/libbsp/m68k/mvme162/startup/bspstart.c new file mode 100644 index 0000000000..7cbfd6f83b --- /dev/null +++ b/c/src/lib/libbsp/m68k/mvme162/startup/bspstart.c @@ -0,0 +1,256 @@ +/* bsp_start() + * + * This routine starts the application. It includes application, + * board, and monitor specific initialization and configuration. + * The generic CPU dependent initialization has been performed + * before this routine is invoked. + * + * INPUT: NONE + * + * OUTPUT: NONE + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * Modifications of respective RTEMS file: COPYRIGHT (c) 1994. + * EISCAT Scientific Association. M.Savitski + * + * This material is a part of the MVME162 Board Support Package + * for the RTEMS executive. Its licensing policies are those of the + * RTEMS above. + * + * $Id$ + */ + +#include <bsp.h> +#include <rtems/libio.h> + +#include <libcsupport.h> + +#include <string.h> +#include <fcntl.h> + +#ifdef STACK_CHECKER_ON +#include <stackchk.h> +#endif + +/* + * The original table from the application and our copy of it with + * some changes. + */ + +extern rtems_configuration_table Configuration; +rtems_configuration_table BSP_Configuration; + +rtems_cpu_table Cpu_table; + +char *rtems_progname; + +/* Initialize whatever libc we are using + * called from postdriver hook + */ + +void bsp_libc_init() +{ + extern int end; + rtems_unsigned32 heap_start; + + heap_start = (rtems_unsigned32) &end; + if (heap_start & (CPU_ALIGNMENT-1)) + heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); + + RTEMS_Malloc_Initialize((void *) heap_start, 64 * 1024, 0); + + /* + * Init the RTEMS libio facility to provide UNIX-like system + * calls for use by newlib (ie: provide __open, __close, etc) + * Uses malloc() to get area for the iops, so must be after malloc init + */ + + rtems_libio_init(); + + /* + * Set up for the libc handling. + */ + + if (BSP_Configuration.ticks_per_timeslice > 0) + libc_init(1); /* reentrant if possible */ + else + libc_init(0); /* non-reentrant */ +} + +/* + * Function: bsp_pretasking_hook + * Created: 95/03/10 + * + * Description: + * BSP pretasking hook. Called just before drivers are initialized. + * Used to setup libc and install any BSP extensions. + * + * NOTES: + * Must not use libc (to do io) from here, since drivers are + * not yet initialized. + * + */ + +void +bsp_pretasking_hook(void) +{ + bsp_libc_init(); + +#ifdef STACK_CHECKER_ON + /* + * Initialize the stack bounds checker + * We can either turn it on here or from the app. + */ + + Stack_check_Initialize(); +#endif + +#ifdef RTEMS_DEBUG + rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); +#endif +} + + +/* + * After drivers are setup, register some "filenames" + * and open stdin, stdout, stderr files + * + * Newlib will automatically associate the files with these + * (it hardcodes the numbers) + */ + +void +bsp_postdriver_hook(void) +{ + int stdin_fd, stdout_fd, stderr_fd; + int error_code; + + error_code = 'S' << 24 | 'T' << 16; + + if ((stdin_fd = __open("/dev/console", O_RDONLY, 0)) == -1) + rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); + + if ((stdout_fd = __open("/dev/console", O_WRONLY, 0)) == -1) + rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); + + if ((stderr_fd = __open("/dev/console", O_WRONLY, 0)) == -1) + rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); + + if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) + rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); +} + +int main( + int argc, + char **argv, + char **environp +) +{ + m68k_isr_entry *monitors_vector_table; + int index; + + if ((argc > 0) && argv && argv[0]) + rtems_progname = argv[0]; + else + rtems_progname = "RTEMS"; + + /* + * 162Bug Vectors are at 0xFFE00000 + */ + + monitors_vector_table = (m68k_isr_entry *)0xFFE00000; + + m68k_set_vbr( monitors_vector_table ); + + for ( index=2 ; index<=255 ; index++ ) + M68Kvec[ index ] = monitors_vector_table[ 32 ]; + + M68Kvec[ 2 ] = monitors_vector_table[ 2 ]; /* bus error vector */ + M68Kvec[ 4 ] = monitors_vector_table[ 4 ]; /* breakpoints vector */ + M68Kvec[ 9 ] = monitors_vector_table[ 9 ]; /* trace vector */ + M68Kvec[ 47 ] = monitors_vector_table[ 47 ]; /* system call vector */ + + m68k_set_vbr( &M68Kvec ); + + /* + * You may wish to make the VME arbitration round-robin here, currently + * we leave it as it is. + */ + + /* set the Interrupt Base Vectors */ + + lcsr->vector_base = (VBR0 << 28) | (VBR1 << 24); + + page_table_init(); + + /* + * we only use a hook to get the C library initialized. + */ + + Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ + + Cpu_table.predriver_hook = NULL; + + Cpu_table.postdriver_hook = bsp_postdriver_hook; + + Cpu_table.idle_task = NULL; /* do not override system IDLE task */ + + Cpu_table.do_zero_of_workspace = TRUE; + + Cpu_table.interrupt_vector_table = (m68k_isr_entry *) &M68Kvec; + + Cpu_table.interrupt_stack_size = 4096; + + Cpu_table.extra_mpci_receive_server_stack = 0; + + /* + * Copy the table + */ + + BSP_Configuration = Configuration; + + /* + * Add 1 region for the RTEMS Malloc + */ + + BSP_Configuration.RTEMS_api_configuration->maximum_regions++; + + /* + * Add 1 extension for newlib libc + */ + +#ifdef RTEMS_NEWLIB + BSP_Configuration.maximum_extensions++; +#endif + + /* + * Add another extension if using the stack checker + */ + +#ifdef STACK_CHECKER_ON + BSP_Configuration.maximum_extensions++; +#endif + + /* + * Tell libio how many fd's we want and allow it to tweak config + */ + + rtems_libio_config(&BSP_Configuration, BSP_LIBIO_MAX_FDS); + + BSP_Configuration.work_space_start = (void *) + (RAM_END - BSP_Configuration.work_space_size); + + rtems_initialize_executive( &BSP_Configuration, &Cpu_table ); + /* does not return */ + + bsp_cleanup(); + + return 0; +} diff --git a/c/src/lib/libbsp/m68k/mvme162/startup/linkcmds b/c/src/lib/libbsp/m68k/mvme162/startup/linkcmds new file mode 100644 index 0000000000..21a844ca88 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mvme162/startup/linkcmds @@ -0,0 +1,50 @@ +/* + * This file contains directives for the GNU linker which are specific + * to the Motorola MVME162 board. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * Modifications of respective RTEMS file: COPYRIGHT (c) 1994. + * EISCAT Scientific Association. M.Savitski + * + * This material is a part of the MVME162 Board Support Package + * for the RTEMS executive. Its licensing policies are those of the + * RTEMS above. + * + * $Id$ + */ + +MEMORY + { + ram : org = 0x100000, l = 1M + } + +SECTIONS +{ + .text 0x100000 : + { + text_start = . ; + *(.text) + etext = ALIGN( 0x10 ) ; + } + .data ADDR( .text ) + SIZEOF( .text ): + { + data_start = . ; + *(.data) + edata = ALIGN( 0x10 ) ; + } + .bss ADDR( .data ) + SIZEOF( .data ): + { + bss_start = . ; + *(.bss) + *(COMMON) + end = . ; + _end = . ; + } +} diff --git a/c/src/lib/libbsp/m68k/mvme162/startup/page_table.c b/c/src/lib/libbsp/m68k/mvme162/startup/page_table.c new file mode 100644 index 0000000000..76f0d5d52b --- /dev/null +++ b/c/src/lib/libbsp/m68k/mvme162/startup/page_table.c @@ -0,0 +1,201 @@ +/* + * $Id$ + * + * This file was submitted by Eric Vaitl <vaitl@viasat.com>. + * The manipulation of the page table has a very positive impact on + * the performance of the MVME162. + * + * The following history is included verbatim from the submitter. + * + * Revision 1.8 1995/11/18 00:07:25 vaitl + * Modified asm statements to get rid of the register hard-codes. + * + * Revision 1.7 1995/10/27 21:00:32 vaitl + * Modified page table routines so application code can map + * VME space. + * + * Revision 1.6 1995/10/26 17:40:01 vaitl + * Two cache changes after reading the mvme162 users manual. + * + * 1) The users manual says that the MPU can act as a source for the + * VME2 chip, so I made the VME accessable memory copy-back instead + * of write through. I have't changed the comments yet. If this + * causes problems, I'll change it back. + * + * 2) The 162 book also says that IO space should be serialized as well as + * non-cacheable. I flipped the appropriate dttr0 and ittr0 registers. I + * don't think this is really necessary because we don't recover from any + * exceptions. If it slows down IO addresses too much, I'll change it back + * and see what happens. + * + * Revision 1.5 1995/10/25 19:32:38 vaitl + * Got it. Three problems: + * 1) Must cpusha instead of cinva. + * 2) On page descriptors the PDT field of 1 or 3 is resident. On pointer + * descriptors resident is 2 or 3. I was using 2 for everything. + * Changed it to 3 for everything. + * 3) Forgot to do a pflusha. + * + * Revision 1.4 1995/10/25 17:47:11 vaitl + * Still working on it. + * + * Revision 1.3 1995/10/25 17:16:05 vaitl + * Working on page table. Caching partially set up, but can't currently + * set tc register. + * +*/ +#include <string.h> +#include "page_table.h" + +/* All page table must fit between BASE_TABLE_ADDR and + MAX_TABLE_ADDR. */ + +#define BASE_TABLE_ADDR 0x10000 +#define MAX_TABLE_ADDR 0x20000 +#define ROOT_TABLE_SIZE 512 +#define POINTER_TABLE_SIZE 512 +#define PAGE_TABLE_SIZE 256 + +static unsigned long *root_table; +static unsigned long *next_avail; + +/* Returns a zeroed out table. */ +static unsigned long *table_alloc(int size){ + unsigned long *addr=next_avail; + if(((unsigned long)next_avail + size) > MAX_TABLE_ADDR){ + return 0; + } + bzero((void *)addr,size); + next_avail =(unsigned long *)((unsigned long)next_avail + size); + return addr; +} + + + +/* + void page_table_init(); + + This should transparently map the first 4 Meg of ram. Caching is + turned off from 0x00000000 to 0x00020000 (this region is used by + 162Bug and contains the page tables). From 0x00020000 to 0x00400000 + we are using copy back caching. DTTR0 and ITTR0 are set up to + directly translate from 0x80000000-0xffffffff with caching turned + off and serialized. Addresses between 0x400000 and 0x80000000 are + illegal. +*/ +void page_table_init(){ + + /* put everything in a known state */ + page_table_teardown(); + + root_table=table_alloc(ROOT_TABLE_SIZE); + + /* First set up TTR. + base address = 0x80000000 + address mask = 0x7f + Ignore FC2 for match. + Noncachable. + Not write protected.*/ + asm volatile ("movec %0,%%dtt0 + movec %0,%%itt0" + :: "d" (0x807fc040)); + + /* Point urp and srp at root page table. */ + asm volatile ("movec %0,%%urp + movec %0,%%srp" + :: "d" (BASE_TABLE_ADDR)); + + page_table_map((void *)0,0x20000, CACHE_NONE); + page_table_map((void *)0x20000,0x400000-0x20000,CACHE_COPYBACK); + + /* Turn on paging with a 4 k page size.*/ + asm volatile ("movec %0,%%tc" + :: "d" (0x8000)); + + /* Turn on the cache. */ + asm volatile ("movec %0,%%cacr" + :: "d" (0x80008000)); +} + +void page_table_teardown(){ + next_avail=(unsigned long *)BASE_TABLE_ADDR; + /* Turn off paging. Turn off the cache. Flush the cache. Tear down + the transparent translations. */ + asm volatile ("movec %0,%%tc + movec %0,%%cacr + cpusha %%bc + movec %0,%%dtt0 + movec %0,%%itt0 + movec %0,%%dtt1 + movec %0,%%itt1" + :: "d" (0) ); +} + +/* Identity maps addr to addr+size with caching cache_type. */ +int page_table_map(void *addr, unsigned long size, int cache_type){ + unsigned long *pointer_table; + unsigned long *page_table; + unsigned long root_index, pointer_index, page_index; + /* addr must be a multiple of 4k */ + if((unsigned long)addr & 0xfff){ + return PTM_BAD_ADDR; + } + /* size must also be a multiple of 4k */ + if(size & 0xfff){ + return PTM_BAD_SIZE; + } + /* check for valid cache type */ + if( (cache_type>CACHE_NONE) || (cache_type<CACHE_WRITE_THROUGH)){ + return PTM_BAD_CACHE; + } + + while(size){ + root_index=(unsigned long)addr; + root_index >>= 25; + root_index &= 0x7f; + + if(root_table[root_index]){ + pointer_table = + (unsigned long *) (root_table[root_index] & 0xfffffe00); + }else{ + if(!(pointer_table=table_alloc(POINTER_TABLE_SIZE))){ + return PTM_NO_TABLE_SPACE; + } + root_table[root_index]=((unsigned long)pointer_table) + 0x03; + } + + pointer_index=(unsigned long)addr; + pointer_index >>=18; + pointer_index &= 0x7f; + + if(pointer_table[pointer_index]){ + page_table = + (unsigned long *) (pointer_table[pointer_index] & + 0xffffff00); + }else{ + if(!(page_table=table_alloc(PAGE_TABLE_SIZE))){ + return PTM_NO_TABLE_SPACE; + } + pointer_table[pointer_index]= + ((unsigned long)page_table) + 0x03; + } + + page_index=(unsigned long)addr; + page_index >>=12; + page_index &= 0x3f; + + page_table[page_index] = + ((unsigned long) addr & 0xfffff000) + 0x03 + (cache_type << 5); + + size -= 4096; + addr = (void *) ((unsigned long)addr + 4096); + } + + /* Flush the ATC. Push and invalidate the cache. */ + asm volatile ("pflusha + cpusha %bc"); + + return PTM_SUCCESS; +} + + |