summaryrefslogtreecommitdiffstats
path: root/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
diff options
context:
space:
mode:
Diffstat (limited to '')
-rw-r--r--c/src/lib/libbsp/m68k/gen68360/startup/init68360.c168
1 files changed, 124 insertions, 44 deletions
diff --git a/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c b/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
index 2c22b931bd..5326cc0307 100644
--- a/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
+++ b/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
@@ -36,7 +36,7 @@ void M360ExecuteRISC(rtems_unsigned16 command)
void _Init68360 (void)
{
int i;
- extern void *_RomBase, *_RamBase;
+ unsigned long l;
m68k_isr_entry *vbr;
extern void _CopyDataClearBSSAndStart (void);
@@ -58,20 +58,20 @@ void _Init68360 (void)
* Change if you're not using an external 25 MHz oscillator.
*/
m360.clkocr = 0x8F; /* No more writes, no clock outputs */
- m360.pllcr = 0xD000; /* PLL, no writes, no prescale, */
- /* no LPSTOP slowdown, PLL X1 */
+ m360.pllcr = 0xD000; /* PLL, no writes, no prescale,
+ no LPSTOP slowdown, PLL X1 */
m360.cdvcr = 0x8000; /* No more writes, no clock division */
/*
* Step 8: Initialize system protection
* Disable watchdog FIXME: Should use watchdog!!!!
* Watchdog causes system reset
- * Fastest watchdog timeout
+ * Slowest watchdog timeout
* Enable double bus fault monitor
* Enable bus monitor external
* 128 clocks for external timeout
*/
- m360.sypcr = 0x4F;
+ m360.sypcr = 0x7F;
/*
* Step 9: Clear parameter RAM and reset communication processor module
@@ -89,60 +89,139 @@ void _Init68360 (void)
* SINTOUT not used (CPU32+ mode)
* CF1MODE=00 (CONFIG1 input)
* RAS1* double drive
- * A31-A28
+ * WE0* - WE3*
* OE* output
- * CAS2* / CAS3*
- * CAS0* / CAS1*
+ * CAS2* - CAS3*
+ * CAS0* - CAS1*
* CS7*
* AVEC*
* HARDWARE:
* Change if you are using a different memory configuration
* (static RAM, external address multiplexing, etc).
*/
- m360.pepar = 0x0100;
+ m360.pepar = 0x0180;
/*
* Step 11: Remap Chip Select 0 (CS0*), set up GMR
- * 1024 addresses per DRAM page (1M DRAM chips)
- * 60 nsec DRAM
- * 180 nsec ROM (3 wait states)
- * HARDWARE:
- * Change if you are using a different memory configuration
*/
- m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN | M360_GMR_RCYC(0) |
- M360_GMR_PGS(3) | M360_GMR_DPS_32BIT | M360_GMR_NCS |
- M360_GMR_GAMX;
- m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
- M360_MEMC_BR_V;
- m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_512KB |
+ if (&_MC68360HardwareType == &_MC68360HardwareTypeAtlasHSB) {
+ m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN |
+ M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
+ M360_GMR_DPS_32BIT | M360_GMR_DWQ |
+ M360_GMR_GAMX;
+ m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
+ M360_MEMC_BR_V;
+ m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
+ M360_MEMC_OR_8BIT;
+ }
+ else {
+ /*
+ * 1024/2048/4096 addresses per DRAM page (1M/4M/16M DRAM chips)
+ * 60 nsec DRAM
+ * 180 nsec ROM (3 wait states)
+ */
+ switch ((unsigned long)&_RamSize) {
+ default:
+ case 4*1024*1024:
+ m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN |
+ M360_GMR_RCYC(0) | M360_GMR_PGS(3) |
+ M360_GMR_DPS_32BIT | M360_GMR_NCS |
+ M360_GMR_GAMX;
+ break;
+
+ case 16*1024*1024:
+ m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN |
+ M360_GMR_RCYC(0) | M360_GMR_PGS(5) |
+ M360_GMR_DPS_32BIT | M360_GMR_NCS |
+ M360_GMR_GAMX;
+ break;
+
+ case 64*1024*1024:
+ m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN |
+ M360_GMR_RCYC(0) | M360_GMR_PGS(7) |
+ M360_GMR_DPS_32BIT | M360_GMR_NCS |
+ M360_GMR_GAMX;
+ break;
+ }
+ m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
+ M360_MEMC_BR_V;
+ m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
M360_MEMC_OR_8BIT;
+ }
/*
* Step 12: Initialize the system RAM
- * Set up option/base registers
- * 4 MB DRAM
- * 60 nsec DRAM
- * Wait for chips to power up
- * Perform 8 read cycles
- * Set all parity bits to correct state
- * Enable parity checking
- * HARDWARE:
- * Change if you are using a different memory configuration
*/
- m360.memc[1].or = M360_MEMC_OR_TCYC(0) | M360_MEMC_OR_4MB |
- M360_MEMC_OR_DRAM;
- m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
- for (i = 0; i < 50000; i++)
- continue;
- for (i = 0; i < 8; ++i)
- *((volatile unsigned long *)(unsigned long)&_RamBase);
- for (i = 0 ; i < 4*1024*1024 ; i += sizeof (unsigned long)) {
- volatile unsigned long *lp;
- lp = (unsigned long *)((unsigned char *)&_RamBase + i);
- *lp = *lp;
- }
- m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_PAREN |
+ if (&_MC68360HardwareType == &_MC68360HardwareTypeAtlasHSB) {
+ /* first bank 1MByte DRAM */
+ m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
+ M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
+ m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
+
+ /* second bank 1MByte DRAM */
+ m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
+ M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
+ m360.memc[2].br = ((unsigned long)&_RamBase + 0x100000) |
+ M360_MEMC_BR_V;
+
+ /* flash rom socket U6 on CS5 */
+ m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP |
M360_MEMC_BR_V;
+ m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
+ M360_MEMC_OR_8BIT;
+
+ /* CSRs on CS7 */
+ m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB |
+ M360_MEMC_OR_8BIT;
+ m360.memc[7].br = ATLASHSB_ESR | 0x01;
+ for (i = 0; i < 50000; i++)
+ continue;
+ for (i = 0; i < 8; ++i)
+ *((volatile unsigned long *)(unsigned long)&_RamBase);
+ }
+ else {
+ /*
+ * Set up option/base registers
+ * 4M/16M/64M DRAM
+ * 60 nsec DRAM
+ * Wait for chips to power up
+ * Perform 8 read cycles
+ * Set all parity bits to correct state
+ * Enable parity checking
+ */
+ switch ((unsigned long)&_RamSize) {
+ default:
+ case 4*1024*1024:
+ m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
+ M360_MEMC_OR_4MB |
+ M360_MEMC_OR_DRAM;
+ break;
+
+ case 16*1024*1024:
+ m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
+ M360_MEMC_OR_16MB |
+ M360_MEMC_OR_DRAM;
+ break;
+
+ case 64*1024*1024:
+ m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
+ M360_MEMC_OR_64MB |
+ M360_MEMC_OR_DRAM;
+ break;
+ }
+ m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
+ for (i = 0; i < 50000; i++)
+ continue;
+ for (i = 0; i < 8; ++i)
+ *((volatile unsigned long *)(unsigned long)&_RamBase);
+ for (l = 0 ; l < (unsigned long)&_RamSize ; l += sizeof (unsigned long)) {
+ volatile unsigned long *lp;
+ lp = (unsigned long *)((unsigned char *)&_RamBase + i);
+ *lp = *lp;
+ }
+ m360.memc[1].br = (unsigned long)&_RamBase |
+ M360_MEMC_BR_PAREN | M360_MEMC_BR_V;
+ }
/*
* Step 13: Copy the exception vector table to system RAM
@@ -155,6 +234,7 @@ void _Init68360 (void)
/*
* Step 14: More system initialization
* SDCR (Serial DMA configuration register)
+ * Disable SDMA during FREEZE
* Give SDMA priority over all interrupt handlers
* Set DMA arbiration level to 4
* CICR (CPM interrupt configuration register):
@@ -167,7 +247,7 @@ void _Init68360 (void)
* Vector base 128
* SCCs priority grouped at top of table
*/
- m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
+ m360.sdcr = M360_SDMA_FREEZE | M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
(4 << 13) | (0x1F << 8) | (128);
@@ -178,7 +258,7 @@ void _Init68360 (void)
* BCLRO* arbitration level 3
* No show cycles
* User/supervisor access
- * Bus clear interupt service level 7
+ * Bus clear interrupt service level 7
* SIM60 interrupt sources higher priority than CPM
*/
m360.mcr = 0x4C7F;
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-01 22:33:29 +0000