diff options
Diffstat (limited to 'c/src/lib/libbsp/arm/vegaplus/include/registers.h')
| -rw-r--r-- | c/src/lib/libbsp/arm/vegaplus/include/registers.h | 31 |
1 files changed, 0 insertions, 31 deletions
diff --git a/c/src/lib/libbsp/arm/vegaplus/include/registers.h b/c/src/lib/libbsp/arm/vegaplus/include/registers.h index 2a153fd8d9..c11fc851c3 100644 --- a/c/src/lib/libbsp/arm/vegaplus/include/registers.h +++ b/c/src/lib/libbsp/arm/vegaplus/include/registers.h @@ -10,7 +10,6 @@ * */ - #ifndef __LMREGS_H__ #define __LMREGS_H__ @@ -28,8 +27,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ #endif - - /****************************************************************************** * RADIO CONTROLLER BLOCK 0x0C00 - 0x0FFF * ****************************************************************************** @@ -71,7 +68,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ #define ADCPERIOD ((RC_BASE+0x7C)/4) #define SYNTIOCNTL ((RC_BASE+0x80)/4) /* added 30/08/99 */ - /* modified 30/08/99 by LHT */ #define SHAPE0 ((RC_BASE+0x100)/4) /* previously 0x80 */ #define SHAPE1 ((RC_BASE+0x104)/4) @@ -121,7 +117,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ #define TSTRXD ((PLP_BASE+0x78)/4) #define PLPID ((PLP_BASE+0x7C)/4) - /** ENCRYPTION ENGINE 0x1800 - 0x1BFF */ #define EE_BASE 0x1800 @@ -250,7 +245,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ #define RSCNT ((UART_BASE+0x20)/4) /*PRODUCT_VERSION*/ - /** THUMB and INTERFACES BLOCK 0x3400 - 0x4FFF */ #define TIM_BASE 0x3400 @@ -333,8 +327,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ #define SLEEPTIMER ((TI_BASE+0x204)/4) #define SLEEPCNTL ((TI_BASE+0x208)/4) - - /****************************************************************************** * BIT MASKS for Chip registers ****************************************************************************** @@ -358,8 +350,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ #define MSK_TADCMD 0x0F /* Mask on TADCMD */ #define CONTINUE 0x10 - - /** RADIO CONTROLER BLOCK (RC3) */ /* SLICECNTL register */ @@ -461,7 +451,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ /* RCCNTL register */ #define RCCNTL_ENABLE 0x80 - /* ADCCNTL1 register */ #define ADCSTART 0x80 #define SCAN 0x40 @@ -474,8 +463,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ #define ADCDWN1 0x04 #define ADCDWN2 0x08 - - /** PLP BLOCK */ /* DCNTL0 register */ @@ -511,7 +498,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ #define MSK_PRES 0x0F /* mask on PRES field */ - /* PLPALIN register */ #define SYNM 0x08 #define BITSLIP 0x10 @@ -537,7 +523,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ /* Bit ENABLE already defined */ #define EECNTL_ENABLE 0x80 - /** PAINT+ BLOCK */ /* PAINTCNTL register */ @@ -555,7 +540,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ #define FORCE13 0x4000 #define PAINTENB 0x8000 - /* PAINTPLLCNTL register */ #define MSK_MC 0x001F /* Mask on MC field */ #define MCSIGN 0x0020 @@ -649,7 +633,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ #define G726ENB0 0x0001 #define G726ENB1 0x0003 - /** GENERAL REGISTERS BLOCK */ /* RINGCNTL register */ @@ -730,7 +713,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ #define PWM0_PADENB 0x20 #define MIRROR 0x10 - /* LCDEECNTL1 register */ /* Bit ENABLE already defined */ #define LCDEE_ENABLE 0x80 @@ -788,7 +770,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ #define CSMODE_16_WHWL 0x0002 #define CSMODE_16_BHBL 0x0003 - /* MUXADCNTL register */ #define MSK_AHOLD 0x0007 #define MSK_ALEWIDTH 0x0070 @@ -815,11 +796,9 @@ extern volatile unsigned long *Regs; /* Chip registers */ #define ADDRESS_1M 0x3000 #define ADDRESS_2M 0x4000 - /* CSGCNTL register */ #define CSSWITCH 0x0040 - /* SLEEPCNTL register */ #define EXPIRED 0x01 #define SLEEP_ENABLE 0x80 @@ -828,12 +807,10 @@ extern volatile unsigned long *Regs; /* Chip registers */ #define WDSTROKE 0x80 #define WDFLAG 0x80 /* same bit */ - /* DCC register */ /* bit ENABLE=0x80 already defined */ #define DCC_ENABLE 0x80 - /* TIMERCNTL[0:1] register */ /* bit ENABLE=0x80 already defined */ #define TIMER_ENABLE 0x80 @@ -844,7 +821,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ #define TIMER_216kHz 0x0001 #define TIMER_27kHz 0x0000 - /* INTMASKALL register */ #define MASKIRQ 0x80 #define MASKFIQ 0x40 @@ -880,7 +856,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ /* INTHPAI register */ #define AUTOACK 0x0080 - /****************************************************************************** * Memory Mapping definition ****************************************************************************** @@ -899,7 +874,6 @@ extern volatile unsigned long *Regs; /* Chip registers */ #define REGS_BASE_ADR 0x000F0000 /* Base Address of registers */ #define RADRAM_BASE_ADR 0x000F0000 /* Base Address of registers */ - /****************************************************************************** * Slot Control bloc ****************************************************************************** @@ -1067,10 +1041,6 @@ typedef LM_SCB *LM_SCB_P; /* pointer to Slot Control Block */ #define LM_WIN_OPEN 0x3F /* wide open window size */ #define MSK_WINSZ 0x3F - - - - /* * Some macros to mask the VEGA+ interrupt sources ****************************************************************************** @@ -1085,7 +1055,6 @@ typedef LM_SCB *LM_SCB_P; /* pointer to Slot Control Block */ #define LM_MaskSTX() (LM_Regs[RSIER] &= ~TX_INT_ENABLE) #define LM_MaskUARTStatus() (LM_Regs[RSIER] &= ~LINE_STATUS_ENABLE) - #define LM_MaskTMR0() (LM_Regs[INTMASK] |= TMR0) #define LM_MaskTMR1() (LM_Regs[INTMASK] |= TMR1) #define LM_MaskLCDEE() (LM_Regs[INTMASK] |= LCDEE) |