diff options
Diffstat (limited to 'c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h')
| -rw-r--r-- | c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h | 111 |
1 files changed, 54 insertions, 57 deletions
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h index b4e227b8e3..0810fd097f 100644 --- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h +++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h @@ -36,8 +36,8 @@ * of the authors and should not be interpreted as representing official policies, * either expressed or implied, of the FreeBSD Project. */ -#ifndef LIBBSP_ARM_tms570_EMIF -#define LIBBSP_ARM_tms570_EMIF +#ifndef LIBBSP_ARM_TMS570_EMIF +#define LIBBSP_ARM_TMS570_EMIF #include <bsp/utility.h> @@ -62,19 +62,16 @@ typedef struct{ } tms570_emif_t; -/*----------------------TMS570_EMIFMIDR----------------------*/ +/*----------------------TMS570_EMIF_MIDR----------------------*/ /* field: REV - Module ID of EMIF. See the device-specific data manual. */ -#define TMS570_EMIF_MIDR_REV(val) BSP_FLD32(val,0, 31) -#define TMS570_EMIF_MIDR_REV_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_EMIF_MIDR_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) +/* Whole 32 bits */ - -/*----------------------TMS570_EMIFAWCC----------------------*/ +/*----------------------TMS570_EMIF_AWCC----------------------*/ /* field: WP1 - EMIF_nWAIT[1] polarity bit. This bit defines the polarity of the EMIF_nWAIT[1] pin. */ -#define TMS570_EMIF_AWCC_WP1 BSP_FLD32(29) +#define TMS570_EMIF_AWCC_WP1 BSP_BIT32(29) /* field: WP0 - EMIF_nWAIT[0] polarity bit. This bit defines the polarity of the EMIF_nWAIT[0] pin. */ -#define TMS570_EMIF_AWCC_WP0 BSP_FLD32(28) +#define TMS570_EMIF_AWCC_WP0 BSP_BIT32(28) /* field: CS5_WAIT - Chip Select 5 WAIT signal selection. */ #define TMS570_EMIF_AWCC_CS5_WAIT(val) BSP_FLD32(val,22, 23) @@ -102,18 +99,18 @@ typedef struct{ #define TMS570_EMIF_AWCC_MAX_EXT_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) -/*----------------------TMS570_EMIFSDCR----------------------*/ +/*----------------------TMS570_EMIF_SDCR----------------------*/ /* field: SR - Self-Refresh mode bit. */ -#define TMS570_EMIF_SDCR_SR BSP_FLD32(31) +#define TMS570_EMIF_SDCR_SR BSP_BIT32(31) /* field: PD - Power Down bit. This bit controls entering and exiting of the power-down mode. */ -#define TMS570_EMIF_SDCR_PD BSP_FLD32(30) +#define TMS570_EMIF_SDCR_PD BSP_BIT32(30) /* field: PDWR - Perform refreshes during power down. */ -#define TMS570_EMIF_SDCR_PDWR BSP_FLD32(29) +#define TMS570_EMIF_SDCR_PDWR BSP_BIT32(29) /* field: NM - Narrow mode bit. This bit defines whether a 16- or 32-bit-wide SDRAM is connected to the EMIF. */ -#define TMS570_EMIF_SDCR_NM BSP_FLD32(14) +#define TMS570_EMIF_SDCR_NM BSP_BIT32(14) /* field: CL - CAS Latency. */ #define TMS570_EMIF_SDCR_CL(val) BSP_FLD32(val,9, 11) @@ -121,7 +118,7 @@ typedef struct{ #define TMS570_EMIF_SDCR_CL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11) /* field: BIT11_9LOCK - Bits 11 to 9 lock. CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */ -#define TMS570_EMIF_SDCR_BIT11_9LOCK BSP_FLD32(8) +#define TMS570_EMIF_SDCR_BIT11_9LOCK BSP_BIT32(8) /* field: IBANK - Internal SDRAM Bank size. */ #define TMS570_EMIF_SDCR_IBANK(val) BSP_FLD32(val,4, 6) @@ -134,19 +131,19 @@ typedef struct{ #define TMS570_EMIF_SDCR_PAGESIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2) -/*----------------------TMS570_EMIFSDRCR----------------------*/ +/*---------------------TMS570_EMIF_SDRCR---------------------*/ /* field: RR - Refresh Rate. This field is used to define the SDRAM refresh period in terms of EMIF_CLK cycles. */ #define TMS570_EMIF_SDRCR_RR(val) BSP_FLD32(val,0, 12) #define TMS570_EMIF_SDRCR_RR_GET(reg) BSP_FLD32GET(reg,0, 12) #define TMS570_EMIF_SDRCR_RR_SET(reg,val) BSP_FLD32SET(reg, val,0, 12) -/*---------------------TMS570_EMIFCE2CFG---------------------*/ +/*---------------------TMS570_EMIF_CE2CFG---------------------*/ /* field: SS - Select Strobe bit. */ -#define TMS570_EMIF_CE2CFG_SS BSP_FLD32(31) +#define TMS570_EMIF_CE2CFG_SS BSP_BIT32(31) /* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */ -#define TMS570_EMIF_CE2CFG_EW BSP_FLD32(30) +#define TMS570_EMIF_CE2CFG_EW BSP_BIT32(30) /* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ #define TMS570_EMIF_CE2CFG_W_SETUP(val) BSP_FLD32(val,26, 29) @@ -189,12 +186,12 @@ typedef struct{ #define TMS570_EMIF_CE2CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) -/*---------------------TMS570_EMIFCE3CFG---------------------*/ +/*---------------------TMS570_EMIF_CE3CFG---------------------*/ /* field: SS - Select Strobe bit. */ -#define TMS570_EMIF_CE3CFG_SS BSP_FLD32(31) +#define TMS570_EMIF_CE3CFG_SS BSP_BIT32(31) /* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */ -#define TMS570_EMIF_CE3CFG_EW BSP_FLD32(30) +#define TMS570_EMIF_CE3CFG_EW BSP_BIT32(30) /* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ #define TMS570_EMIF_CE3CFG_W_SETUP(val) BSP_FLD32(val,26, 29) @@ -237,12 +234,12 @@ typedef struct{ #define TMS570_EMIF_CE3CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) -/*---------------------TMS570_EMIFCE4CFG---------------------*/ +/*---------------------TMS570_EMIF_CE4CFG---------------------*/ /* field: SS - Select Strobe bit. */ -#define TMS570_EMIF_CE4CFG_SS BSP_FLD32(31) +#define TMS570_EMIF_CE4CFG_SS BSP_BIT32(31) /* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */ -#define TMS570_EMIF_CE4CFG_EW BSP_FLD32(30) +#define TMS570_EMIF_CE4CFG_EW BSP_BIT32(30) /* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ #define TMS570_EMIF_CE4CFG_W_SETUP(val) BSP_FLD32(val,26, 29) @@ -285,12 +282,12 @@ typedef struct{ #define TMS570_EMIF_CE4CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) -/*---------------------TMS570_EMIFCE5CFG---------------------*/ +/*---------------------TMS570_EMIF_CE5CFG---------------------*/ /* field: SS - Select Strobe bit. */ -#define TMS570_EMIF_CE5CFG_SS BSP_FLD32(31) +#define TMS570_EMIF_CE5CFG_SS BSP_BIT32(31) /* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */ -#define TMS570_EMIF_CE5CFG_EW BSP_FLD32(30) +#define TMS570_EMIF_CE5CFG_EW BSP_BIT32(30) /* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */ #define TMS570_EMIF_CE5CFG_W_SETUP(val) BSP_FLD32(val,26, 29) @@ -333,7 +330,7 @@ typedef struct{ #define TMS570_EMIF_CE5CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) -/*---------------------TMS570_EMIFSDTIMR---------------------*/ +/*---------------------TMS570_EMIF_SDTIMR---------------------*/ /* field: T_RFC - Specifies the Trfc value of the SDRAM. */ #define TMS570_EMIF_SDTIMR_T_RFC(val) BSP_FLD32(val,27, 31) #define TMS570_EMIF_SDTIMR_T_RFC_GET(reg) BSP_FLD32GET(reg,27, 31) @@ -370,68 +367,68 @@ typedef struct{ #define TMS570_EMIF_SDTIMR_T_RRD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6) -/*---------------------TMS570_EMIFSDSRETR---------------------*/ +/*--------------------TMS570_EMIF_SDSRETR--------------------*/ /* field: T_XS - This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command, */ #define TMS570_EMIF_SDSRETR_T_XS(val) BSP_FLD32(val,0, 4) #define TMS570_EMIF_SDSRETR_T_XS_GET(reg) BSP_FLD32GET(reg,0, 4) #define TMS570_EMIF_SDSRETR_T_XS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) -/*---------------------TMS570_EMIFINTRAW---------------------*/ +/*---------------------TMS570_EMIF_INTRAW---------------------*/ /* field: WR - Wait Rise. */ -#define TMS570_EMIF_INTRAW_WR BSP_FLD32(2) +#define TMS570_EMIF_INTRAW_WR BSP_BIT32(2) /* field: LT - Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line size. */ -#define TMS570_EMIF_INTRAW_LT BSP_FLD32(1) +#define TMS570_EMIF_INTRAW_LT BSP_BIT32(1) /* field: AT - Asynchronous Timeout. */ -#define TMS570_EMIF_INTRAW_AT BSP_FLD32(0) +#define TMS570_EMIF_INTRAW_AT BSP_BIT32(0) -/*---------------------TMS570_EMIFINTMSK---------------------*/ +/*---------------------TMS570_EMIF_INTMSK---------------------*/ /* field: WR_MASKED - Wait Rise Masked. */ -#define TMS570_EMIF_INTMSK_WR_MASKED BSP_FLD32(2) +#define TMS570_EMIF_INTMSK_WR_MASKED BSP_BIT32(2) /* field: LT_MASKED - Masked Line Trap. */ -#define TMS570_EMIF_INTMSK_LT_MASKED BSP_FLD32(1) +#define TMS570_EMIF_INTMSK_LT_MASKED BSP_BIT32(1) /* field: AT_MASKED - Asynchronous Timeout Masked. */ -#define TMS570_EMIF_INTMSK_AT_MASKED BSP_FLD32(0) +#define TMS570_EMIF_INTMSK_AT_MASKED BSP_BIT32(0) -/*--------------------TMS570_EMIFINTMSKSET--------------------*/ +/*-------------------TMS570_EMIF_INTMSKSET-------------------*/ /* field: WR_MASK_SET - Wait Rise Mask Set. This bit determines whether or not the wait rise Interrupt is enabled. */ -#define TMS570_EMIF_INTMSKSET_WR_MASK_SET BSP_FLD32(2) +#define TMS570_EMIF_INTMSKSET_WR_MASK_SET BSP_BIT32(2) /* field: LT_MASK_SET - LT_MASK_SET Mask set for LT_MASKED bit in the EMIF interrupt mask register (INTMSK). */ -#define TMS570_EMIF_INTMSKSET_LT_MASK_SET BSP_FLD32(1) +#define TMS570_EMIF_INTMSKSET_LT_MASK_SET BSP_BIT32(1) /* field: AT_MASK_SET - Asynchronous Timeout Mask Set. */ -#define TMS570_EMIF_INTMSKSET_AT_MASK_SET BSP_FLD32(0) +#define TMS570_EMIF_INTMSKSET_AT_MASK_SET BSP_BIT32(0) -/*--------------------TMS570_EMIFINTMSKCLR--------------------*/ +/*-------------------TMS570_EMIF_INTMSKCLR-------------------*/ /* field: WR_MASK_CLR - Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. */ -#define TMS570_EMIF_INTMSKCLR_WR_MASK_CLR BSP_FLD32(2) +#define TMS570_EMIF_INTMSKCLR_WR_MASK_CLR BSP_BIT32(2) /* field: LT_MASK_CLR - 1 to this bit clears this bit, clears the LT_MASK_SET bit in the EMIF interrupt mask set register */ -#define TMS570_EMIF_INTMSKCLR_LT_MASK_CLR BSP_FLD32(1) +#define TMS570_EMIF_INTMSKCLR_LT_MASK_CLR BSP_BIT32(1) /* field: AT_MASK_CLR - Asynchronous Timeout Mask Clear. */ -#define TMS570_EMIF_INTMSKCLR_AT_MASK_CLR BSP_FLD32(0) +#define TMS570_EMIF_INTMSKCLR_AT_MASK_CLR BSP_BIT32(0) -/*----------------------TMS570_EMIFPMCR----------------------*/ +/*----------------------TMS570_EMIF_PMCR----------------------*/ /* field: CS5_PG_DEL - Page access delay for NOR Flash connected on CS5. CS5 is not available on this device. */ #define TMS570_EMIF_PMCR_CS5_PG_DEL(val) BSP_FLD32(val,26, 31) #define TMS570_EMIF_PMCR_CS5_PG_DEL_GET(reg) BSP_FLD32GET(reg,26, 31) #define TMS570_EMIF_PMCR_CS5_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,26, 31) /* field: CS5_PG_SIZE - Page Size for NOR Flash connected on CS5. CS5 is not available on this device. */ -#define TMS570_EMIF_PMCR_CS5_PG_SIZE BSP_FLD32(25) +#define TMS570_EMIF_PMCR_CS5_PG_SIZE BSP_BIT32(25) /* field: CS5_PG_MD_EN - Page Mode enable for NOR Flash connected on CS5. CS5 is not available on this device. */ -#define TMS570_EMIF_PMCR_CS5_PG_MD_EN BSP_FLD32(24) +#define TMS570_EMIF_PMCR_CS5_PG_MD_EN BSP_BIT32(24) /* field: CS4_PG_DEL - Page access delay for NOR Flash connected on CS4. */ #define TMS570_EMIF_PMCR_CS4_PG_DEL(val) BSP_FLD32(val,18, 23) @@ -439,10 +436,10 @@ typedef struct{ #define TMS570_EMIF_PMCR_CS4_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,18, 23) /* field: CS4_PG_SIZE - Page Size for NOR Flash connected on CS4. */ -#define TMS570_EMIF_PMCR_CS4_PG_SIZE BSP_FLD32(17) +#define TMS570_EMIF_PMCR_CS4_PG_SIZE BSP_BIT32(17) /* field: CS4_PG_MD_EN - Page Mode enable for NOR Flash connected on CS4. */ -#define TMS570_EMIF_PMCR_CS4_PG_MD_EN BSP_FLD32(16) +#define TMS570_EMIF_PMCR_CS4_PG_MD_EN BSP_BIT32(16) /* field: CS3_PG_DEL - the page read data to be valid, minus one cycle. This value must not be cleared to 0. */ #define TMS570_EMIF_PMCR_CS3_PG_DEL(val) BSP_FLD32(val,10, 15) @@ -450,10 +447,10 @@ typedef struct{ #define TMS570_EMIF_PMCR_CS3_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,10, 15) /* field: CS3_PG_SIZE - Page Size for NOR Flash connected on CS3. */ -#define TMS570_EMIF_PMCR_CS3_PG_SIZE BSP_FLD32(9) +#define TMS570_EMIF_PMCR_CS3_PG_SIZE BSP_BIT32(9) /* field: CS3_PG_MD_EN - Page Mode enable for NOR Flash connected on CS3. */ -#define TMS570_EMIF_PMCR_CS3_PG_MD_EN BSP_FLD32(8) +#define TMS570_EMIF_PMCR_CS3_PG_MD_EN BSP_BIT32(8) /* field: CS2_PG_DEL - Page access delay for NOR Flash connected on CS2. */ #define TMS570_EMIF_PMCR_CS2_PG_DEL(val) BSP_FLD32(val,2, 7) @@ -461,11 +458,11 @@ typedef struct{ #define TMS570_EMIF_PMCR_CS2_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 7) /* field: CS2_PG_SIZE - Page Size for NOR Flash connected on CS2. */ -#define TMS570_EMIF_PMCR_CS2_PG_SIZE BSP_FLD32(1) +#define TMS570_EMIF_PMCR_CS2_PG_SIZE BSP_BIT32(1) /* field: CS2_PG_MD_EN - Page Mode enable for NOR Flash connected on CS2. */ -#define TMS570_EMIF_PMCR_CS2_PG_MD_EN BSP_FLD32(0) +#define TMS570_EMIF_PMCR_CS2_PG_MD_EN BSP_BIT32(0) -#endif /* LIBBSP_ARM_tms570_EMIF */ +#endif /* LIBBSP_ARM_TMS570_EMIF */ |