diff options
Diffstat (limited to 'c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h')
| -rw-r--r-- | c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h | 234 |
1 files changed, 93 insertions, 141 deletions
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h index 8798c121c7..f1352f67b6 100644 --- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h +++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h @@ -36,8 +36,8 @@ * of the authors and should not be interpreted as representing official policies, * either expressed or implied, of the FreeBSD Project. */ -#ifndef LIBBSP_ARM_tms570_CRC -#define LIBBSP_ARM_tms570_CRC +#ifndef LIBBSP_ARM_TMS570_CRC +#define LIBBSP_ARM_TMS570_CRC #include <bsp/utility.h> @@ -91,27 +91,27 @@ typedef struct{ } tms570_crc_t; -/*----------------------TMS570_CRCCTRL0----------------------*/ +/*----------------------TMS570_CRC_CTRL0----------------------*/ /* field: CH2_PSA_SWREST - Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */ -#define TMS570_CRC_CTRL0_CH2_PSA_SWREST BSP_FLD32(8) +#define TMS570_CRC_CTRL0_CH2_PSA_SWREST BSP_BIT32(8) /* field: CH1_PSA_SWREST - Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */ -#define TMS570_CRC_CTRL0_CH1_PSA_SWREST BSP_FLD32(0) +#define TMS570_CRC_CTRL0_CH1_PSA_SWREST BSP_BIT32(0) -/*----------------------TMS570_CRCCTRL1----------------------*/ +/*----------------------TMS570_CRC_CTRL1----------------------*/ /* field: PWDN - Power Down. */ -#define TMS570_CRC_CTRL1_PWDN BSP_FLD32(0) +#define TMS570_CRC_CTRL1_PWDN BSP_BIT32(0) -/*----------------------TMS570_CRCCTRL2----------------------*/ +/*----------------------TMS570_CRC_CTRL2----------------------*/ /* field: CH2_MODE - Channel 2 Mode Selection */ #define TMS570_CRC_CTRL2_CH2_MODE(val) BSP_FLD32(val,8, 9) #define TMS570_CRC_CTRL2_CH2_MODE_GET(reg) BSP_FLD32GET(reg,8, 9) #define TMS570_CRC_CTRL2_CH2_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) /* field: CH1_TRACEEN - Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. */ -#define TMS570_CRC_CTRL2_CH1_TRACEEN BSP_FLD32(4) +#define TMS570_CRC_CTRL2_CH1_TRACEEN BSP_BIT32(4) /* field: CH1_MODE - Channel 1 Mode Selection */ #define TMS570_CRC_CTRL2_CH1_MODE(val) BSP_FLD32(val,0, 1) @@ -119,309 +119,261 @@ typedef struct{ #define TMS570_CRC_CTRL2_CH1_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) -/*-----------------------TMS570_CRCINTS-----------------------*/ +/*----------------------TMS570_CRC_INTS----------------------*/ /* field: CH2_TIMEOUTENS - Channel 2 Timeout Interrupt Enable Bit. */ -#define TMS570_CRC_INTS_CH2_TIMEOUTENS BSP_FLD32(12) +#define TMS570_CRC_INTS_CH2_TIMEOUTENS BSP_BIT32(12) /* field: CH2_UNDERENS - Channel 2 Underrun Interrupt Enable Bit. */ -#define TMS570_CRC_INTS_CH2_UNDERENS BSP_FLD32(11) +#define TMS570_CRC_INTS_CH2_UNDERENS BSP_BIT32(11) /* field: CH2_OVERENS - Channel 2 Overrun Interrupt Enable Bit. */ -#define TMS570_CRC_INTS_CH2_OVERENS BSP_FLD32(10) +#define TMS570_CRC_INTS_CH2_OVERENS BSP_BIT32(10) /* field: CH2_CRCFAILENS - Channel 2 CRC Fail Interrupt Enable Bit. */ -#define TMS570_CRC_INTS_CH2_CRCFAILENS BSP_FLD32(9) +#define TMS570_CRC_INTS_CH2_CRCFAILENS BSP_BIT32(9) /* field: CH2_CCITENS - Channel 2 Compression Complete Interrupt Enable Bit. */ -#define TMS570_CRC_INTS_CH2_CCITENS BSP_FLD32(8) +#define TMS570_CRC_INTS_CH2_CCITENS BSP_BIT32(8) /* field: CH1_TIMEOUTENS - Channel 1 Timeout Interrupt Enable Bit. */ -#define TMS570_CRC_INTS_CH1_TIMEOUTENS BSP_FLD32(4) +#define TMS570_CRC_INTS_CH1_TIMEOUTENS BSP_BIT32(4) /* field: CH1_UNDERENS - Channel 1 Underrun Interrupt Enable Bit. */ -#define TMS570_CRC_INTS_CH1_UNDERENS BSP_FLD32(3) +#define TMS570_CRC_INTS_CH1_UNDERENS BSP_BIT32(3) /* field: CH1_OVERENS - CH1_OVERENS Channel 1 Overrun Interrupt Enable Bit. */ -#define TMS570_CRC_INTS_CH1_OVERENS BSP_FLD32(2) +#define TMS570_CRC_INTS_CH1_OVERENS BSP_BIT32(2) /* field: CH1_CRCFAILENS - Channel 1 CRC Fail Interrupt Enable Bit. */ -#define TMS570_CRC_INTS_CH1_CRCFAILENS BSP_FLD32(1) +#define TMS570_CRC_INTS_CH1_CRCFAILENS BSP_BIT32(1) /* field: CH1_CCITENS - Channel 1 Compression Complete Interrupt Enable Bit. */ -#define TMS570_CRC_INTS_CH1_CCITENS BSP_FLD32(0) +#define TMS570_CRC_INTS_CH1_CCITENS BSP_BIT32(0) -/*-----------------------TMS570_CRCINTR-----------------------*/ +/*----------------------TMS570_CRC_INTR----------------------*/ /* field: CH2_TIMEOUTENR - Channel 2 Timeout Interrupt Enable Bit. */ -#define TMS570_CRC_INTR_CH2_TIMEOUTENR BSP_FLD32(12) +#define TMS570_CRC_INTR_CH2_TIMEOUTENR BSP_BIT32(12) /* field: CH2_UNDERENR - Channel 2 Underrun Interrupt Enable Bit. */ -#define TMS570_CRC_INTR_CH2_UNDERENR BSP_FLD32(11) +#define TMS570_CRC_INTR_CH2_UNDERENR BSP_BIT32(11) /* field: CH2_OVERENR - Channel 2 Overrun Interrupt Enable Bit. */ -#define TMS570_CRC_INTR_CH2_OVERENR BSP_FLD32(10) +#define TMS570_CRC_INTR_CH2_OVERENR BSP_BIT32(10) /* field: CH2_CRCFAILENR - Channel 2 CRC Fail Interrupt Enable Bit. */ -#define TMS570_CRC_INTR_CH2_CRCFAILENR BSP_FLD32(9) +#define TMS570_CRC_INTR_CH2_CRCFAILENR BSP_BIT32(9) /* field: CH2_CCITENR - Channel 2 Compression Complete Interrupt Enable Bit. */ -#define TMS570_CRC_INTR_CH2_CCITENR BSP_FLD32(8) +#define TMS570_CRC_INTR_CH2_CCITENR BSP_BIT32(8) /* field: CH1_TIMEOUTENR - Channel 1 Timeout Interrupt Enable Bit. */ -#define TMS570_CRC_INTR_CH1_TIMEOUTENR BSP_FLD32(4) +#define TMS570_CRC_INTR_CH1_TIMEOUTENR BSP_BIT32(4) /* field: CH1_UNDERENR - interrupt. Writing a zero has no effect. */ -#define TMS570_CRC_INTR_CH1_UNDERENR BSP_FLD32(3) +#define TMS570_CRC_INTR_CH1_UNDERENR BSP_BIT32(3) /* field: CH1_OVERENR - CH1_OVERENR */ -#define TMS570_CRC_INTR_CH1_OVERENR BSP_FLD32(2) +#define TMS570_CRC_INTR_CH1_OVERENR BSP_BIT32(2) /* field: CH1_CRCFAILENR - Channel 1 CRC Fail Interrupt Enable Bit. */ -#define TMS570_CRC_INTR_CH1_CRCFAILENR BSP_FLD32(1) +#define TMS570_CRC_INTR_CH1_CRCFAILENR BSP_BIT32(1) /* field: CH1_CCITENR - Channel 1 Compression Complete Interrupt Enable Bit. */ -#define TMS570_CRC_INTR_CH1_CCITENR BSP_FLD32(0) +#define TMS570_CRC_INTR_CH1_CCITENR BSP_BIT32(0) -/*----------------------TMS570_CRCSTATUS----------------------*/ +/*---------------------TMS570_CRC_STATUS---------------------*/ /* field: CH2_TIMEOUT - Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a '1' to it only. */ -#define TMS570_CRC_STATUS_CH2_TIMEOUT BSP_FLD32(12) +#define TMS570_CRC_STATUS_CH2_TIMEOUT BSP_BIT32(12) /* field: CH2_UNDER - Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a '1' to it only. */ -#define TMS570_CRC_STATUS_CH2_UNDER BSP_FLD32(11) +#define TMS570_CRC_STATUS_CH2_UNDER BSP_BIT32(11) /* field: CH2_OVER - Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a '1' to it only. */ -#define TMS570_CRC_STATUS_CH2_OVER BSP_FLD32(10) +#define TMS570_CRC_STATUS_CH2_OVER BSP_BIT32(10) /* field: CH2_CRCFAIL - Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a '1' to it only. */ -#define TMS570_CRC_STATUS_CH2_CRCFAIL BSP_FLD32(9) +#define TMS570_CRC_STATUS_CH2_CRCFAIL BSP_BIT32(9) /* field: CH2_CCIT - Channel 2 CRC Pattern Compression Complete Status Flag. */ -#define TMS570_CRC_STATUS_CH2_CCIT BSP_FLD32(8) +#define TMS570_CRC_STATUS_CH2_CCIT BSP_BIT32(8) /* field: CH1_TIMEOUT - Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). */ -#define TMS570_CRC_STATUS_CH1_TIMEOUT BSP_FLD32(4) +#define TMS570_CRC_STATUS_CH1_TIMEOUT BSP_BIT32(4) /* field: CH1_UNDER - Channel 1 Underrun Interrupt Enable Bit. */ -#define TMS570_CRC_STATUS_CH1_UNDER BSP_FLD32(3) +#define TMS570_CRC_STATUS_CH1_UNDER BSP_BIT32(3) /* field: CH1_OVER - Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit disable the overrun interrupt. */ -#define TMS570_CRC_STATUS_CH1_OVER BSP_FLD32(2) +#define TMS570_CRC_STATUS_CH1_OVER BSP_BIT32(2) /* field: CH1_CRCFAIL - Channel 1 CRC Fail Interrupt Enable Bit. */ -#define TMS570_CRC_STATUS_CH1_CRCFAIL BSP_FLD32(1) +#define TMS570_CRC_STATUS_CH1_CRCFAIL BSP_BIT32(1) /* field: CH1_CCIT - Channel 1 CRC Pattern Compression Complete Status Flag. */ -#define TMS570_CRC_STATUS_CH1_CCIT BSP_FLD32(0) +#define TMS570_CRC_STATUS_CH1_CCIT BSP_BIT32(0) -/*-------------------TMS570_CRCINT_OFFS_REG-------------------*/ +/*------------------TMS570_CRC_INT_OFFS_REG------------------*/ /* field: OFSTREG - CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. */ #define TMS570_CRC_INT_OFFS_REG_OFSTREG(val) BSP_FLD32(val,0, 7) #define TMS570_CRC_INT_OFFS_REG_OFSTREG_GET(reg) BSP_FLD32GET(reg,0, 7) #define TMS570_CRC_INT_OFFS_REG_OFSTREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) -/*-----------------------TMS570_CRCBUSY-----------------------*/ +/*----------------------TMS570_CRC_BUSY----------------------*/ /* field: CH2_BUSY - CH2_BUSY. */ -#define TMS570_CRC_BUSY_CH2_BUSY BSP_FLD32(8) +#define TMS570_CRC_BUSY_CH2_BUSY BSP_BIT32(8) /* field: CH1_BUSY - CH1_BUSY. */ -#define TMS570_CRC_BUSY_CH1_BUSY BSP_FLD32(0) +#define TMS570_CRC_BUSY_CH1_BUSY BSP_BIT32(0) -/*-------------------TMS570_CRCPCOUNT_REG1-------------------*/ +/*-------------------TMS570_CRC_PCOUNT_REG1-------------------*/ /* field: CRC_PAT_COUNT1 - Channel 1 Pattern Counter Preload Register. */ #define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1(val) BSP_FLD32(val,0, 19) #define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19) #define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) -/*-------------------TMS570_CRCSCOUNT_REG1-------------------*/ +/*-------------------TMS570_CRC_SCOUNT_REG1-------------------*/ /* field: CRC_SEC_COUNT1 - Channel 1 Sector Counter Preload Register. */ #define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1(val) BSP_FLD32(val,0, 15) #define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 15) #define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) -/*-------------------TMS570_CRCCURSEC_REG1-------------------*/ +/*-------------------TMS570_CRC_CURSEC_REG1-------------------*/ /* field: CRC_CURSEC1 - Channel 1 Current Sector ID Register. */ #define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1(val) BSP_FLD32(val,0, 15) #define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_GET(reg) BSP_FLD32GET(reg,0, 15) #define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) -/*---------------------TMS570_CRCWDTOPLD1---------------------*/ +/*--------------------TMS570_CRC_WDTOPLD1--------------------*/ /* field: CRC_WDTOPLD1 - CRC_WDTOPLD1 */ #define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1(val) BSP_FLD32(val,0, 23) #define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23) #define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) -/*---------------------TMS570_CRCBCTOPLD1---------------------*/ +/*--------------------TMS570_CRC_BCTOPLD1--------------------*/ /* field: CRC_BCTOPLD1 - Channel 1 Block Complete Timeout Counter Preload Register. */ #define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1(val) BSP_FLD32(val,0, 23) #define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23) #define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) -/*-------------------TMS570_CRCPSA_SIGREGL1-------------------*/ +/*------------------TMS570_CRC_PSA_SIGREGL1------------------*/ /* field: PSASIG1 - Channel 1 PSA Signature Low Register. */ -#define TMS570_CRC_PSA_SIGREGL1_PSASIG1(val) BSP_FLD32(val,0, 31) -#define TMS570_CRC_PSA_SIGREGL1_PSASIG1_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_CRC_PSA_SIGREGL1_PSASIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) +/* Whole 32 bits */ - -/*-------------------TMS570_CRCPSA_SIGREGH1-------------------*/ +/*------------------TMS570_CRC_PSA_SIGREGH1------------------*/ /* field: PSASIG1 - register. */ -#define TMS570_CRC_PSA_SIGREGH1_PSASIG1(val) BSP_FLD32(val,0, 31) -#define TMS570_CRC_PSA_SIGREGH1_PSASIG1_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_CRC_PSA_SIGREGH1_PSASIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) - +/* Whole 32 bits */ -/*----------------------TMS570_CRCREGL1----------------------*/ +/*----------------------TMS570_CRC_REGL1----------------------*/ /* field: CRC1 - Channel 1 CRC Value Low Register. */ -#define TMS570_CRC_REGL1_CRC1(val) BSP_FLD32(val,0, 31) -#define TMS570_CRC_REGL1_CRC1_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_CRC_REGL1_CRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) +/* Whole 32 bits */ - -/*----------------------TMS570_CRCREGH1----------------------*/ +/*----------------------TMS570_CRC_REGH1----------------------*/ /* field: CRC1 - Channel 1 CRC Value Low Register. */ -#define TMS570_CRC_REGH1_CRC1(val) BSP_FLD32(val,0, 31) -#define TMS570_CRC_REGH1_CRC1_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_CRC_REGH1_CRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) - +/* Whole 32 bits */ -/*-----------------TMS570_CRCPSA_SECSIGREGL1-----------------*/ +/*-----------------TMS570_CRC_PSA_SECSIGREGL1-----------------*/ /* field: PSASECSIG1 - Channel 1 PSA Sector Signature Low Register. */ -#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1(val) BSP_FLD32(val,0, 31) -#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) +/* Whole 32 bits */ - -/*-----------------TMS570_CRCPSA_SECSIGREGH1-----------------*/ +/*-----------------TMS570_CRC_PSA_SECSIGREGH1-----------------*/ /* field: PSASECSIG1 - Channel 1 PSA Sector Signature High Register. */ -#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1(val) BSP_FLD32(val,0, 31) -#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) - +/* Whole 32 bits */ -/*------------------TMS570_CRCRAW_DATAREGL1------------------*/ +/*------------------TMS570_CRC_RAW_DATAREGL1------------------*/ /* field: RAW_DATA1 - hannel 1 Raw Data Low Register.This register contains bits 31:0 of the uncompressed raw data. */ -#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1(val) BSP_FLD32(val,0, 31) -#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) +/* Whole 32 bits */ - -/*------------------TMS570_CRCRAW_DATAREGH1------------------*/ +/*------------------TMS570_CRC_RAW_DATAREGH1------------------*/ /* field: RAW_DATA1 - Channel 1 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data. */ -#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1(val) BSP_FLD32(val,0, 31) -#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) - +/* Whole 32 bits */ -/*-------------------TMS570_CRCPCOUNT_REG2-------------------*/ +/*-------------------TMS570_CRC_PCOUNT_REG2-------------------*/ /* field: CRC_PAT_COUNT2 - Channel 2 Pattern Counter Preload Register. */ #define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2(val) BSP_FLD32(val,0, 19) #define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 19) #define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) -/*-------------------TMS570_CRCSCOUNT_REG2-------------------*/ +/*-------------------TMS570_CRC_SCOUNT_REG2-------------------*/ /* field: CRC_SEC_COUNT2 - Channel 2 Sector Counter Preload Register. */ #define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2(val) BSP_FLD32(val,0, 15) #define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 15) #define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) -/*-------------------TMS570_CRCCURSEC_REG2-------------------*/ +/*-------------------TMS570_CRC_CURSEC_REG2-------------------*/ /* field: CRC_CURSEC2 - Channel 2 Current Sector ID Register. */ #define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2(val) BSP_FLD32(val,0, 15) #define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_GET(reg) BSP_FLD32GET(reg,0, 15) #define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) -/*---------------------TMS570_CRCWDTOPLD2---------------------*/ +/*--------------------TMS570_CRC_WDTOPLD2--------------------*/ /* field: CRC_WDTOPLD2 - Channel 2 Watchdog Timeout Counter Preload Register. */ #define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2(val) BSP_FLD32(val,0, 23) #define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23) #define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) -/*---------------------TMS570_CRCBCTOPLD2---------------------*/ +/*--------------------TMS570_CRC_BCTOPLD2--------------------*/ /* field: CRC_BCTOPLD2 - Channel 2 Block Complete Timeout Counter Preload Register. */ #define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2(val) BSP_FLD32(val,0, 23) #define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23) #define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) -/*-------------------TMS570_CRCPSA_SIGREGL2-------------------*/ +/*------------------TMS570_CRC_PSA_SIGREGL2------------------*/ /* field: PSASIG2 - Channel 2 PSA Signature Low Register. */ -#define TMS570_CRC_PSA_SIGREGL2_PSASIG2(val) BSP_FLD32(val,0, 31) -#define TMS570_CRC_PSA_SIGREGL2_PSASIG2_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_CRC_PSA_SIGREGL2_PSASIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) +/* Whole 32 bits */ - -/*-------------------TMS570_CRCPSA_SIGREGH2-------------------*/ +/*------------------TMS570_CRC_PSA_SIGREGH2------------------*/ /* field: PSASIG2 - Channel 2 PSA Signature High Register. */ -#define TMS570_CRC_PSA_SIGREGH2_PSASIG2(val) BSP_FLD32(val,0, 31) -#define TMS570_CRC_PSA_SIGREGH2_PSASIG2_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_CRC_PSA_SIGREGH2_PSASIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) - +/* Whole 32 bits */ -/*----------------------TMS570_CRCREGL2----------------------*/ +/*----------------------TMS570_CRC_REGL2----------------------*/ /* field: CRC2 - stored at CRC2[31:0] register. */ -#define TMS570_CRC_REGL2_CRC2(val) BSP_FLD32(val,0, 31) -#define TMS570_CRC_REGL2_CRC2_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_CRC_REGL2_CRC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) +/* Whole 32 bits */ - -/*----------------------TMS570_CRCREGH2----------------------*/ +/*----------------------TMS570_CRC_REGH2----------------------*/ /* field: CRC2 - Channel 2 CRC Value High Register. */ -#define TMS570_CRC_REGH2_CRC2(val) BSP_FLD32(val,0, 31) -#define TMS570_CRC_REGH2_CRC2_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_CRC_REGH2_CRC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) - +/* Whole 32 bits */ -/*-----------------TMS570_CRCPSA_SECSIGREGL2-----------------*/ +/*-----------------TMS570_CRC_PSA_SECSIGREGL2-----------------*/ /* field: PSASECSIG2 - Channel 2 PSA Sector Signature Low Register. */ -#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2(val) BSP_FLD32(val,0, 31) -#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) +/* Whole 32 bits */ - -/*-----------------TMS570_CRCPSA_SECSIGREGH2-----------------*/ +/*-----------------TMS570_CRC_PSA_SECSIGREGH2-----------------*/ /* field: PSASECSIG2 - Channel 2 PSA Sector Signature High Register. */ -#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2(val) BSP_FLD32(val,0, 31) -#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) - +/* Whole 32 bits */ -/*------------------TMS570_CRCRAW_DATAREGL2------------------*/ +/*------------------TMS570_CRC_RAW_DATAREGL2------------------*/ /* field: RAW_DATA2 - Channel 2 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data.. */ -#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2(val) BSP_FLD32(val,0, 31) -#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) +/* Whole 32 bits */ - -/*------------------TMS570_CRCRAW_DATAREGH2------------------*/ +/*------------------TMS570_CRC_RAW_DATAREGH2------------------*/ /* field: RAW_DATA2 - Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data.. */ -#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2(val) BSP_FLD32(val,0, 31) -#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2_GET(reg) BSP_FLD32GET(reg,0, 31) -#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31) - +/* Whole 32 bits */ -/*---------------------TMS570_CRCBUS_SEL---------------------*/ +/*---------------------TMS570_CRC_BUS_SEL---------------------*/ /* field: MEn - Enable/disables the tracing of Peripheral Bus Master */ -#define TMS570_CRC_BUS_SEL_MEn BSP_FLD32(2) +#define TMS570_CRC_BUS_SEL_MEn BSP_BIT32(2) /* field: DTCMEn - Enable/disables the tracing of data TCM */ -#define TMS570_CRC_BUS_SEL_DTCMEn BSP_FLD32(1) +#define TMS570_CRC_BUS_SEL_DTCMEn BSP_BIT32(1) /* field: ITCMEn - Enable/disables the tracing of instruction TCM */ -#define TMS570_CRC_BUS_SEL_ITCMEn BSP_FLD32(0) +#define TMS570_CRC_BUS_SEL_ITCMEn BSP_BIT32(0) -#endif /* LIBBSP_ARM_tms570_CRC */ +#endif /* LIBBSP_ARM_TMS570_CRC */ |