diff options
Diffstat (limited to 'c/src/lib/libbsp/arm/stm32f4/include/io.h')
| -rw-r--r-- | c/src/lib/libbsp/arm/stm32f4/include/io.h | 204 |
1 files changed, 193 insertions, 11 deletions
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/io.h b/c/src/lib/libbsp/arm/stm32f4/include/io.h index 032664c48a..1d8c512ec8 100644 --- a/c/src/lib/libbsp/arm/stm32f4/include/io.h +++ b/c/src/lib/libbsp/arm/stm32f4/include/io.h @@ -16,13 +16,21 @@ #define LIBBSP_ARM_STM32F4_IO_H #include <stdbool.h> - -#include <bsp/stm32f4.h> +#include <stdint.h> +#include <bspopts.h> #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ +#define STM32F4_GPIO_PIN(port, index) ((((port) << 4) | (index)) & 0xff) + +#define STM32F4_GPIO_PORT_OF_PIN(pin) (((pin) >> 4) & 0xf) + +#define STM32F4_GPIO_INDEX_OF_PIN(pin) ((pin) & 0xf) + +#ifdef STM32F4_FAMILY_F4XXXX + typedef enum { STM32F4_GPIO_MODE_INPUT, STM32F4_GPIO_MODE_OUTPUT, @@ -86,12 +94,6 @@ typedef enum { STM32F4_GPIO_AF_EVENTOUT = 15 } stm32f4_gpio_af; -#define STM32F4_GPIO_PIN(port, index) ((((port) << 4) | (index)) & 0xff) - -#define STM32F4_GPIO_PORT_OF_PIN(pin) (((pin) >> 4) & 0xf) - -#define STM32F4_GPIO_INDEX_OF_PIN(pin) ((pin) & 0xf) - typedef union { struct { uint32_t pin_first : 8; @@ -108,15 +110,141 @@ typedef union { uint32_t value; } stm32f4_gpio_config; +#define STM32F4_GPIO_CONFIG_TERMINAL \ + { { 0xff, 0xff, 0x3, 0x1, 0x3, 0x3, 0x1, 0xf, 0xf } } + +#endif /* STM32F4_FAMILY_F4XXXX */ +#ifdef STM32F4_FAMILY_F10XXX + +typedef enum { + STM32F4_GPIO_MODE_INPUT, + STM32F4_GPIO_MODE_OUTPUT_10MHz, + STM32F4_GPIO_MODE_OUTPUT_2MHz, + STM32F4_GPIO_MODE_OUTPUT_50MHz +} stm32f4_gpio_mode; + +typedef enum { + STM32F4_GPIO_CNF_IN_ANALOG = 0, + STM32F4_GPIO_CNF_IN_FLOATING = 1, + STM32F4_GPIO_CNF_IN_PULL_UPDOWN = 2, + + STM32F4_GPIO_CNF_OUT_GPIO_PP = 0, + STM32F4_GPIO_CNF_OUT_GPIO_OD = 1, + STM32F4_GPIO_CNF_OUT_AF_PP = 2, + STM32F4_GPIO_CNF_OUT_AF_OD = 3, +} stm32f4_gpio_cnf; + +typedef enum { + STM32F4_GPIO_REMAP_DONT_CHANGE, + STM32F4_GPIO_REMAP_SPI1_0, + STM32F4_GPIO_REMAP_SPI1_1, + STM32F4_GPIO_REMAP_I2C1_0, + STM32F4_GPIO_REMAP_I2C1_1, + STM32F4_GPIO_REMAP_USART1_0, + STM32F4_GPIO_REMAP_USART1_1, + STM32F4_GPIO_REMAP_USART2_0, + STM32F4_GPIO_REMAP_USART2_1, + STM32F4_GPIO_REMAP_USART3_0, + STM32F4_GPIO_REMAP_USART3_1, + STM32F4_GPIO_REMAP_USART3_3, + STM32F4_GPIO_REMAP_TIM1_0, + STM32F4_GPIO_REMAP_TIM1_1, + STM32F4_GPIO_REMAP_TIM1_3, + STM32F4_GPIO_REMAP_TIM2_0, + STM32F4_GPIO_REMAP_TIM2_1, + STM32F4_GPIO_REMAP_TIM2_2, + STM32F4_GPIO_REMAP_TIM2_3, + STM32F4_GPIO_REMAP_TIM3_0, + STM32F4_GPIO_REMAP_TIM3_2, + STM32F4_GPIO_REMAP_TIM3_3, + STM32F4_GPIO_REMAP_TIM4_0, + STM32F4_GPIO_REMAP_TIM4_1, + STM32F4_GPIO_REMAP_CAN1_0, + STM32F4_GPIO_REMAP_CAN1_2, + STM32F4_GPIO_REMAP_CAN1_3, + STM32F4_GPIO_REMAP_PD01_0, + STM32F4_GPIO_REMAP_PD01_1, + STM32F4_GPIO_REMAP_TIM5CH4_0, + STM32F4_GPIO_REMAP_TIM5CH4_1, + STM32F4_GPIO_REMAP_ADC1_ETRGINJ_0, + STM32F4_GPIO_REMAP_ADC1_ETRGINJ_1, + STM32F4_GPIO_REMAP_ADC1_ETRGREG_0, + STM32F4_GPIO_REMAP_ADC1_ETRGREG_1, + STM32F4_GPIO_REMAP_ADC2_ETRGINJ_0, + STM32F4_GPIO_REMAP_ADC2_ETRGINJ_1, + STM32F4_GPIO_REMAP_ADC2_ETRGREG_0, + STM32F4_GPIO_REMAP_ADC2_ETRGREG_1, + STM32F4_GPIO_REMAP_ETH_0, + STM32F4_GPIO_REMAP_ETH_1, + STM32F4_GPIO_REMAP_CAN2_0, + STM32F4_GPIO_REMAP_CAN2_1, + STM32F4_GPIO_REMAP_MII_RMII_0, + STM32F4_GPIO_REMAP_MII_RMII_1, + STM32F4_GPIO_REMAP_SWJ_0, + STM32F4_GPIO_REMAP_SWJ_1, + STM32F4_GPIO_REMAP_SWJ_2, + STM32F4_GPIO_REMAP_SWJ_4, + STM32F4_GPIO_REMAP_SPI3_0, + STM32F4_GPIO_REMAP_SPI3_1, + STM32F4_GPIO_REMAP_TIM2ITR1_0, + STM32F4_GPIO_REMAP_TIM2ITR1_1, + STM32F4_GPIO_REMAP_PTP_PPS_0, + STM32F4_GPIO_REMAP_PTP_PPS_1, + STM32F4_GPIO_REMAP_TIM15_0, + STM32F4_GPIO_REMAP_TIM15_1, + STM32F4_GPIO_REMAP_TIM16_0, + STM32F4_GPIO_REMAP_TIM16_1, + STM32F4_GPIO_REMAP_TIM17_0, + STM32F4_GPIO_REMAP_TIM17_1, + STM32F4_GPIO_REMAP_CEC_0, + STM32F4_GPIO_REMAP_CEC_1, + STM32F4_GPIO_REMAP_TIM1_DMA_0, + STM32F4_GPIO_REMAP_TIM1_DMA_1, + STM32F4_GPIO_REMAP_TIM9_0, + STM32F4_GPIO_REMAP_TIM9_1, + STM32F4_GPIO_REMAP_TIM10_0, + STM32F4_GPIO_REMAP_TIM10_1, + STM32F4_GPIO_REMAP_TIM11_0, + STM32F4_GPIO_REMAP_TIM11_1, + STM32F4_GPIO_REMAP_TIM13_0, + STM32F4_GPIO_REMAP_TIM13_1, + STM32F4_GPIO_REMAP_TIM14_0, + STM32F4_GPIO_REMAP_TIM14_1, + STM32F4_GPIO_REMAP_FSMC_0, + STM32F4_GPIO_REMAP_FSMC_1, + STM32F4_GPIO_REMAP_TIM67_DAC_DMA_0, + STM32F4_GPIO_REMAP_TIM67_DAC_DMA_1, + STM32F4_GPIO_REMAP_TIM12_0, + STM32F4_GPIO_REMAP_TIM12_1, + STM32F4_GPIO_REMAP_MISC_0, + STM32F4_GPIO_REMAP_MISC_1, +} stm32f4_gpio_remap; + +typedef union { + struct { + uint32_t pin_first : 8; + uint32_t pin_last : 8; + uint32_t mode : 2; + uint32_t cnf : 2; + uint32_t output : 1; + uint32_t remap : 8; + uint32_t reserved : 3; + } fields; + + uint32_t value; +} stm32f4_gpio_config; + +#define STM32F4_GPIO_CONFIG_TERMINAL \ + { { 0xff, 0xff, 0x3, 0x3, 0x1, 0xff, 0x7 } } + +#endif /* STM32F4_FAMILY_F10XXX */ + extern const stm32f4_gpio_config stm32f4_start_config_gpio []; void stm32f4_gpio_set_clock(int pin, bool set); void stm32f4_gpio_set_config(const stm32f4_gpio_config *config); -#define STM32F4_GPIO_CONFIG_TERMINAL \ - { { 0xff, 0xff, 0x3, 0x1, 0x3, 0x3, 0x1, 0xf, 0xf } } - /** * @brief Sets the GPIO configuration of an array terminated by * STM32F4_GPIO_CONFIG_TERMINAL. @@ -127,6 +255,8 @@ void stm32f4_gpio_set_output(int pin, bool set); bool stm32f4_gpio_get_input(int pin); +#ifdef STM32F4_FAMILY_F4XXXX + #define STM32F4_PIN_USART(port, idx, altfunc) \ { \ { \ @@ -166,6 +296,58 @@ bool stm32f4_gpio_get_input(int pin); #define STM32F4_PIN_USART6_TX_PC6 STM32F4_PIN_USART(2, 6, STM32F4_GPIO_AF_USART6) #define STM32F4_PIN_USART6_RX_PC7 STM32F4_PIN_USART(2, 7, STM32F4_GPIO_AF_USART6) +#endif /* STM32F4_FAMILY_F4XXXX */ +#ifdef STM32F4_FAMILY_F10XXX + +#define STM32F4_PIN_USART_TX(port, idx, remapvalue) \ + { \ + { \ + .pin_first = STM32F4_GPIO_PIN(port, idx), \ + .pin_last = STM32F4_GPIO_PIN(port, idx), \ + .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \ + .cnf = STM32F4_GPIO_CNF_OUT_AF_PP, \ + .output = 0, \ + .remap = remapvalue \ + } \ + } + +#define STM32F4_PIN_USART_RX(port, idx, remapvalue) \ + { \ + { \ + .pin_first = STM32F4_GPIO_PIN(port, idx), \ + .pin_last = STM32F4_GPIO_PIN(port, idx), \ + .mode = STM32F4_GPIO_MODE_INPUT, \ + .cnf = STM32F4_GPIO_CNF_IN_FLOATING, \ + .output = 0, \ + .remap = remapvalue \ + } \ + } + +#define STM32F4_PIN_USART1_TX_MAP_0 STM32F4_PIN_USART_TX(0, 9, STM32F4_GPIO_REMAP_USART1_0) +#define STM32F4_PIN_USART1_RX_MAP_0 STM32F4_PIN_USART_RX(0, 10, STM32F4_GPIO_REMAP_USART1_0) +#define STM32F4_PIN_USART1_TX_MAP_1 STM32F4_PIN_USART_TX(1, 6, STM32F4_GPIO_REMAP_USART1_1) +#define STM32F4_PIN_USART1_RX_MAP_1 STM32F4_PIN_USART_RX(1, 7, STM32F4_GPIO_REMAP_USART1_1) + +#define STM32F4_PIN_USART2_TX_MAP_0 STM32F4_PIN_USART_TX(0, 2, STM32F4_GPIO_REMAP_USART2_0) +#define STM32F4_PIN_USART2_RX_MAP_0 STM32F4_PIN_USART_RX(0, 3, STM32F4_GPIO_REMAP_USART2_0) +#define STM32F4_PIN_USART2_TX_MAP_1 STM32F4_PIN_USART_TX(3, 5, STM32F4_GPIO_REMAP_USART2_1) +#define STM32F4_PIN_USART2_RX_MAP_1 STM32F4_PIN_USART_RX(3, 6, STM32F4_GPIO_REMAP_USART2_1) + +#define STM32F4_PIN_USART3_TX_MAP_0 STM32F4_PIN_USART_TX(1, 10, STM32F4_GPIO_REMAP_USART3_0) +#define STM32F4_PIN_USART3_RX_MAP_0 STM32F4_PIN_USART_RX(1, 11, STM32F4_GPIO_REMAP_USART3_0) +#define STM32F4_PIN_USART3_TX_MAP_1 STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_USART3_1) +#define STM32F4_PIN_USART3_RX_MAP_1 STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_USART3_1) +#define STM32F4_PIN_USART3_TX_MAP_3 STM32F4_PIN_USART_TX(3, 8, STM32F4_GPIO_REMAP_USART3_3) +#define STM32F4_PIN_USART3_RX_MAP_3 STM32F4_PIN_USART_RX(3, 9, STM32F4_GPIO_REMAP_USART3_3) + +#define STM32F4_PIN_UART4_TX STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_DONT_CHANGE) +#define STM32F4_PIN_UART4_RX STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_DONT_CHANGE) + +#define STM32F4_PIN_UART5_TX STM32F4_PIN_USART_TX(2, 12, STM32F4_GPIO_REMAP_DONT_CHANGE) +#define STM32F4_PIN_UART5_RX STM32F4_PIN_USART_RX(3, 2, STM32F4_GPIO_REMAP_DONT_CHANGE) + +#endif /* STM32F4_FAMILY_F10XXX */ + #ifdef __cplusplus } #endif /* __cplusplus */ |