diff options
Diffstat (limited to 'c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h')
| -rw-r--r-- | c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h | 199 |
1 files changed, 107 insertions, 92 deletions
diff --git a/c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h b/c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h index ddcd4ffde9..2a4d772dba 100644 --- a/c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h +++ b/c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2014 Andre Marques <andre.lousa.marques at gmail.com> + * Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com> * Copyright (c) 2013 Alan Cudmore. * * The license and distribution terms for this file may be @@ -68,15 +68,15 @@ #define BCM2835_TIMER_BASE (RPI_PERIPHERAL_BASE + 0xB400) -#define BCM2835_TIMER_LOD (BCM2835_TIMER_BASE+0x00) -#define BCM2835_TIMER_VAL (BCM2835_TIMER_BASE+0x04) -#define BCM2835_TIMER_CTL (BCM2835_TIMER_BASE+0x08) -#define BCM2835_TIMER_CLI (BCM2835_TIMER_BASE+0x0C) -#define BCM2835_TIMER_RIS (BCM2835_TIMER_BASE+0x10) -#define BCM2835_TIMER_MIS (BCM2835_TIMER_BASE+0x14) -#define BCM2835_TIMER_RLD (BCM2835_TIMER_BASE+0x18) -#define BCM2835_TIMER_DIV (BCM2835_TIMER_BASE+0x1C) -#define BCM2835_TIMER_CNT (BCM2835_TIMER_BASE+0x20) +#define BCM2835_TIMER_LOD (BCM2835_TIMER_BASE + 0x00) +#define BCM2835_TIMER_VAL (BCM2835_TIMER_BASE + 0x04) +#define BCM2835_TIMER_CTL (BCM2835_TIMER_BASE + 0x08) +#define BCM2835_TIMER_CLI (BCM2835_TIMER_BASE + 0x0C) +#define BCM2835_TIMER_RIS (BCM2835_TIMER_BASE + 0x10) +#define BCM2835_TIMER_MIS (BCM2835_TIMER_BASE + 0x14) +#define BCM2835_TIMER_RLD (BCM2835_TIMER_BASE + 0x18) +#define BCM2835_TIMER_DIV (BCM2835_TIMER_BASE + 0x1C) +#define BCM2835_TIMER_CNT (BCM2835_TIMER_BASE + 0x20) #define BCM2835_TIMER_PRESCALE 0xF9 @@ -90,19 +90,19 @@ #define BCM2835_GPIO_REGS_BASE (RPI_PERIPHERAL_BASE + 0x200000) -#define BCM2835_GPIO_GPFSEL1 (BCM2835_GPIO_REGS_BASE+0x04) -#define BCM2835_GPIO_GPSET0 (BCM2835_GPIO_REGS_BASE+0x1C) -#define BCM2835_GPIO_GPCLR0 (BCM2835_GPIO_REGS_BASE+0x28) -#define BCM2835_GPIO_GPLEV0 (BCM2835_GPIO_REGS_BASE+0x34) -#define BCM2835_GPIO_GPEDS0 (BCM2835_GPIO_REGS_BASE+0x40) -#define BCM2835_GPIO_GPREN0 (BCM2835_GPIO_REGS_BASE+0x4C) -#define BCM2835_GPIO_GPFEN0 (BCM2835_GPIO_REGS_BASE+0x58) -#define BCM2835_GPIO_GPHEN0 (BCM2835_GPIO_REGS_BASE+0x64) -#define BCM2835_GPIO_GPLEN0 (BCM2835_GPIO_REGS_BASE+0x70) -#define BCM2835_GPIO_GPAREN0 (BCM2835_GPIO_REGS_BASE+0x7C) -#define BCM2835_GPIO_GPAFEN0 (BCM2835_GPIO_REGS_BASE+0x88) -#define BCM2835_GPIO_GPPUD (BCM2835_GPIO_REGS_BASE+0x94) -#define BCM2835_GPIO_GPPUDCLK0 (BCM2835_GPIO_REGS_BASE+0x98) +#define BCM2835_GPIO_GPFSEL1 (BCM2835_GPIO_REGS_BASE + 0x04) +#define BCM2835_GPIO_GPSET0 (BCM2835_GPIO_REGS_BASE + 0x1C) +#define BCM2835_GPIO_GPCLR0 (BCM2835_GPIO_REGS_BASE + 0x28) +#define BCM2835_GPIO_GPLEV0 (BCM2835_GPIO_REGS_BASE + 0x34) +#define BCM2835_GPIO_GPEDS0 (BCM2835_GPIO_REGS_BASE + 0x40) +#define BCM2835_GPIO_GPREN0 (BCM2835_GPIO_REGS_BASE + 0x4C) +#define BCM2835_GPIO_GPFEN0 (BCM2835_GPIO_REGS_BASE + 0x58) +#define BCM2835_GPIO_GPHEN0 (BCM2835_GPIO_REGS_BASE + 0x64) +#define BCM2835_GPIO_GPLEN0 (BCM2835_GPIO_REGS_BASE + 0x70) +#define BCM2835_GPIO_GPAREN0 (BCM2835_GPIO_REGS_BASE + 0x7C) +#define BCM2835_GPIO_GPAFEN0 (BCM2835_GPIO_REGS_BASE + 0x88) +#define BCM2835_GPIO_GPPUD (BCM2835_GPIO_REGS_BASE + 0x94) +#define BCM2835_GPIO_GPPUDCLK0 (BCM2835_GPIO_REGS_BASE + 0x98) /** @} */ @@ -114,18 +114,18 @@ #define BCM2835_AUX_BASE (RPI_PERIPHERAL_BASE + 0x215000) -#define AUX_ENABLES (BCM2835_AUX_BASE+0x04) -#define AUX_MU_IO_REG (BCM2835_AUX_BASE+0x40) -#define AUX_MU_IER_REG (BCM2835_AUX_BASE+0x44) -#define AUX_MU_IIR_REG (BCM2835_AUX_BASE+0x48) -#define AUX_MU_LCR_REG (BCM2835_AUX_BASE+0x4C) -#define AUX_MU_MCR_REG (BCM2835_AUX_BASE+0x50) -#define AUX_MU_LSR_REG (BCM2835_AUX_BASE+0x54) -#define AUX_MU_MSR_REG (BCM2835_AUX_BASE+0x58) -#define AUX_MU_SCRATCH (BCM2835_AUX_BASE+0x5C) -#define AUX_MU_CNTL_REG (BCM2835_AUX_BASE+0x60) -#define AUX_MU_STAT_REG (BCM2835_AUX_BASE+0x64) -#define AUX_MU_BAUD_REG (BCM2835_AUX_BASE+0x68) +#define AUX_ENABLES (BCM2835_AUX_BASE + 0x04) +#define AUX_MU_IO_REG (BCM2835_AUX_BASE + 0x40) +#define AUX_MU_IER_REG (BCM2835_AUX_BASE + 0x44) +#define AUX_MU_IIR_REG (BCM2835_AUX_BASE + 0x48) +#define AUX_MU_LCR_REG (BCM2835_AUX_BASE + 0x4C) +#define AUX_MU_MCR_REG (BCM2835_AUX_BASE + 0x50) +#define AUX_MU_LSR_REG (BCM2835_AUX_BASE + 0x54) +#define AUX_MU_MSR_REG (BCM2835_AUX_BASE + 0x58) +#define AUX_MU_SCRATCH (BCM2835_AUX_BASE + 0x5C) +#define AUX_MU_CNTL_REG (BCM2835_AUX_BASE + 0x60) +#define AUX_MU_STAT_REG (BCM2835_AUX_BASE + 0x64) +#define AUX_MU_BAUD_REG (BCM2835_AUX_BASE + 0x68) /** @} */ @@ -137,24 +137,24 @@ #define BCM2835_UART0_BASE (RPI_PERIPHERAL_BASE + 0x201000) -#define BCM2835_UART0_DR (BCM2835_UART0_BASE+0x00) -#define BCM2835_UART0_RSRECR (BCM2835_UART0_BASE+0x04) -#define BCM2835_UART0_FR (BCM2835_UART0_BASE+0x18) -#define BCM2835_UART0_ILPR (BCM2835_UART0_BASE+0x20) -#define BCM2835_UART0_IBRD (BCM2835_UART0_BASE+0x24) -#define BCM2835_UART0_FBRD (BCM2835_UART0_BASE+0x28) -#define BCM2835_UART0_LCRH (BCM2835_UART0_BASE+0x2C) -#define BCM2835_UART0_CR (BCM2835_UART0_BASE+0x30) -#define BCM2835_UART0_IFLS (BCM2835_UART0_BASE+0x34) -#define BCM2835_UART0_IMSC (BCM2835_UART0_BASE+0x38) -#define BCM2835_UART0_RIS (BCM2835_UART0_BASE+0x3C) -#define BCM2835_UART0_MIS (BCM2835_UART0_BASE+0x40) -#define BCM2835_UART0_ICR (BCM2835_UART0_BASE+0x44) -#define BCM2835_UART0_DMACR (BCM2835_UART0_BASE+0x48) -#define BCM2835_UART0_ITCR (BCM2835_UART0_BASE+0x80) -#define BCM2835_UART0_ITIP (BCM2835_UART0_BASE+0x84) -#define BCM2835_UART0_ITOP (BCM2835_UART0_BASE+0x88) -#define BCM2835_UART0_TDR (BCM2835_UART0_BASE+0x8C) +#define BCM2835_UART0_DR (BCM2835_UART0_BASE + 0x00) +#define BCM2835_UART0_RSRECR (BCM2835_UART0_BASE + 0x04) +#define BCM2835_UART0_FR (BCM2835_UART0_BASE + 0x18) +#define BCM2835_UART0_ILPR (BCM2835_UART0_BASE + 0x20) +#define BCM2835_UART0_IBRD (BCM2835_UART0_BASE + 0x24) +#define BCM2835_UART0_FBRD (BCM2835_UART0_BASE + 0x28) +#define BCM2835_UART0_LCRH (BCM2835_UART0_BASE + 0x2C) +#define BCM2835_UART0_CR (BCM2835_UART0_BASE + 0x30) +#define BCM2835_UART0_IFLS (BCM2835_UART0_BASE + 0x34) +#define BCM2835_UART0_IMSC (BCM2835_UART0_BASE + 0x38) +#define BCM2835_UART0_RIS (BCM2835_UART0_BASE + 0x3C) +#define BCM2835_UART0_MIS (BCM2835_UART0_BASE + 0x40) +#define BCM2835_UART0_ICR (BCM2835_UART0_BASE + 0x44) +#define BCM2835_UART0_DMACR (BCM2835_UART0_BASE + 0x48) +#define BCM2835_UART0_ITCR (BCM2835_UART0_BASE + 0x80) +#define BCM2835_UART0_ITIP (BCM2835_UART0_BASE + 0x84) +#define BCM2835_UART0_ITOP (BCM2835_UART0_BASE + 0x88) +#define BCM2835_UART0_TDR (BCM2835_UART0_BASE + 0x8C) #define BCM2835_UART0_MIS_RX 0x10 #define BCM2835_UART0_MIS_TX 0x20 @@ -173,16 +173,16 @@ * @{ */ -#define BCM2835_I2C_BASE (0x20804000) +#define BCM2835_I2C_BASE (RPI_PERIPHERAL_BASE + 0x804000) -#define BCM2835_I2C_C (BCM2835_I2C_BASE+0x00) -#define BCM2835_I2C_S (BCM2835_I2C_BASE+0x04) -#define BCM2835_I2C_DLEN (BCM2835_I2C_BASE+0x08) -#define BCM2835_I2C_A (BCM2835_I2C_BASE+0x0C) -#define BCM2835_I2C_FIFO (BCM2835_I2C_BASE+0x10) -#define BCM2835_I2C_DIV (BCM2835_I2C_BASE+0x14) -#define BCM2835_I2C_DEL (BCM2835_I2C_BASE+0x18) -#define BCM2835_I2C_CLKT (BCM2835_I2C_BASE+0x1C) +#define BCM2835_I2C_C (BCM2835_I2C_BASE + 0x00) +#define BCM2835_I2C_S (BCM2835_I2C_BASE + 0x04) +#define BCM2835_I2C_DLEN (BCM2835_I2C_BASE + 0x08) +#define BCM2835_I2C_A (BCM2835_I2C_BASE + 0x0C) +#define BCM2835_I2C_FIFO (BCM2835_I2C_BASE + 0x10) +#define BCM2835_I2C_DIV (BCM2835_I2C_BASE + 0x14) +#define BCM2835_I2C_DEL (BCM2835_I2C_BASE + 0x18) +#define BCM2835_I2C_CLKT (BCM2835_I2C_BASE + 0x1C) /** @} */ @@ -192,14 +192,14 @@ * @{ */ -#define BCM2835_SPI_BASE (0x20204000) +#define BCM2835_SPI_BASE (RPI_PERIPHERAL_BASE + 0x204000) -#define BCM2835_SPI_CS (BCM2835_SPI_BASE+0x00) -#define BCM2835_SPI_FIFO (BCM2835_SPI_BASE+0x04) -#define BCM2835_SPI_CLK (BCM2835_SPI_BASE+0x08) -#define BCM2835_SPI_DLEN (BCM2835_SPI_BASE+0x0C) -#define BCM2835_SPI_LTOH (BCM2835_SPI_BASE+0x10) -#define BCM2835_SPI_DC (BCM2835_SPI_BASE+0x14) +#define BCM2835_SPI_CS (BCM2835_SPI_BASE + 0x00) +#define BCM2835_SPI_FIFO (BCM2835_SPI_BASE + 0x04) +#define BCM2835_SPI_CLK (BCM2835_SPI_BASE + 0x08) +#define BCM2835_SPI_DLEN (BCM2835_SPI_BASE + 0x0C) +#define BCM2835_SPI_LTOH (BCM2835_SPI_BASE + 0x10) +#define BCM2835_SPI_DC (BCM2835_SPI_BASE + 0x14) /** @} */ @@ -209,22 +209,22 @@ * @{ */ -#define BCM2835_I2C_SPI_BASE (0x20214000) - -#define BCM2835_I2C_SPI_DR (BCM2835_I2C_SPI_BASE+0x00) -#define BCM2835_I2C_SPI_RSR (BCM2835_I2C_SPI_BASE+0x04) -#define BCM2835_I2C_SPI_SLV (BCM2835_I2C_SPI_BASE+0x08) -#define BCM2835_I2C_SPI_CR (BCM2835_I2C_SPI_BASE+0x0C) -#define BCM2835_I2C_SPI_FR (BCM2835_I2C_SPI_BASE+0x10) -#define BCM2835_I2C_SPI_IFLS (BCM2835_I2C_SPI_BASE+0x14) -#define BCM2835_I2C_SPI_IMSC (BCM2835_I2C_SPI_BASE+0x18) -#define BCM2835_I2C_SPI_RIS (BCM2835_I2C_SPI_BASE+0x1C) -#define BCM2835_I2C_SPI_MIS (BCM2835_I2C_SPI_BASE+0x20) -#define BCM2835_I2C_SPI_ICR (BCM2835_I2C_SPI_BASE+0x24) -#define BCM2835_I2C_SPI_DMACR (BCM2835_I2C_SPI_BASE+0x28) -#define BCM2835_I2C_SPI_TDR (BCM2835_I2C_SPI_BASE+0x2C) -#define BCM2835_I2C_SPI_GPUSTAT (BCM2835_I2C_SPI_BASE+0x30) -#define BCM2835_I2C_SPI_HCTRL (BCM2835_I2C_SPI_BASE+0x34) +#define BCM2835_I2C_SPI_BASE (RPI_PERIPHERAL_BASE + 0x214000) + +#define BCM2835_I2C_SPI_DR (BCM2835_I2C_SPI_BASE + 0x00) +#define BCM2835_I2C_SPI_RSR (BCM2835_I2C_SPI_BASE + 0x04) +#define BCM2835_I2C_SPI_SLV (BCM2835_I2C_SPI_BASE + 0x08) +#define BCM2835_I2C_SPI_CR (BCM2835_I2C_SPI_BASE + 0x0C) +#define BCM2835_I2C_SPI_FR (BCM2835_I2C_SPI_BASE + 0x10) +#define BCM2835_I2C_SPI_IFLS (BCM2835_I2C_SPI_BASE + 0x14) +#define BCM2835_I2C_SPI_IMSC (BCM2835_I2C_SPI_BASE + 0x18) +#define BCM2835_I2C_SPI_RIS (BCM2835_I2C_SPI_BASE + 0x1C) +#define BCM2835_I2C_SPI_MIS (BCM2835_I2C_SPI_BASE + 0x20) +#define BCM2835_I2C_SPI_ICR (BCM2835_I2C_SPI_BASE + 0x24) +#define BCM2835_I2C_SPI_DMACR (BCM2835_I2C_SPI_BASE + 0x28) +#define BCM2835_I2C_SPI_TDR (BCM2835_I2C_SPI_BASE + 0x2C) +#define BCM2835_I2C_SPI_GPUSTAT (BCM2835_I2C_SPI_BASE + 0x30) +#define BCM2835_I2C_SPI_HCTRL (BCM2835_I2C_SPI_BASE + 0x34) /** @} */ @@ -262,13 +262,28 @@ */ #define BCM2835_GPU_TIMER_BASE (RPI_PERIPHERAL_BASE + 0x3000) -#define BCM2835_GPU_TIMER_CS (BCM2835_TIMER_BASE+0x00) -#define BCM2835_GPU_TIMER_CLO (BCM2835_TIMER_BASE+0x04) -#define BCM2835_GPU_TIMER_CHI (BCM2835_TIMER_BASE+0x08) -#define BCM2835_GPU_TIMER_C0 (BCM2835_TIMER_BASE+0x0C) -#define BCM2835_GPU_TIMER_C1 (BCM2835_TIMER_BASE+0x10) -#define BCM2835_GPU_TIMER_C2 (BCM2835_TIMER_BASE+0x14) -#define BCM2835_GPU_TIMER_C3 (BCM2835_TIMER_BASE+0x18) +#define BCM2835_GPU_TIMER_CS (BCM2835_TIMER_BASE + 0x00) +#define BCM2835_GPU_TIMER_CLO (BCM2835_TIMER_BASE + 0x04) +#define BCM2835_GPU_TIMER_CHI (BCM2835_TIMER_BASE + 0x08) +#define BCM2835_GPU_TIMER_C0 (BCM2835_TIMER_BASE + 0x0C) +#define BCM2835_GPU_TIMER_C1 (BCM2835_TIMER_BASE + 0x10) +#define BCM2835_GPU_TIMER_C2 (BCM2835_TIMER_BASE + 0x14) +#define BCM2835_GPU_TIMER_C3 (BCM2835_TIMER_BASE + 0x18) + +/** @} */ + +/** + * @name EMMC Registers + * + * @{ + */ + +/** + * NOTE: Since the SD controller follows the SDHCI standard, + * the rtems-libbsd tree already provides the remaining registers. + */ + +#define BCM2835_EMMC_BASE (RPI_PERIPHERAL_BASE + 0x300000) /** @} */ |